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ORCIDYu Cao 0001
Person information
- affiliation: Arizona State University, School of Electrical, Computer and Energy Engineering, Tempe, AZ, USA
- affiliation (PhD 2002): University of California, Berkeley, CA, USA
Other persons with the same name
- Yu Cao — disambiguation page
- Yu Cao 0002
![[0000-0001-8624-1099]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-8624-1099")
— University of Massachusetts, Lowell, MA, USA (and 3 more) - Yu Cao 0003 — IBM Almaden Research Center, San Jose, CA, USA (and 1 more)
- Yu Cao 0004 — Tsinghua Science Park, EMC Labs, Beijing, China
- Yu Cao 0005 — Duke University, Department of Mathematics, Durham, NC, USA (and 1 more)
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2020 – today
- 2020
[j40]Sumit K. Mandal, Gokul Krishnan, Chaitali Chakrabarti, Jae-Sun Seo, Yu Cao, Ümit Y. Ogras:
A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 362-375 (2020)- [j39]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo:
Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 424-437 (2020) - [j38]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo:
Performance Modeling for CNN Inference Accelerators on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 843-856 (2020) - [c71]Xiaocong Du, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao:
Noise-based Selection of Robust Inherited Model for Accurate Continual Learning. CVPR Workshops 2020: 983-988 - [c70]Gouranga Charan, Jubin Hazra, Karsten Beckmann, Xiaocong Du, Gokul Krishnan, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao:
Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation. DAC 2020: 1-6 - [c69]Zhenhua Zhu, Hanbo Sun, Kaizhong Qiu, Lixue Xia, Gokul Krishnan, Guohao Dai, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, Yuan Xie, Yu Wang, Huazhong Yang:
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems. ACM Great Lakes Symposium on VLSI 2020: 83-88 - [c68]Shreyas Kolala Venkataramanaiah, Xiaocong Du, Zheng Li, Shihui Yin, Yu Cao, Jae-sun Seo:
Efficient and Modularized Training on FPGA for Real-time Applications. IJCAI 2020: 5237-5239 - [c67]Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao:
Online Knowledge Acquisition with the Selective Inherited Model. IJCNN 2020: 1-7 - [c66]Zheng Li, Xiaocong Du, Yu Cao:
GAR: Graph Assisted Reasoning for Object Detection. WACV 2020: 1284-1293
2010 – 2019
- 2019
- [j37]Xiaocong Du, Zheng Li, Yufei Ma, Yu Cao:
Efficient Network Construction Through Structural Plasticity. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3): 453-464 (2019) - [j36]Jae-sun Seo, Yu Cao, Xin Li, Paul N. Whatmough:
Guest Editors' Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning. ACM J. Emerg. Technol. Comput. Syst. 15(2): 14:1-14:2 (2019) - [j35]Jae-Sun Seo, Yu Cao, Xin Li, Paul N. Whatmough:
Guest Editors' Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2). ACM J. Emerg. Technol. Comput. Syst. 15(4): 31:1-31:2 (2019) - [j34]Shihui Yin, Minkyu Kim, Deepak Kadetotad, Yang Liu, Chisung Bae, Sang Joon Kim, Yu Cao, Jae-sun Seo:
A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring. IEEE J. Solid State Circuits 54(8): 2316-2326 (2019) - [j33]Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Luning Wei, Xiaofei He, Yu Cao, Jae-sun Seo:
A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3843-3853 (2019) - [c65]Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo:
Automatic Compiler Based FPGA Accelerator for CNN Training. FPL 2019: 166-172 - [c64]Xiaocong Du, Gouranga Charan, Frank Liu, Yu Cao:
Single-Net Continual Learning with Progressive Segmented Training. ICMLA 2019: 1629-1636 - [i9]Xiaocong Du, Zheng Li, Yufei Ma, Yu Cao:
Efficient Network Construction through Structural Plasticity. CoRR abs/1905.11530 (2019) - [i8]Xiaocong Du, Zheng Li, Yu Cao:
CGaP: Continuous Growth and Pruning for Efficient Deep Learning. CoRR abs/1905.11533 (2019) - [i7]Xiaocong Du, Gouranga Charan, Frank Liu, Yu Cao:
Single-Net Continual Learning with Progressive Segmented Training (PST). CoRR abs/1905.11550 (2019) - [i6]Xiaocong Du, Gokul Krishnan, Abinash Mohanty, Zheng Li, Gouranga Charan, Yu Cao:
Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches. CoRR abs/1906.08866 (2019) - [i5]Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo:
Automatic Compiler Based FPGA Accelerator for CNN Training. CoRR abs/1908.06724 (2019) - [i4]Gokul Krishnan, Xiaocong Du, Yu Cao:
Structural Pruning in Deep Neural Networks: A Small-World Approach. CoRR abs/1911.04453 (2019) - 2018
- [j32]Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integr. 62: 14-23 (2018) - [j31]Yu Cao, Xin Li, Jae-sun Seo, Ganesh Dasika:
Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning. ACM J. Emerg. Technol. Comput. Syst. 14(2): 14:1-14:2 (2018) - [j30]Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim:
Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition. ACM J. Emerg. Technol. Comput. Syst. 14(4): 42:1-42:19 (2018) - [j29]Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1009-1022 (2018) - [j28]Robert D'Angelo, Xiaocong Du, Christopher D. Salthouse, Brent Hollosi, Geremy Freifeld, Wes Uy, Haiyao Huang, Nhut Tran, Armand Chery, Jae-sun Seo, Yu Cao, Dorothy C. Poppe, Sameer R. Sonkusale:
Process Scalability of Pulse-Based Circuits for Analog Image Convolution. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2929-2938 (2018) - [j27]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1354-1367 (2018) - [c63]Devyani Patra, Jiayang Zhang, Runsheng Wang, Mehdi Katoozi, Ethan H. Cannon, Ru Huang, Yu Cao:
Compact modeling and simulation of accelerated circuit aging. CICC 2018: 1-4 - [c62]Prad Kadambi, Abinash Mohanty, Hao Ren, Jaclyn Smith, Kevin McGuinnes, Kimberly Holt, Armin Furtwaengler, Roberto Slepetys, Zheng Yang, Jae-sun Seo, Junseok Chae, Yu Cao, Visar Berisha:
Towards a Wearable Cough Detector Based on Neural Networks. ICASSP 2018: 2161-2165 - [c61]Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. ICCAD 2018: 57 - [i3]Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, Ralph Etienne-Cummings:
Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain. CoRR abs/1805.08932 (2018) - 2017
- [j26]Zihan Xu, Steven Skorheim, Ming Tu, Visar Berisha, Shimeng Yu, Jae-sun Seo, Maxim Bazhenov, Yu Cao:
Improving efficiency in sparse learning with the feedforward inhibitory motif. Neurocomputing 267: 141-151 (2017) - [j25]Yu Cao, Xin Li, Taemin Kim, Suyog Gupta:
Guest Editors' Introduction: Hardware and Algorithms for On-Chip Learning. ACM J. Emerg. Technol. Comput. Syst. 13(3): 30:1-30:3 (2017) - [j24]Chengen Yang, Manqing Mao, Yu Cao, Chaitali Chakrabarti:
Cost-Effective Design Solutions for Enhancing PRAM Reliability and Performance. IEEE Trans. Multi Scale Comput. Syst. 3(1): 1-11 (2017) - [j23]Abinash Mohanty, Ketul B. Sutaria, Hiromitsu Awano, Takashi Sato, Yu Cao:
RTN in Scaled Transistors for On-Chip Random Seed Generation. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2248-2257 (2017) - [c60]Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo:
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ASP-DAC 2017: 21-22 - [c59]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. BioCAS 2017: 1-5 - [c58]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. FPGA 2017: 45-54 - [c57]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. FPL 2017: 1-8 - [c56]Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo:
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ISCAS 2017: 1-4 - [c55]Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
End-to-end scalable FPGA accelerator for deep residual networks. ISCAS 2017: 1-4 - [c54]Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim:
Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition. ISLPED 2017: 1-6 - [i2]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations. CoRR abs/1709.06206 (2017) - 2016
- [j22]Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 352-363 (2016) - [j21]Lixue Xia, Peng Gu, Boxun Li, Tianqi Tang, Xiling Yin, Wenqin Huangfu, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang:
Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication. J. Comput. Sci. Technol. 31(1): 3-19 (2016) - [j20]Naveen Suda, Jounghyuk Suh, Nagib Hakim, Yu Cao, Bertan Bakkaloglu:
A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 181-190 (2016) - [c53]Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation platform for memristor-based neuromorphic computing system. DATE 2016: 469-474 - [c52]Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA 2016: 16-25 - [c51]Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula:
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. FPL 2016: 1-8 - [c50]Ming Tu, Visar Berisha, Martin Woolf, Jae-sun Seo, Yu Cao:
Ranking the parameters of deep neural networks using the fisher information. ICASSP 2016: 2647-2651 - [c49]Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu:
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. ICCAD 2016: 15 - [c48]Dawei Zhou, Jingrui He, Yu Cao, Jae-sun Seo:
Bi-Level Rare Temporal Pattern Detection. ICDM 2016: 719-728 - [c47]Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:
High-performance face detection with CPU-FPGA acceleration. ISCAS 2016: 117-120 - [c46]Ayush Shrivastava, Pai-Yu Chen, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Design of a reliable RRAM-based PUF for compact hardware security primitives. ISCAS 2016: 2326-2329 - [c45]Ming Tu, Visar Berisha, Yu Cao, Jae-sun Seo:
Reducing the Model Order of Deep Neural Networks Using Information Theory. ISVLSI 2016: 93-98 - [i1]Ming Tu, Visar Berisha, Yu Cao, Jae-sun Seo:
Reducing the Model Order of Deep Neural Networks Using Information Theory. CoRR abs/1605.04859 (2016) - 2015
- [j19]Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo:
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 194-204 (2015) - [c44]Peng Gu, Boxun Li, Tianqi Tang, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang:
Technological exploration of RRAM crossbar array for matrix-vector multiplication. ASP-DAC 2015: 106-111 - [c43]Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. DATE 2015: 854-859 - [c42]Shimeng Yu, Yu Cao:
On-chip Sparse Learning with Resistive Cross-point Array Architecture. ACM Great Lakes Symposium on VLSI 2015: 195-197 - [c41]Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu:
Exploiting resistive cross-point array for compact design of physical unclonable function. HOST 2015: 26-31 - [c40]Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. ICCAD 2015: 194-199 - [c39]Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings. ICCD 2015: 359-366 - [c38]Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula:
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. ICCD 2015: 443-446 - [c37]Ketul B. Sutaria, Pengpeng Ren, Abinash Mohanty, Xixiang Feng, Runsheng Wang, Ru Huang, Yu Cao:
Duty cycle shift under static/dynamic aging in 28nm HK-MG technology. IRPS 2015: 7 - [c36]Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Programming strategies to improve energy efficiency and reliability of ReRAM memory systems. SiPS 2015: 1-6 - 2014
- [j18]Zihan Xu, Matteo Cavaliere, Pei An, Sarma B. K. Vrudhula, Yu Cao:
The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits. Fundam. Informaticae 134(1-2): 183-200 (2014) - [j17]Chengen Yang, Yunus Emre, Zihan Xu, Hsing Min Chen, Yu Cao, Chaitali Chakrabarti:
A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram. J. Signal Process. Syst. 76(2): 133-147 (2014) - [c35]Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao:
Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. BICA 2014: 126-133 - [c34]Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo:
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. BioCAS 2014: 536-539 - [c33]Manqing Mao, Chengen Yang, Zihan Xu, Yu Cao, Chaitali Chakrabarti:
Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems. SiPS 2014: 139-144 - 2013
- [j16]Shengqi Yang, Wenping Wang, Mark Hagan, Wei Zhang, Pallav Gupta, Yu Cao:
NBTI-aware circuit node criticality computation. ACM J. Emerg. Technol. Comput. Syst. 9(3): 23:1-23:19 (2013) - [j15]Jounghyuk Suh, Naveen Suda, Cheng Xu, Nagib Hakim, Yu Cao, Bertan Bakkaloglu:
Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1369-1380 (2013) - [c32]Min Chen, Vijay Reddy, Srikanth Krishnan, Jay Ondrusek, Yu Cao:
ACE: A robust variability and aging sensor for high-k/metal gate SoC. ESSDERC 2013: 182-185 - [c31]Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao:
Compact modeling of STT-MTJ for SPICE simulation. ESSDERC 2013: 338-341 - 2012
- [j14]Min Chen, Vijay Reddy, Srikanth Krishnan, Venkatesh Srinivasan, Yu Cao:
Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors. IEEE Des. Test Comput. 29(5): 18-26 (2012) - [j13]Chengen Yang, Yunus Emre, Yu Cao, Chaitali Chakrabarti:
Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding. EURASIP J. Adv. Signal Process. 2012: 211 (2012) - [c30]Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao:
Exploring sub-20nm FinFET design with predictive technology models. DAC 2012: 283-288 - [c29]Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao:
Hierarchical modeling of Phase Change memory for reliable design. ICCD 2012: 115-120 - [c28]Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao:
Design benchmarking to 7nm with FinFET predictive technology models. ISLPED 2012: 15-20 - [c27]Samatha Gummalla, Anupama R. Subramaniam, Yu Cao, Chaitali Chakrabarti:
An analytical approach to efficient circuit variability analysis in scaled CMOS design. ISQED 2012: 641-647 - [c26]Chengen Yang, Yunus Emre, Yu Cao, Chaitali Chakrabarti:
Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell PRAM. SiPS 2012: 114-119 - [c25]Yunus Emre, Chengen Yang, Ketul Sutaria, Yu Cao, Chaitali Chakrabarti:
Enhancing the Reliability of STT-RAM through Circuit and System Level Techniques. SiPS 2012: 125-130 - 2011
- [b1]Yu Cao:
Predictive Technology Model for Robust Nanoelectronic Design. Integrated Circuits and Systems, Springer 2011, ISBN 978-1-4614-0444-6, pp. 1-173 - [j12]Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang:
Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 615-628 (2011) - [j11]Yun Ye, Frank Liu, Min Chen, Sani R. Nassif, Yu Cao:
Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 987-996 (2011) - [c24]Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma, Huazhong Yang:
Circuit-level delay modeling considering both TDDB and NBTI. ISQED 2011: 14-21 - 2010
- [j10]Yu Cao, Frank Liu:
Guest Editors' Introduction: Compact Variability Modeling in Scaled CMOS Design. IEEE Des. Test Comput. 27(2): 6-7 (2010) - [j9]Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Frank Liu, Yu Cao:
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 173-183 (2010) - [j8]Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Chi-Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao:
Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 666-670 (2010) - [c23]Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark:
In-situ characterization and extraction of SRAM variability. DAC 2010: 711-716
2000 – 2009
- 2009
- [j7]Yu Cao, Asha Balijepalli, Saurabh Sinha, Chi-Chao Wang, Wenping Wang, Wei Zhao:
The Predictive Technology Model in the Late Silicon Era and Beyond. Found. Trends Electron. Des. Autom. 3(4): 305-401 (2009) - [j6]Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan:
New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components. Int. J. Parallel Program. 37(4): 417-431 (2009) - [j5]Min Chen, Wei Zhao, Frank Liu, Yu Cao:
Finite-Point-Based Transistor Model: A New Approach to Fast Circuit Simulation. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1470-1480 (2009) - [c22]Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan:
A framework for estimating NBTI degradation of microarchitectural components. ASP-DAC 2009: 455-460 - [c21]Yun Ye, Frank Liu, Min Chen, Yu Cao:
Variability analysis under layout pattern-dependent rapid-thermal annealing process. DAC 2009: 551-556 - [c20]Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang:
Gate replacement techniques for simultaneous leakage and aging optimization. DATE 2009: 328-333 - [c19]Chi-Chao Wang, Wei Zhao, Frank Liu, Min Chen, Yu Cao:
Modeling of layout-dependent stress effect in CMOS design. ICCAD 2009: 513-520 - [c18]Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang:
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power. ISQED 2009: 19-26 - 2008
- [j4]Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula:
Scalable model for predicting the effect of negative bias temperature instability for reliable design. IET Circuits Devices Syst. 2(4): 361-371 (2008) - [j3]Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar, Kenneth L. Shepard:
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. Proc. IEEE 96(2): 343-365 (2008) - [c17]Wenping Wang, Vijay Reddy, Bo Yang, Varsha Balakrishnan, Srikanth Krishnan, Yu Cao:
Statistical prediction of circuit aging under process variations. CICC 2008: 13-16 - [c16]Yun Ye, Frank Liu, Sani R. Nassif, Yu Cao:
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. DAC 2008: 900-905 - [c15]Xin Li, Yu Cao:
Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations. ISQED 2008: 108-113 - [c14]Wenping Wang, Shengqi Yang, Yu Cao:
Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect. ISQED 2008: 763-768 - [c13]Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra:
Optimized Circuit Failure Prediction for Aging: Practicality and Promise. ITC 2008: 1-10 - 2007
- [c12]Wenping Wang, Vijay Reddy, Anand T. Krishnan, Rakesh Vattikonda, Srikanth Krishnan, Yu Cao:
An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. CICC 2007: 511-514 - [c11]Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao:
The Impact of NBTI on the Performance of Combinational and Sequential Circuits. DAC 2007: 364-369 - [c10]Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao:
Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation. DAC 2007: 823-828 - [c9]Min Chen, Wei Zhao, Frank Liu, Yu Cao:
Fast statistical circuit analysis with finite-point based transistor model. DATE 2007: 1391-1396 - [c8]Wenping Wang, Zile Wei, Shengqi Yang, Yu Cao:
An efficient method to identify critical gates under circuit aging. ICCAD 2007: 735-740 - [c7]Rakesh Vattikonda, Yansheng Luo, Alex Gyure, Xiaoning Qi, Sam C. Lo, Mahmoud Shahram, Yu Cao, Kishore Singhal, Dino Toffolon:
A New Simulation Method for NBTI Analysis in SPICE Environment. ISQED 2007: 41-46 - 2006
- [j2]Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula:
Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. J. Low Power Electron. 2(2): 240-250 (2006) - [j1]Huifang Qin, Rakesh Vattikonda, Thuan Trinh, Yu Cao, Jan M. Rabaey:
SRAM Cell Optimization for Ultra-Low Power Standby. J. Low Power Electron. 2(3): 401-411 (2006) - [c6]