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ORCIDYu Cao 0001
Person information
- affiliation: Arizona State University, School of Electrical, Computer and Energy Engineering, Tempe, AZ, USA
- affiliation (PhD 2002): University of California, Berkeley, CA, USA
Other persons with the same name
- Yu Cao — disambiguation page
- Yu Cao 0002
![[0000-0001-8624-1099]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-8624-1099")
— University of Massachusetts, Lowell, MA, USA (and 3 more) - Yu Cao 0003 — IBM Almaden Research Center, San Jose, CA, USA (and 1 more)
- Yu Cao 0004 — Tsinghua Science Park, EMC Labs, Beijing, China
- Yu Cao 0005 — Duke University, Department of Mathematics, Durham, NC, USA (and 1 more)
- Yu Cao 0006 — Zhejiang University, Department of Land Management, School of Public Affairs, China (and 1 more)
- Yu Cao 0007 — University of Edinburgh, School of Engineering, UK (and 1 more)
- Yu Cao 0008 — Huazhong University of Science and Technology, School of Artificial Intelligence and Automation, Key Laboratory of Image Processing and Intelligent Control, Wuhan, China
- Yu Cao 0009 — Tianjin University, School of Marine Science and Technology, China
- Yu Cao 0010 — Shandong University, Institute of Materials Joining, Jinan, China
- Yu Cao 0011 — Zhejiang University, Department of Land Management, School of Public Affairs, Hangzhou, China
- Yu Cao 0012 — Baidu USA LLC, Sunnyvale, CA, USA
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2020 – today
- 2022
[i16]Sumit K. Mandal, Gokul Krishnan, A. Alper Goksoy, Gopikrishnan Ravindran Nair, Yu Cao, Ümit Y. Ogras:
COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks. CoRR abs/2205.07311 (2022)- 2021
- [j55]Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-Sun Seo, Ümit Y. Ogras, Yu Cao:
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks. ACM Trans. Embed. Comput. Syst. 20(5s): 68:1-68:24 (2021) - [c109]Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-Sun Seo, Ümit Y. Ogras, Yu Cao:
System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration. ASICON 2021: 1-4 - [c108]Yufei Ma, Gokul Krishnan, Yu Cao, Le Ye, Ru Huang:
SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA. FPGA 2021: 148 - [c107]Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo:
End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. FPL 2021: 76-82 - [c106]Han-Sok Suh, Jian Meng, Ty Nguyen, Shreyas K. Venkataramanaiah, Vijay Kumar, Yu Cao, Jae-sun Seo:
Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA. FPT 2021: 1-9 - [c105]Xiaocong Du, Bhargav Bhushanam, Jiecao Yu, Dhruv Choudhary, Tianxiang Gao, Sherman Wong, Louis Feng, Jongsoo Park, Yu Cao, Arun Kejariwal:
Alternate Model Growth and Pruning for Efficient Training of Recommendation Systems. ICMLA 2021: 1421-1428 - [c104]Xiaocong Du, Zheng Li, Jingbo Sun, Frank Liu, Yu Cao:
Evolutionary NAS in Light of Model Stability for Accurate Continual Learning. IJCNN 2021: 1-8 - [c103]Gokul Krishnan, Jingbo Sun, Jubin Hazra, Xiaocong Du, Maximilian Liehr, Zheng Li, Karsten Beckmann, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao:
Robust RRAM-based In-Memory Computing in Light of Model Stability. IRPS 2021: 1-5 - [i15]Adnan Siraj Rakin, Li Yang, Jingtao Li, Fan Yao, Chaitali Chakrabarti, Yu Cao, Jae-sun Seo, Deliang Fan:
RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy. CoRR abs/2103.13813 (2021) - [i14]Xiaocong Du, Bhargav Bhushanam, Jiecao Yu, Dhruv Choudhary, Tianxiang Gao, Sherman Wong, Louis Feng, Jongsoo Park, Yu Cao, Arun Kejariwal:
Alternate Model Growth and Pruning for Efficient Training of Recommendation Systems. CoRR abs/2105.01064 (2021) - [i13]Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao:
Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks. CoRR abs/2107.02358 (2021) - [i12]Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao:
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks. CoRR abs/2108.08903 (2021) - [i11]Jingbo Sun, Li Yang, Jiaxin Zhang, Frank Liu, Mahantesh Halappanavar, Deliang Fan, Yu Cao:
Gradient-based Novelty Detection Boosted by Self-supervised Binary Classification. CoRR abs/2112.09815 (2021) - 2020
- [j54]Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao:
Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs. IEEE Des. Test 37(6): 79-87 (2020) - [j53]Sumit K. Mandal, Gokul Krishnan, Chaitali Chakrabarti, Jae-Sun Seo, Yu Cao, Ümit Y. Ogras:
A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 362-375 (2020) - [j52]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo:
Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 424-437 (2020) - [j51]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo:
Performance Modeling for CNN Inference Accelerators on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 843-856 (2020) - [c102]Xiaocong Du, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao:
Noise-based Selection of Robust Inherited Model for Accurate Continual Learning. CVPR Workshops 2020: 983-988 - [c101]Gouranga Charan, Jubin Hazra, Karsten Beckmann, Xiaocong Du, Gokul Krishnan, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao:
Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation. DAC 2020: 1-6 - [c100]Li Yang, Zhezhi He, Yu Cao, Deliang Fan:
Non-uniform DNN Structured Subnets Sampling for Dynamic Inference. DAC 2020: 1-6 - [c99]Zhenhua Zhu, Hanbo Sun, Kaizhong Qiu, Lixue Xia, Gokul Krishnan, Guohao Dai, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, Yuan Xie, Yu Wang, Huazhong Yang:
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems. ACM Great Lakes Symposium on VLSI 2020: 83-88 - [c98]Shreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-Sun Seo:
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. ICCAD 2020: 74:1-74:8 - [c97]Zheng Li, Xiaocong Du, Yu Cao:
DAT-RNN: Trajectory Prediction with Diverse Attention. ICMLA 2020: 1512-1518 - [c96]Shreyas Kolala Venkataramanaiah, Xiaocong Du, Zheng Li, Shihui Yin, Yu Cao, Jae-sun Seo:
Efficient and Modularized Training on FPGA for Real-time Applications. IJCAI 2020: 5237-5239 - [c95]Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao:
Online Knowledge Acquisition with the Selective Inherited Model. IJCNN 2020: 1-7 - [c94]Shreyas K. Venkataramanaiah, Shihui Yin, Yu Cao, Jae-Sun Seo:
Deep Neural Network Training Accelerator Designs in ASIC and FPGA. ISOCC 2020: 21-22 - [c93]Zheng Li, Xiaocong Du, Yu Cao:
GAR: Graph Assisted Reasoning for Object Detection. WACV 2020: 1284-1293
2010 – 2019
- 2019
- [j50]Xiaocong Du, Zheng Li, Yufei Ma, Yu Cao:
Efficient Network Construction Through Structural Plasticity. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3): 453-464 (2019) - [j49]Jae-sun Seo, Yu Cao, Xin Li, Paul N. Whatmough:
Guest Editors' Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning. ACM J. Emerg. Technol. Comput. Syst. 15(2): 14:1-14:2 (2019) - [j48]Jae-Sun Seo, Yu Cao, Xin Li, Paul N. Whatmough:
Guest Editors' Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2). ACM J. Emerg. Technol. Comput. Syst. 15(4): 31:1-31:2 (2019) - [j47]Shihui Yin, Minkyu Kim, Deepak Kadetotad, Yang Liu, Chisung Bae, Sang Joon Kim, Yu Cao, Jae-sun Seo:
A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring. IEEE J. Solid State Circuits 54(8): 2316-2326 (2019) - [j46]Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Luning Wei, Xiaofei He, Yu Cao, Jae-sun Seo:
A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3843-3853 (2019) - [c92]Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo:
Automatic Compiler Based FPGA Accelerator for CNN Training. FPL 2019: 166-172 - [c91]Xiaocong Du, Gouranga Charan, Frank Liu, Yu Cao:
Single-Net Continual Learning with Progressive Segmented Training. ICMLA 2019: 1629-1636 - [i10]Xiaocong Du, Zheng Li, Yufei Ma, Yu Cao:
Efficient Network Construction through Structural Plasticity. CoRR abs/1905.11530 (2019) - [i9]Xiaocong Du, Zheng Li, Yu Cao:
CGaP: Continuous Growth and Pruning for Efficient Deep Learning. CoRR abs/1905.11533 (2019) - [i8]Xiaocong Du, Gouranga Charan, Frank Liu, Yu Cao:
Single-Net Continual Learning with Progressive Segmented Training (PST). CoRR abs/1905.11550 (2019) - [i7]Xiaocong Du, Gokul Krishnan, Abinash Mohanty, Zheng Li, Gouranga Charan, Yu Cao:
Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches. CoRR abs/1906.08866 (2019) - [i6]Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo:
Automatic Compiler Based FPGA Accelerator for CNN Training. CoRR abs/1908.06724 (2019) - [i5]Gokul Krishnan, Xiaocong Du, Yu Cao:
Structural Pruning in Deep Neural Networks: A Small-World Approach. CoRR abs/1911.04453 (2019) - 2018
- [j45]Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integr. 62: 14-23 (2018) - [j44]Yu Cao, Xin Li, Jae-sun Seo, Ganesh Dasika:
Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning. ACM J. Emerg. Technol. Comput. Syst. 14(2): 14:1-14:2 (2018) - [j43]Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim:
Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition. ACM J. Emerg. Technol. Comput. Syst. 14(4): 42:1-42:19 (2018) - [j42]Devyani Patra, Ahmed Kamal Reza, Mohammad Khaled Hassan, Mehdi Katoozi, Ethan H. Cannon, Kaushik Roy, Yu Cao:
Adaptive accelerated aging for 28 nm HKMG technology. Microelectron. Reliab. 80: 149-154 (2018) - [j41]Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1009-1022 (2018) - [j40]Robert D'Angelo, Xiaocong Du, Christopher D. Salthouse, Brent Hollosi, Geremy Freifeld, Wes Uy, Haiyao Huang, Nhut Tran, Armand Chery, Jae-sun Seo, Yu Cao, Dorothy C. Poppe, Sameer R. Sonkusale:
Process Scalability of Pulse-Based Circuits for Analog Image Convolution. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2929-2938 (2018) - [j39]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1354-1367 (2018) - [c90]Devyani Patra, Jiayang Zhang, Runsheng Wang, Mehdi Katoozi, Ethan H. Cannon, Ru Huang, Yu Cao:
Compact modeling and simulation of accelerated circuit aging. CICC 2018: 1-4 - [c89]Prad Kadambi, Abinash Mohanty, Hao Ren, Jaclyn Smith, Kevin McGuinnes, Kimberly Holt, Armin Furtwaengler, Roberto Slepetys, Zheng Yang, Jae-sun Seo, Junseok Chae, Yu Cao, Visar Berisha:
Towards a Wearable Cough Detector Based on Neural Networks. ICASSP 2018: 2161-2165 - [c88]Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. ICCAD 2018: 57 - [c87]Devyani Patra, Ahmed Kamal Reza, Mehdi Katoozi, Ethan H. Cannon, Kaushik Roy, Yu Cao:
Accelerated BTI degradation under stochastic TDDB effect. IRPS 2018: 5 - [c86]Lina J. Karam, Tejas S. Borkar, Yu Cao, Junseok Chae:
Generative Sensing: Transforming Unreliable Sensor Data for Reliable Recognition. MIPR 2018: 100-105 - [i4]Lina J. Karam, Tejas S. Borkar, Yu Cao, Junseok Chae:
Generative Sensing: Transforming Unreliable Sensor Data for Reliable Recognition. CoRR abs/1801.02684 (2018) - [i3]Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, Ralph Etienne-Cummings:
Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain. CoRR abs/1805.08932 (2018) - 2017
- [j38]Zihan Xu, Steven Skorheim, Ming Tu, Visar Berisha, Shimeng Yu, Jae-sun Seo, Maxim Bazhenov, Yu Cao:
Improving efficiency in sparse learning with the feedforward inhibitory motif. Neurocomputing 267: 141-151 (2017) - [j37]Yu Cao, Xin Li, Taemin Kim, Suyog Gupta:
Guest Editors' Introduction: Hardware and Algorithms for On-Chip Learning. ACM J. Emerg. Technol. Comput. Syst. 13(3): 30:1-30:3 (2017) - [j36]Chengen Yang, Manqing Mao, Yu Cao, Chaitali Chakrabarti:
Cost-Effective Design Solutions for Enhancing PRAM Reliability and Performance. IEEE Trans. Multi Scale Comput. Syst. 3(1): 1-11 (2017) - [j35]Abinash Mohanty, Ketul B. Sutaria, Hiromitsu Awano, Takashi Sato, Yu Cao:
RTN in Scaled Transistors for On-Chip Random Seed Generation. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2248-2257 (2017) - [c85]Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo:
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ASP-DAC 2017: 21-22 - [c84]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. BioCAS 2017: 1-5 - [c83]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. FPGA 2017: 45-54 - [c82]Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. FPL 2017: 1-8 - [c81]Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo:
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ISCAS 2017: 1-4 - [c80]Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
End-to-end scalable FPGA accelerator for deep residual networks. ISCAS 2017: 1-4 - [c79]Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim:
Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition. ISLPED 2017: 1-6 - [i2]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations. CoRR abs/1709.06206 (2017) - 2016
- [j34]Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 352-363 (2016) - [j33]Lixue Xia, Peng Gu, Boxun Li, Tianqi Tang, Xiling Yin, Wenqin Huangfu, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang:
Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication. J. Comput. Sci. Technol. 31(1): 3-19 (2016) - [j32]Naveen Suda, Jounghyuk Suh, Nagib Hakim, Yu Cao, Bertan Bakkaloglu:
A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 181-190 (2016) - [c78]Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation platform for memristor-based neuromorphic computing system. DATE 2016: 469-474 - [c77]Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA 2016: 16-25 - [c76]Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula:
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. FPL 2016: 1-8 - [c75]Ming Tu, Visar Berisha, Martin Woolf, Jae-sun Seo, Yu Cao:
Ranking the parameters of deep neural networks using the fisher information. ICASSP 2016: 2647-2651 - [c74]Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu:
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. ICCAD 2016: 15 - [c73]Dawei Zhou, Jingrui He, Yu Cao, Jae-sun Seo:
Bi-Level Rare Temporal Pattern Detection. ICDM 2016: 719-728 - [c72]Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:
High-performance face detection with CPU-FPGA acceleration. ISCAS 2016: 117-120 - [c71]Ayush Shrivastava, Pai-Yu Chen, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Design of a reliable RRAM-based PUF for compact hardware security primitives. ISCAS 2016: 2326-2329 - [c70]Ming Tu, Visar Berisha, Yu Cao, Jae-sun Seo:
Reducing the Model Order of Deep Neural Networks Using Information Theory. ISVLSI 2016: 93-98 - [i1]Ming Tu, Visar Berisha, Yu Cao, Jae-sun Seo:
Reducing the Model Order of Deep Neural Networks Using Information Theory. CoRR abs/1605.04859 (2016) - 2015
- [j31]Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo:
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 194-204 (2015) - [j30]Anupama R. Subramaniam, Janet Roveda, Yu Cao:
Finite-point method for efficient timing characterization of sequential elements. Integr. 49: 104-113 (2015) - [j29]Anupama R. Subramaniam, Janet Roveda, Yu Cao:
A Finite-Point Method for Efficient Gate Characterization Under Multiple Input Switching. ACM Trans. Design Autom. Electr. Syst. 21(1): 10:1-10:25 (2015) - [c69]Peng Gu, Boxun Li, Tianqi Tang, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang:
Technological exploration of RRAM crossbar array for matrix-vector multiplication. ASP-DAC 2015: 106-111 - [c68]Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. DATE 2015: 854-859 - [c67]Shimeng Yu, Yu Cao:
On-chip Sparse Learning with Resistive Cross-point Array Architecture. ACM Great Lakes Symposium on VLSI 2015: 195-197 - [c66]Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu:
Exploiting resistive cross-point array for compact design of physical unclonable function. HOST 2015: 26-31 - [c65]Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. ICCAD 2015: 194-199 - [c64]Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings. ICCD 2015: 359-366 - [c63]Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula:
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. ICCD 2015: 443-446 - [c62]Ketul B. Sutaria, Pengpeng Ren, Abinash Mohanty, Xixiang Feng, Runsheng Wang, Ru Huang, Yu Cao:
Duty cycle shift under static/dynamic aging in 28nm HK-MG technology. IRPS 2015: 7 - [c61]Runsheng Wang, Yu Cao:
Impact of temporal transistor variations on circuit reliability. ISCAS 2015: 2453-2456 - [c60]Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Programming strategies to improve energy efficiency and reliability of ReRAM memory systems. SiPS 2015: 1-6 - 2014
- [j28]Zihan Xu, Matteo Cavaliere, Pei An, Sarma B. K. Vrudhula, Yu Cao:
The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits. Fundam. Informaticae 134(1-2): 183-200 (2014) - [j27]Yu Cao, Jyothi Velamala, Ketul Sutaria, Mike Shuo-Wei Chen, Jonathan Ahlbin, Ivan Sanchez Esqueda, Michael Bajura, Michael Fritze:
Cross-Layer Modeling and Simulation of Circuit Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 8-23 (2014) - [j26]Chengen Yang, Yunus Emre, Zihan Xu, Hsing Min Chen, Yu Cao, Chaitali Chakrabarti:
A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram. J. Signal Process. Syst. 76(2): 133-147 (2014) - [c59]Xiaoming Chen, Yu Wang, Yu Cao, Huazhong Yang:
Statistical analysis of random telegraph noise in digital circuits. ASP-DAC 2014: 161-166 - [c58]Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao:
Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. BICA 2014: 126-133 - [c57]Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo:
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. BioCAS 2014: 536-539 - [c56]Ketul Sutaria, Athul Ramkumar, Rongjun Zhu, Renju Rajveev, Yao Ma, Yu Cao:
BTI-Induced Aging under Random Stress Waveforms: Modeling, Simulation and Silicon Validation. DAC 2014: 203:1-203:6 - [c55]Ketul Sutaria, Athul Ramkumar, Rongjun Zhu, Yu Cao:
Where is the Achilles Heel under Circuit Aging. ISVLSI 2014: 278-279 - [c54]Manqing Mao, Chengen Yang, Zihan Xu, Yu Cao, Chaitali Chakrabarti:
Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems. SiPS 2014: 139-144 - 2013
- [j25]Xiaoming Chen, Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang:
Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits. IET Circuits Devices Syst. 7(5): 273-282 (2013) - [j24]Shengqi Yang, Wenping Wang, Mark Hagan, Wei Zhang, Pallav Gupta, Yu Cao:
NBTI-aware circuit node criticality computation. ACM J. Emerg. Technol. Comput. Syst. 9(3): 23:1-23:19 (2013) - [j23]Jounghyuk Suh, Naveen Suda, Cheng Xu, Nagib Hakim, Yu Cao, Bertan Bakkaloglu:
Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1369-1380 (2013) - [c53]Min Chen, Vijay Reddy, Srikanth Krishnan, Jay Ondrusek, Yu Cao:
ACE: A robust variability and aging sensor for high-k/metal gate SoC. ESSDERC 2013: 182-185 - [c52]Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao:
Compact modeling of STT-MTJ for SPICE simulation. ESSDERC 2013: 338-341 - 2012
- [j22]Min Chen, Vijay Reddy, Srikanth Krishnan, Venkatesh Srinivasan, Yu Cao:
Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors. IEEE Des. Test Comput. 29(5): 18-26 (2012) - [j21]