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Salvatore Levantino
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2020 – today
- 2024
- [j60]Paolo Melillo
, Simone Zaffin
, Mauro Leoncini
, Alberto Brunero
, Alessandro Gasparini
, Salvatore Levantino
, Massimo Ghioni
:
A Wide-Input-Range Time-Based Buck Converter With Adaptive Gain and Continuous Phase Preset for Seamless PFM/PWM Transitions. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3436-3447 (2024) - [c68]Simone Mattia Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector. CICC 2024: 1-2 - [c67]Pietro Salvi, Simone Mattia Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Andrea L. Lacaita, Salvatore Levantino:
A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC. CICC 2024: 1-2 - [c66]Michele Rossoni, Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Riccardo Dell'Orto, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino:
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM. ISSCC 2024: 188-190 - [c65]Francesco Tesolin, Simone Mattia Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino:
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion. ISSCC 2024: 198-200 - 2023
- [j59]Mauro Leoncini
, Alessandro Bertolini
, Paolo Melillo, Salvatore Levantino, Massimo Ghioni:
Integration of loop gain measurement circuit for stability evaluation in DC/DC converters with time-based control. Integr. 90: 196-204 (2023) - [j58]Francesco Buccoleri
, Simone Mattia Dartizio
, Francesco Tesolin
, Luca Avallone
, Alessio Santiccioli
, Agata Iesurum
, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi
, Andrea Bevilacqua
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. IEEE J. Solid State Circuits 58(3): 634-646 (2023) - [j57]Francesco Tesolin
, Simone Mattia Dartizio
, Francesco Buccoleri
, Alessio Santiccioli
, Luca Bertulessi
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays. IEEE J. Solid State Circuits 58(9): 2466-2477 (2023) - [j56]Simone Mattia Dartizio
, Francesco Tesolin
, Giacomo Castoro
, Francesco Buccoleri
, Michele Rossoni, Dmytro Cherniak, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. IEEE J. Solid State Circuits 58(12): 3320-3337 (2023) - [j55]Giacomo Castoro
, Simone Mattia Dartizio
, Andrea L. Lacaita
, Salvatore Levantino
:
Phase Noise Analysis of Periodically ON/OFF Switched Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 54-63 (2023) - [c64]Paolo Melillo
, Mauro Leoncini
, Simone Zaffin, Alberto Brunero, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni:
A Compact Wide-Input-Range Time-Domain Buck Converter with Fast Transient Response for Industrial Applications. ESSCIRC 2023: 433-436 - [c63]Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Resson, Dmytro Cherniak, Luca Bertulessi
, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. ISSCC 2023: 78-79 - [c62]Giacomo Castoro, Simone Mattia Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi
, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology. ISSCC 2023: 82-83 - [c61]Paolo Melillo
, Simone Zaffin, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni:
Time-Based Buck Converter with Variable Frequency DCM and ON-Time Correction for Seamless Transitions. PRIME 2023: 205-208 - [c60]Luca Ricci, Lorenzo Scaletti
, Gabriele Bè
, Michele Rocco, Luca Bertulessi
, Salvatore Levantino, Andrea L. Lacaita, Carlo Samori, Andrea Bonfanti:
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j54]Mario Mercandelli
, Alessio Santiccioli
, Angelo Parisi
, Luca Bertulessi
, Dmytro Cherniak, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino
:
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. IEEE J. Solid State Circuits 57(2): 505-517 (2022) - [j53]Simone Mattia Dartizio
, Francesco Tesolin
, Mario Mercandelli
, Alessio Santiccioli
, Abanob Shehata
, Saleh Karman
, Luca Bertulessi
, Francesco Buccoleri
, Luca Avallone
, Angelo Parisi
, Andrea L. Lacaita
, Michael Peter Kennedy
, Carlo Samori
, Salvatore Levantino
:
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. IEEE J. Solid State Circuits 57(6): 1723-1735 (2022) - [j52]Alessandro Garghetti
, Andrea L. Lacaita
, David Seebacher
, Matteo Bassi
, Salvatore Levantino
:
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology. IEEE J. Solid State Circuits 57(6): 1788-1799 (2022) - [j51]Rabia Tugce Yazicigil
, Salvatore Levantino:
Special Section on the 47th IEEE European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 57(7): 1955-1956 (2022) - [j50]Simone Mattia Dartizio
, Francesco Buccoleri
, Francesco Tesolin
, Luca Avallone
, Alessio Santiccioli
, Agata Iesurum
, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi
, Andrea Bevilacqua
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. IEEE J. Solid State Circuits 57(12): 3538-3551 (2022) - [j49]Luca Bertulessi
, Dmytro Cherniak
, Mario Mercandelli
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 1858-1870 (2022) - [j48]Gabriele Bè
, Angelo Parisi
, Luca Bertulessi
, Luca Ricci, Lorenzo Scaletti
, Mario Mercandelli
, Andrea L. Lacaita
, Salvatore Levantino
, Carlo Samori
, Andrea Bonfanti
:
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3645-3649 (2022) - [c59]Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum
, Giovanni Steffan, Andrea Bevilacqua
, Luca Bertulessi
, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. CICC 2022: 1-2 - [c58]Salvatore Levantino:
Recent Advances in High-Performance Frequency Synthesizer Design. CICC 2022: 1-7 - [c57]Luca Ricci, Lorenzo Scaletti
, Gabriele Bè
, Luca Bertulessi
, Salvatore Levantino, Carlo Samori, Andrea Bonfanti:
Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs. ISCAS 2022: 900-904 - [c56]Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum
, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi
, Andrea Bevilacqua
, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino:
A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. ISSCC 2022: 1-3 - [c55]Lorenzo Scaletti
, Gabriele Bè
, Angelo Parisi, Luca Bertulessi
, Luca Ricci, Mario Mercandelli, Salvatore Levantino, Carlo Samori, Andrea Bonfanti:
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters. NEWCAS 2022: 20-24 - [c54]Alessandro Dago, Mauro Leoncini
, Alberto Cattani, Salvatore Levantino, Massimo Ghioni:
A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation. PRIME 2022: 81-84 - [c53]Mauro Leoncini
, Paolo Melillo, Alessandro Bertolini
, Salvatore Levantino, Massimo Ghioni:
Integrated Loop-Gain Measurement Circuit for DC/DC Boost Converters with Time-Based Control. PRIME 2022: 253-256 - [c52]Paolo Melillo, Alessandro Dago, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni:
A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters. PRIME 2022: 257-260 - [c51]Salvatore Levantino:
Frequency Synthesizers for 5G Applications. VLSI-SoC 2022: 1-4 - 2021
- [j47]Saleh Karman
, Francesco Tesolin
, Salvatore Levantino
, Carlo Samori
:
A Novel Topology of Coupled Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 989-997 (2021) - [j46]Luca Avallone
, Mario Mercandelli
, Alessio Santiccioli
, Michael Peter Kennedy
, Salvatore Levantino
, Carlo Samori
:
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2775-2786 (2021) - [c50]Mario Mercandelli, Luca Bertulessi
, Carlo Samori, Salvatore Levantino:
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter. A-SSCC 2021: 1-3 - [c49]Alessandro Garghetti, Andrea Leonardo Lacaita
, David Seebacher, Matteo Bassi, Salvatore Levantino:
A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS. CICC 2021: 1-2 - [c48]Mauro Leoncini, Alessandro Bertolini, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni:
An 800-mA Time-Based Boost Converter in 0.18µm BCD with Right-Half-Plane Zero Elimination and 96% Power Efficiency. ESSCIRC 2021: 223-226 - [c47]Andrea Bevilacqua
, Salvatore Levantino, Hua Wang:
Session 20 Overview: High-Performance VCOs Rf Subcommittee. ISSCC 2021: 292-293 - [c46]Mario Mercandelli
, Alessio Santiccioli, Simone Mattia Dartizio, Abanob Shehata
, Francesco Tesolin, Saleh Karman, Luca Bertulessi
, Francesco Buccoleri, Luca Avallone, Angelo Parisi
, Andrea Leonardo Lacaita
, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino:
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. ISSCC 2021: 445-447 - [c45]Alessio Santiccioli, Mario Mercandelli
, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata
, Luca Bertulessi
, Francesco Buccoleri, Luca Avallone, Angelo Parisi
, Dmytro Cherniak, Andrea L. Lacaita
, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino:
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. ISSCC 2021: 456-458 - 2020
- [j45]Alessio Santiccioli
, Mario Mercandelli
, Luca Bertulessi
, Angelo Parisi
, Dmytro Cherniak, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino
:
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking. IEEE J. Solid State Circuits 55(12): 3349-3361 (2020) - [j44]Luca Avallone
, Michael Peter Kennedy
, Saleh Karman
, Carlo Samori
, Salvatore Levantino
:
Jitter Minimization in Digital PLLs with Mid-Rise TDCs. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(3): 743-752 (2020) - [c44]Tommaso Rosa, Mauro Leoncini
, Salvatore Levantino, Massimo Ghioni:
A Novel Start-Up Technique for Time-Based Boost Converters with Seamless PFM/PWM Transition. ISCAS 2020: 1-5 - [c43]Alessio Santiccioli, Mario Mercandelli
, Luca Bertulessi
, Angelo Parisi
, Dmytro Cherniak, Andrea Leonardo Lacaita
, Carlo Samori, Salvatore Levantino:
17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. ISSCC 2020: 268-270 - [c42]Mario Mercandelli
, Alessio Santiccioli, Angelo Parisi
, Luca Bertulessi
, Dmytro Cherniak, Andrea Leonardo Lacaita
, Carlo Samori, Salvatore Levantino:
17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. ISSCC 2020: 274-276
2010 – 2019
- 2019
- [j43]Alessio Santiccioli
, Mario Mercandelli
, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino
:
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power. IEEE J. Solid State Circuits 54(11): 3149-3160 (2019) - [j42]Luca Bertulessi
, Saleh Karman
, Dmytro Cherniak, Alessandro Garghetti
, Carlo Samori, Andrea L. Lacaita
, Salvatore Levantino
:
A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. IEEE J. Solid State Circuits 54(12): 3493-3502 (2019) - [j41]Alessandro Garghetti
, Andrea L. Lacaita
, Salvatore Levantino
:
A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(5): 1737-1745 (2019) - [j40]Alessio Santiccioli
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3775-3785 (2019) - [c41]Dmytro Cherniak, Carlo Samori
, Salvatore Levantino:
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper). CICC 2019: 1-8 - [c40]Alessio Santiccioli, Mario Mercandelli
, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino:
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. CICC 2019: 1-4 - [c39]Luigi Grimaldi, Luca Bertulessi
, Saleh Karman
, Dmytro Cherniak, Alessandro Garghetti
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino:
A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS. ISSCC 2019: 268-270 - 2018
- [j39]Mario Mercandelli
, Luigi Grimaldi
, Luca Bertulessi
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A Background Calibration Technique to Control the Bandwidth of Digital PLLs. IEEE J. Solid State Circuits 53(11): 3243-3255 (2018) - [j38]Dmytro Cherniak
, Luigi Grimaldi
, Luca Bertulessi
, Roberto Nonis, Carlo Samori
, Salvatore Levantino
:
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation. IEEE J. Solid State Circuits 53(12): 3565-3575 (2018) - [j37]Paolo Maffezzoni
, Zheng Zhang
, Salvatore Levantino
, Luca Daniel:
Variation-Aware Modeling of Integrated Capacitors Based on Floating Random Walk Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2180-2184 (2018) - [j36]Dmytro Cherniak
, Carlo Samori
, Roberto Nonis, Salvatore Levantino
:
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 914-924 (2018) - [j35]Mauro Leoncini
, Andrea Bonfanti
, Salvatore Levantino
, Andrea L. Lacaita
:
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1968-1980 (2018) - [c38]Salvatore Levantino
:
Digital phase-locked loops. CICC 2018: 1-79 - [c37]Alessandro Garghetti
, Andrea L. Lacaita
, Salvatore Levantino:
A Single-Inductor Two-Step-Mixing Injection-Locked Frequency Divider by Four with Concurrent Tail-Injection. ICECS 2018: 349-352 - [c36]Dmytro Cherniak, Luigi Grimaldi, Carlo Samori
, Salvatore Levantino:
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators. ISCAS 2018: 1-5 - [c35]Alessandro Garghetti, Andrea L. Lacaita
, Salvatore Levantino:
A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique. ISCAS 2018: 1-4 - [c34]Alessandro Truppi, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino, Marco Ronchi, Marco Sosio:
Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers. ISCAS 2018: 1-4 - [c33]Tuan Minh Vo
, Carlo Samori
, Salvatore Levantino:
A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs. ISCAS 2018: 1-4 - [c32]Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi
, Carlo Samori
, Roberto Nonis, Salvatore Levantino
:
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation. ISSCC 2018: 248-250 - [c31]Luca Bertulessi
, Luigi Grimaldi, Dmytro Cherniak, Carlo Samori
, Salvatore Levantino
:
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range. ISSCC 2018: 252-254 - 2017
- [c30]Dmytro Chemiak, Salvatore Levantino
, Carlo Samori
, Roberto Nonis:
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars. ISCAS 2017: 1-4 - [c29]Tuan Minh Vo
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL. ISCAS 2017: 1-4 - 2016
- [j34]Salvatore Levantino
:
Introduction to the Special Section on the 2015 Radio Frequency Integrated Circuits Symposium. IEEE J. Solid State Circuits 51(5): 1064-1065 (2016) - [c28]Salvatore Levantino
:
Bang-bang digital PLLs. ESSCIRC 2016: 329-334 - 2015
- [j33]Salvatore Levantino
, Giovanni Marucci, Giovanni Marzin, Andrea Fenaroli, Carlo Samori
, Andrea L. Lacaita
:
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop. IEEE J. Solid State Circuits 50(11): 2678-2691 (2015) - 2014
- [j32]Salvatore Levantino
, Giovanni Marzin, Carlo Samori
:
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs. IEEE J. Solid State Circuits 49(8): 1762-1772 (2014) - [j31]Giovanni Marucci, Salvatore Levantino
, Paolo Maffezzoni, Carlo Samori
:
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 26-36 (2014) - [j30]Paolo Maffezzoni, Salvatore Levantino
:
Phase Noise of Pulse Injection-Locked Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2912-2919 (2014) - [c27]Giovanni Marzin, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
2.9 A Background calibration technique to control bandwidth in digital PLLs. ISSCC 2014: 54-55 - [c26]Giovanni Marucci, Andrea Fenaroli, Giovanni Marzin, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC. ISSCC 2014: 360-361 - 2013
- [j29]Federico Pepe
, Andrea Bonfanti
, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band. IEEE J. Solid State Circuits 48(10): 2375-2389 (2013) - [j28]Salvatore Levantino
, Giovanni Marzin, Carlo Samori
, Andrea L. Lacaita
:
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration. IEEE J. Solid State Circuits 48(10): 2419-2429 (2013) - [j27]Giovanni Marucci, Salvatore Levantino
, Paolo Maffezzoni, Carlo Samori
:
Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs. IEEE Trans. Circuits Syst. II Express Briefs 60-II(10): 632-636 (2013) - [c25]Salvatore Levantino
:
Advanced digital phase-locked loops. CICC 2013: 1-95 - [c24]Salvatore Levantino
, Carlo Samori
:
Nonlinearity cancellation in digital PLLs (Invited paper). CICC 2013: 1-8 - [c23]Giovanni Marzin, Andrea Fenaroli, Giovanni Marucci, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
A spur cancellation technique for MDLL-based frequency synthesizers. ISCAS 2013: 165-168 - [c22]Giovanni Marucci, Salvatore Levantino
, Paolo Maffezzoni, Carlo Samori
:
Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise. ISCAS 2013: 173-176 - [c21]Andrea Fenaroli, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
Background adaptive linearization of high-speed digital-to-analog Converters. ISCAS 2013: 582-585 - [c20]Giovanni Marucci, Salvatore Levantino
, Paolo Maffezzoni, Carlo Samori
:
An efficient method to compute phase-noise in injection-locked frequency dividers. ISCAS 2013: 1753-1756 - [c19]Federico Pepe
, Andrea Bonfanti
, Salvatore Levantino
, Paolo Maffezzoni, Carlo Samori
, Andrea L. Lacaita
:
Simulating phase noise induced from cyclostationary noise sources. ISCAS 2013: 2686-2689 - 2012
- [j26]Giovanni Marzin, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power. IEEE J. Solid State Circuits 47(12): 2974-2988 (2012) - [j25]Salvatore Levantino
, Paolo Maffezzoni:
Computing the Perturbation Projection Vector of Oscillators via Frequency Domain Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(10): 1499-1507 (2012) - [j24]Paolo Maffezzoni, Salvatore Levantino
:
Phase-Noise Analysis and Simulation of LC Oscillator-Based Injection-Locked Frequency Dividers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1925-1929 (2012) - [j23]Salvatore Levantino
, Paolo Maffezzoni, Federico Pepe
, Andrea Bonfanti
, Carlo Samori
, Andrea L. Lacaita
:
Efficient Calculation of the Impulse Sensitivity Function in Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 59-II(10): 628-632 (2012) - [j22]Paolo Maffezzoni, Salvatore Levantino
:
Analysis of VCO Phase Noise in Charge-Pump Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2165-2175 (2012) - [c18]Giovanni Marzin, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power. ISSCC 2012: 342-344 - 2011
- [j21]Marco Zanuso, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation. IEEE J. Solid State Circuits 46(3): 627-638 (2011) - [j20]Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power. IEEE J. Solid State Circuits 46(12): 2745-2758 (2011) - [j19]Davide Tasca, Marco Zanuso, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 200-204 (2011) - [c17]Paolo Maffezzoni, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
, Dario D'Amore, Mauro Santomauro:
Behavioral phase-noise analysis of charge-pump phase-locked loops. ECCTD 2011: 357-360 - [c16]Carlo Samori
, Marco Zanuso, Salvatore Levantino
, Andrea L. Lacaita
:
Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs. ISCAS 2011: 418-421 - [c15]Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power. ISSCC 2011: 88-90 - 2010
- [j18]Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita:
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic. EURASIP J. Embed. Syst. 2010 (2010) - [j17]Marco Zanuso, Paolo Madoglio, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(3): 548-555 (2010) - [j16]Salvatore Levantino
, Luca Collamati, Carlo Samori
, Andrea L. Lacaita
:
Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division. IEEE Trans. Circuits Syst. II Express Briefs 57-II(9): 671-675 (2010) - [c14]Marco Zanuso, Salvatore Levantino
, Alberto Puggelli, Carlo Samori
, Andrea L. Lacaita
:
Time-to-digital converter with 3-ps resolution and digital linearization algorithm. ESSCIRC 2010: 262-265 - [c13]Salvatore Levantino
, Marco Zanuso, Carlo Samori
, Andrea L. Lacaita
:
Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band. ISSCC 2010: 50-51 - [c12]Marco Zanuso, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation. ISSCC 2010: 476-477
2000 – 2009
- 2009
- [j15]Marco Zanuso, Davide Tasca, Salvatore Levantino
, Andrea Donadel, Carlo Samori
, Andrea L. Lacaita
:
Noise Analysis and Minimization in Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. II Express Briefs 56-II(11): 835-839 (2009) - [c11]Marco Zanuso, Salvatore Levantino
, Davide Tasca, Daniele Raiteri, Carlo Samori
, Andrea L. Lacaita
:
A glitch-corrector circuit for low-spur ADPLLs. ICECS 2009: 595-598 - [c10]Salvatore Levantino
, Marco Zanuso, Davide Tasca, Carlo Samori
, Andrea L. Lacaita
:
An all-digital architecture for low-jitter regulated delay lines. ICECS 2009: 603-606 - 2008
- [j14]Luigi Panseri, Luca Romanò, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
Low-Power Signal Component Separator for a 64-QAM 802.11 LINC Transmitter. IEEE J. Solid State Circuits 43(5): 1274-1286 (2008) - 2007
- [j13]Paolo Madoglio, Marco Zanuso, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
Quantization Effects in All-Digital Phase-Locked Loops. IEEE Trans. Circuits Syst. II Express Briefs 54-II(12): 1120-1124 (2007) - 2006
- [j12]Luca Romanò, Andrea Bonfanti
, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS. IEEE J. Solid State Circuits 41(11): 2457-2467 (2006) - [j11]Andrea Bonfanti
, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(3): 481-488 (2006) - [j10]Luca Romanò, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
Multiphase LC oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(7): 1579-1588 (2006) - [c9]Luigi Panseri, Luca Romanò, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter. CICC 2006: 133-136 - 2004
- [j9]Stefano Pellerano, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita
:
A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider. IEEE J. Solid State Circuits 39(2): 378-383 (2004) - [j8]Salvatore Levantino
, Luca Romanò, Stefano Pellerano, Carlo Samori
, Andrea L. Lacaita
:
Phase noise in digital frequency dividers. IEEE J. Solid State Circuits 39(5): 775-784 (2004) - [j7]Salvatore Levantino
, Marco Milani, Carlo Samori
, Andrea L. Lacaita
:
Fast-switching analog PLL with finite-impulse response. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(9): 1697-1701 (2004) - [c8]Luca Romanò, Carlo Samori, Salvatore Levantino, Andrea Bonfanti, Andrea L. Lacaita:
A multi-tank LC-oscillator [microwave oscillator example]. ICECS 2004: 29-32 - [c7]Salvatore Levantino, Andrea Bonfanti, Luca Romanò, Carlo Samori, Andrea L. Lacaita:
Differential tuning oscillators with reduced flicker noise upconversion. ICECS 2004: 33-36 - [c6]Luca Romanò, Salvatore Levantino, Andrea Bonfanti, Carlo Samori, Andrea L. Lacaita:
Phase noise and accuracy in quadrature oscillators. ISCAS (1) 2004: 161-164 - [c5]Salvatore Levantino, Luca Romanò, Carlo Samori, Andrea L. Lacaita:
Fast-switching analog PLL with finite-impulse response. ISCAS (4) 2004: 165-168 - 2003
- [j6]Salvatore Levantino
, Carlo Samori
, Mihai Banu, Jack P. F. Glas, Vito Boccuzzi:
A CMOS GSM IF-sampling circuit with reduced in-channel aliasing. IEEE J. Solid State Circuits 38(6): 895-904 (2003) - [j5]Sander L. J. Gierkink, Salvatore Levantino
, Robert C. Frye, Carlo Samori
, Vito Boccuzzi:
A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling. IEEE J. Solid State Circuits 38(7): 1148-1154 (2003) - [c4]Andrea Giovanni Bonfanti
, Salvatore Levantino
, Stefano Pellerano, Carlo Samori
, Andrea L. Lacaita
, Felice Torrisi
:
A voltage-controlled oscillator for IEEE 802.11a and HiperLAN2 application. ESSCIRC 2003: 695-698 - 2002
- [j4]Carlo Samori
, Salvatore Levantino
, Andrea L. Lacaita
:
Integrated LC oscillators for frequency synthesis in wireless applications. IEEE Commun. Mag. 40(5): 166-171 (2002) - [j3]Salvatore Levantino
, Carlo Samori
, Andrea Bonfanti
, Sander L. J. Gierkink, Andrea L. Lacaita
, Vito Boccuzzi:
Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion. IEEE J. Solid State Circuits 37(8): 1003-1011 (2002) - 2001
- [j2]Alfio Zanchi, Carlo Samori
, Salvatore Levantino
, Andrea L. Lacaita
:
A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop. IEEE J. Solid State Circuits 36(4): 611-619 (2001) - [c3]Carlo Samori, Salvatore Levantino, Vito Boccuzzi:
A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications. CICC 2001: 201-204 - [c2]Alfio Zanchi, Andrea Bonfanti, Salvatore Levantino
, Carlo Samori
, Andrea L. Lacaita:
Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCO. CICC 2001: 209-212 - 2000
- [j1]Carlo Samori
, Andrea L. Lacaita
, Alfio Zanchi, Salvatore Levantino
, Giovanni Calí:
Phase noise degradation at high oscillation amplitudes in LC-tuned VCO's. IEEE J. Solid State Circuits 35(1): 96-99 (2000) - [c1]Salvatore Levantino, Alfio Zanchi, Andrea Bonfanti, Carlo Samori:
Fast simulation techniques for phase noise analysis of oscillators. ISCAS 2000: 156-159
Coauthor Index
aka: Andrea Giovanni Bonfanti
aka: Andrea Leonardo Lacaita
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