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Joseph F. Ryan 0002
Person information
- affiliation: University of Virginia
Other persons with the same name
- Joseph F. Ryan 0001 (aka: Joe Ryan 0001) — The University of Newcastle, Australia
- Joseph F. Ryan 0003 — University of Florida, St Augustine, FL, USA (and 2 more)
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2010 – 2019
- 2019
- [j3]Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - 2018
- [c9]Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40 - 2016
- [j2]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. IEEE J. Solid State Circuits 51(1): 18-30 (2016) - 2015
- [c8]Alicia Klinefelter, Joseph F. Ryan, James W. Tschanz, Benton H. Calhoun:
Error-energy analysis of hardware logarithmic approximation methods for low power applications. ISCAS 2015: 2361-2364 - [c7]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. ISSCC 2015: 1-3 - 2014
- [c6]Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De:
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC 2014: 108-109 - 2011
- [c5]Joseph F. Ryan, Sudhanshu Khanna, Benton H. Calhoun:
An analytical model for performance yield of nanoscale SRAM accounting for the sense amplifier strobe signal. ISLPED 2011: 297-302 - 2010
- [j1]Benton H. Calhoun, Joseph F. Ryan, Sudhanshu Khanna, Mateja Putic, John C. Lach:
Flexible Circuits and Architectures for Ultralow Power. Proc. IEEE 98(2): 267-282 (2010) - [c4]Joseph F. Ryan, Benton H. Calhoun:
A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS. CICC 2010: 1-4 - [c3]Benton H. Calhoun, Sudhanshu Khanna, Yanqing Zhang, Joseph F. Ryan, Brian P. Otis:
System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms. ISCAS 2010: 269-272
2000 – 2009
- 2008
- [c2]Joseph F. Ryan, Benton H. Calhoun:
Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation. ISQED 2008: 127-132 - 2007
- [c1]Joseph F. Ryan, Jiajing Wang, Benton H. Calhoun:
Analyzing and modeling process balance for sub-threshold circuit design. ACM Great Lakes Symposium on VLSI 2007: 275-280
Coauthor Index
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