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Younghyun Lim
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2020 – today
- 2024
- [j11]Juyeop Kim
, Yongwoo Jo
, Hangi Park
, Taeho Seong
, Younghyun Lim
, Jaehyouk Choi
:
A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation. IEEE J. Solid State Circuits 59(2): 424-434 (2024) - 2023
- [j10]Yongwoo Jo
, Juyeop Kim
, Yuhwan Shin
, Hangi Park
, Chanwoong Hwang
, Younghyun Lim
, Jaehyouk Choi
:
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier. IEEE J. Solid State Circuits 58(12): 3338-3350 (2023) - 2022
- [j9]Younghyun Lim
, Juyeop Kim
, Yongwoo Jo
, Jooeun Bang
, Jaehyouk Choi
:
A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop. IEEE J. Solid State Circuits 57(2): 480-491 (2022) - 2021
- [j8]Seyeon Yoo
, Seojin Choi
, Yongsun Lee
, Taeho Seong
, Younghyun Lim
, Jaehyouk Choi
:
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator. IEEE J. Solid State Circuits 56(1): 298-309 (2021) - [c10]Juyeop Kim
, Yongwoo Jo
, Younghyun Lim
, Taeho Seong, Hangi Park, Seyeon Yoo, Yongsun Lee, Seojin Choi, Jaehyouk Choi:
32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique. ISSCC 2021: 448-450 - 2020
- [c9]Younghyun Lim
, Juyeop Kim
, Yongwoo Jo
, Jooeun Bang
, Seyeon Yoo, Hangi Park, Heein Yoon, Jaehyouk Choi:
17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator. ISSCC 2020: 280-282
2010 – 2019
- 2019
- [j7]Seojin Choi
, Seyeon Yoo
, Yongsun Lee
, Yongwoo Jo
, Jeonghyun Lee
, Younghyun Lim
, Jaehyouk Choi
:
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114. IEEE J. Solid State Circuits 54(4): 927-936 (2019) - [j6]Juyeop Kim
, Younghyun Lim
, Heein Yoon
, Yongsun Lee
, Hangi Park
, Yoonseo Cho
, Taeho Seong
, Jaehyouk Choi
:
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators. IEEE J. Solid State Circuits 54(12): 3466-3477 (2019) - [c8]Juyeop Kim
, Heein Yoon, Younghyun Lim
, Yongsun Lee, Yoonseo Cho, Taeho Seong, Jaehyouk Choi:
A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization. ISSCC 2019: 258-260 - [c7]Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim
, Jaehyouk Choi:
A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator. ISSCC 2019: 490-492 - [c6]Jeonghyun Lee
, Jooeun Bang
, Younghyun Lim
, Jaehyouk Choi:
A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer. VLSI Circuits 2019: 130- - 2018
- [j5]Kyoohyun Lim
, Sanghoon Lee, Yongha Lee, Byeongmoo Moon, Hwahyeong Shin, Kisub Kang, Seungbeom Kim, Jinhyeok Lee, Hyungsuk Lee, Hyunchul Shim, Chulhoon Sung, Kumyoung Park, Garam Lee, Minjung Kim, Seokyeong Park, Hyosun Jung, Younghyun Lim
, Changhun Song, Jaehyeon Seong, Heechang Cho, Jaehyouk Choi
, Jong-Ryul Lee, Sangwoo Han:
A 65-nm CMOS 2×2 MIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations. IEEE J. Solid State Circuits 53(7): 1960-1976 (2018) - [j4]Younghyun Lim
, Jeonghyun Lee
, Suneui Park, Yongwoo Jo
, Jaehyouk Choi
:
An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique. IEEE J. Solid State Circuits 53(9): 2675-2685 (2018) - [c5]Younghyun Lim
, Jeonghyun Lee
, Suneui Park, Jaehyouk Choi
:
An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate. ASP-DAC 2018: 299-300 - [c4]Younghyun Lim
, Jeonghyun Lee
, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi:
A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector. ESSCIRC 2018: 210-213 - [c3]Heein Yoon, Juyeop Kim
, Suneui Park, Younghyun Lim
, Yongsun Lee, Jooeun Bang
, Kyoohyun Lim, Jaehyouk Choi
:
A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers. ISSCC 2018: 366-368 - [c2]Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo
, Jeonghyun Lee, Younghyun Lim
, Jaehyouk Choi:
153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier. VLSI Circuits 2018: 185-186 - 2017
- [j3]Younghyun Lim
, Jeonghyun Lee
, Yongsun Lee, Seong-Sik Song, Hong-Teuk Kim, Ockgoo Lee
, Jaehyouk Choi
:
An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3006-3018 (2017) - [c1]Younghyun Lim
, Jeonghyun Lee
, Suneui Park, Jaehyouk Choi
:
An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate. CICC 2017: 1-4 - 2016
- [j2]Heein Yoon
, Yongsun Lee, Younghyun Lim
, Geum-Young Tak, Hong-Teuk Kim, Yo-Chuol Ho, Jaehyouk Choi
:
A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers. IEEE J. Solid State Circuits 51(3): 614-625 (2016) - [j1]Seojin Choi, Seyeon Yoo, Younghyun Lim
, Jaehyouk Choi
:
A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector. IEEE J. Solid State Circuits 51(8): 1878-1889 (2016)
Coauthor Index
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last updated on 2024-04-24 23:03 CEST by the dblp team
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