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2020 – today
- 2021
[j26]Tania Cerquitelli, Daniele Jahier Pagliari, Andrea Calimera, Lorenzo Bottaccioli, Edoardo Patti, Andrea Acquaviva, Massimo Poncino:
Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools. Proc. IEEE 109(4): 399-422 (2021)- [j25]Luca Mocerino
, Andrea Calimera:
Fast and Accurate Inference on Microcontrollers With Boosted Cooperative Convolutional Neural Networks (BC-Net). IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 77-88 (2021) - [j24]Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera:
TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 672-676 (2021) - 2020
- [j23]Roberto Giorgio Rizzo, Andrea Calimera, Jun Zhou:
Corrigendum to"Approximate error detection-correction for efficient adaptive voltage Over-Scaling"[Integration 63 (2018) 220-231]. Integr. 70: 159 (2020) - [j22]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 397-410 (2020) - [c76]Matteo Grimaldi, Valentino Peluso, Andrea Calimera:
EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets. AICAS 2020: 233-237 - [c75]Luca Mocerino, Andrea Calimera:
TentacleNet: A Pseudo-Ensemble Template for Accurate Binary Convolutional Neural Networks. AICAS 2020: 261-265 - [c74]Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia:
Enabling monocular depth perception at the very edge. CVPR Workshops 2020: 1581-1583 - [c73]Valentino Peluso, Enrico Macii, Andrea Calimera:
Optimization Tools for ConvNets on the Edge. VLSI-SOC 2020: 204-205
2010 – 2019
- 2019
- [j21]Matteo Grimaldi, Valentino Peluso, Andrea Calimera:
Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores. IEEE Access 7: 152599-152611 (2019) - [j20]Matteo Grimaldi, Valerio Tenace, Andrea Calimera:
Layer-Wise Compressive Training for Convolutional Neural Networks. Future Internet 11(1): 7 (2019) - [c72]Valerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera:
SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. DATE 2019: 372-377 - [c71]Luca Mocerino, Valerio Tenace, Andrea Calimera:
Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse. DATE 2019: 848-853 - [c70]Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Stefano Mattoccia:
Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based Platforms. DATE 2019: 1703-1708 - [c69]Luca Mocerino, Andrea Calimera:
CoopNet: Cooperative Convolutional Neural Network for Low-Power MCUs. ICECS 2019: 414-417 - [c68]Valentino Peluso, Antonio Cipolletta, Francesco Vaiana, Andrea Calimera:
Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores. ICECS 2019: 598-601 - [c67]Valentino Peluso, Roberto Giorgio Rizzo, Antonio Cipolletta, Andrea Calimera:
Inference on the Edge: Performance Analysis of an Image Classification Task Using Off-The-Shelf CPUs and Open-Source ConvNets. SNAMS 2019: 454-459 - [c66]Valentino Peluso, Matteo Grimaldi, Andrea Calimera:
Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT Processors. VLSI-SoC 2019: 142-147 - [i3]Luca Mocerino, Andrea Calimera:
CoopNet: Cooperative Convolutional Neural Network for Low-Power MCUs. CoRR abs/1911.08606 (2019) - [i2]Matteo Grimaldi, Valentino Peluso, Andrea Calimera:
EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets. CoRR abs/1912.10087 (2019) - [i1]Luca Mocerino, Andrea Calimera:
TentacleNet: A Pseudo-Ensemble Template for Accurate Binary Convolutional Neural Networks. CoRR abs/1912.10103 (2019) - 2018
- [j19]Roberto Giorgio Rizzo, Andrea Calimera, Jun Zhou:
Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling. Integr. 63: 220-231 (2018) - [j18]Valerio Tenace, Andrea Calimera:
Quasi-exact logic functions through classification trees. Integr. 63: 248-255 (2018) - [c65]Daniele Jahier Pagliari, Valentino Peluso, Yukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino:
All-digital embedded meters for on-line power estimation. DATE 2018: 737-742 - [c64]Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto:
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator. DATE 2018: 1151-1154 - [c63]Matteo Grimaldi, Federico Pugliese, Valerio Tenace, Andrea Calimera:
A compression-driven training framework for embedded deep neural networks. INTESA@ESWEEK 2018: 45-50 - [c62]Valentino Peluso, Andrea Calimera:
Scalable-effort ConvNets for multilevel classification. ICCAD 2018: 12 - [c61]Marco Vacca, Yaswanth Tavva, Anupam Chattopadhyay, Andrea Calimera:
Logic-In-Memory Architecture For Min/Max Search. ICECS 2018: 853-856 - [c60]Valentino Peluso, Andrea Calimera:
Weak-MAC: Arithmetic Relaxation for Dynamic Energy-Accuracy Scaling in ConvNets. ISCAS 2018: 1-5 - [c59]Roberto Giorgio Rizzo, Valerio Tenace, Andrea Calimera:
Multiplication by Inference using Classification Trees: A Case-Study Analysis. ISCAS 2018: 1-5 - [c58]Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto:
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS. ISCAS 2018: 1-5 - [c57]Valentino Peluso, Andrea Calimera:
Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis. VLSI-SoC (Selected Papers) 2018: 107-127 - [c56]Valentino Peluso, Andrea Calimera:
Energy-Driven Precision Scaling for Fixed-Point ConvNets. VLSI-SoC 2018: 113-118 - [c55]Valerio Tenace, Andrea Calimera:
Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits. VLSI-SoC 2018: 149-154 - 2017
- [c54]Valerio Tenace, Andrea Calimera:
Activation-Kernel Extraction through Machine Learning. NGCAS 2017: 5-8 - [c53]Roberto Giorgio Rizzo, Andrea Calimera:
Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling. NGCAS 2017: 13-16 - [c52]Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou, Xin Liu:
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS. VLSI-SoC 2017: 1-6 - [c51]Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou:
On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling. VLSI-SoC (Selected Papers) 2017: 153-177 - 2016
- [j17]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs. IEEE Trans. Circuits Syst. II Express Briefs 63-II(12): 1111-1115 (2016) - [c50]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture. ACM Great Lakes Symposium on VLSI 2016: 145-150 - [c49]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. ISCAS 2016: 2897 - [c48]Valentino Peluso, Andrea Calimera, Enrico Macii, Massimo Alioto:
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs. VLSI-SoC 2016: 1-6 - [c47]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. VLSI-SoC 2016: 1-6 - [c46]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits. VLSI-SoC (Selected Papers) 2016: 60-82 - [c45]Valentino Peluso, Roberto Giorgio Rizzo, Andrea Calimera, Enrico Macii, Massimo Alioto:
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping. VLSI-SoC (Selected Papers) 2016: 152-172 - 2015
- [j16]Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Ultra-low power circuits using graphene p-n junctions and adiabatic computing. Microprocess. Microsystems 39(8): 962-972 (2015) - [c44]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. DAC 2015: 128:1-128:6 - [c43]Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. ACM Great Lakes Symposium on VLSI 2015: 39-44 - [c42]Yukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino:
Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores. ACM Great Lakes Symposium on VLSI 2015: 75-78 - [c41]Roberto Giorgio Rizzo, Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino:
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. ACM Great Lakes Symposium on VLSI 2015: 253-258 - [c40]Daniele Jahier Pagliari, Andrea Calimera, Enrico Macii, Massimo Poncino:
An automated design flow for approximate circuits based on reduced precision redundancy. ICCD 2015: 86-93 - [c39]Felipe Lavratti, Letícia Maria Bolzani Poehls, Fabian Vargas, Andrea Calimera, Enrico Macii:
Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs. VLSI Design 2015: 405-410 - 2014
- [j15]Sandeep Miryala, Matheus Oleiro, Letícia Maria Bolzani Pöhls, Andrea Calimera, Enrico Macii, Massimo Poncino:
Modeling of Physical Defects in PN Junction Based Graphene Devices. J. Electron. Test. 30(3): 357-370 (2014) - [j14]Valerio Tenace, Sandeep Miryala, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Row-based body-bias assignment for dynamic thermal clock-skew compensation. Microelectron. J. 45(5): 530-538 (2014) - [j13]Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino:
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 251-264 (2014) - [c38]Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
Pass-XNOR logic: A new logic style for P-N junction based graphene circuits. DATE 2014: 1-4 - [c37]Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino:
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. DSD 2014: 365-371 - 2013
- [j12]Alessandro Sassone, Wei Liu, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs. Microelectron. J. 44(11): 970-976 (2013) - [j11]Wei Liu, Andrea Calimera, Alberto Macii, Enrico Macii, Alberto Nannarelli, Massimo Poncino:
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 406-418 (2013) - [c36]Andrea Calimera, Enrico Macii, Massimo Poncino:
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints. DAC 2013: 110:1-110:6 - [c35]Sandeep Miryala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii, Massimo Poncino:
A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. DATE 2013: 877-880 - [c34]Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino:
Delay model for reconfigurable logic gates based on graphene PN-junctions. ACM Great Lakes Symposium on VLSI 2013: 227-232 - [c33]Sandeep Miryala, Andrea Calimera, Massimo Poncino, Enrico Macii:
Exploration of different implementation styles for graphene-based reconfigurable gates. ICICDT 2013: 21-24 - [c32]Felipe Lavratti, Letícia Maria Veiras Bolzani, Andrea Calimera, Fabian Vargas, Enrico Macii:
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs. LATW 2013: 1-6 - [c31]Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino, Letícia Maria Veiras Bolzani Poehls:
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices. LATW 2013: 1-6 - [c30]Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino:
Power modeling and characterization of Graphene-based logic gates. PATMOS 2013: 223-226 - 2012
- [j10]Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera:
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. J. Electron. Test. 28(3): 349-363 (2012) - [j9]Hossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
On-chip process variation-tracking through an all-digital monitoring architecture. IET Circuits Devices Syst. 6(5): 366-373 (2012) - [j8]Andrea Calimera, Enrico Macii, Massimo Poncino:
Design Techniques for NBTI-Tolerant Power-Gating Architectures. IEEE Trans. Circuits Syst. II Express Briefs 59-II(4): 249-253 (2012) - [j7]Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Design Techniques and Architectures for Low-Leakage SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1992-2007 (2012) - [c29]Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino:
IR-drop analysis of graphene-based power distribution networks. DATE 2012: 81-86 - [c28]Alessandro Sassone, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino, Richard Goldman, Vazgen Melikyan, Eduard Babayan, Salvatore Rinaudo:
Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks. DATE 2012: 165-166 - [c27]Wei Liu, Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino:
NBTI effects on tree-like clock distribution networks. ACM Great Lakes Symposium on VLSI 2012: 279-282 - [c26]Mirko Loghi, Haroon Mahmood, Andrea Calimera, Massimo Poncino, Enrico Macii:
Energy-optimal caches with guaranteed lifetime. ISLPED 2012: 141-146 - [c25]Hossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture. PATMOS 2012: 155-165 - 2011
- [j6]Leandro Max de Lima Silva, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Power Efficient Variability Compensation Through Clustered Tunable Power-Gating. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 242-253 (2011) - [c24]Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino:
Partitioned cache architectures for reduced NBTI-induced aging. DATE 2011: 938-943 - [c23]Salvatore Rinaudo, Giuliana Gangemi, Andrea Calimera, Alberto Macii, Massimo Poncino:
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems. DATE 2011: 1127-1128 - [c22]Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino:
Buffering of frequent accesses for reduced cache aging. ACM Great Lakes Symposium on VLSI 2011: 295-300 - [c21]Hossein Karimiyan, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs. PATMOS 2011: 162-172 - [c20]Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. PATMOS 2011: 214-225 - 2010
- [j5]Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino:
Dual-Vt assignment policies in ITD-aware synthesis. Microelectron. J. 41(9): 547-553 (2010) - [j4]Andrea Calimera, Enrico Macii, Massimo Poncino:
NBTI-Aware Clustered Power Gating. ACM Trans. Design Autom. Electr. Syst. 16(1): 3:1-3:25 (2010) - [j3]Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino:
Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1608-1620 (2010) - [c19]Wei Liu, Alberto Nannarelli, Andrea Calimera, Enrico Macii, Massimo Poncino:
Post-placement temperature reduction techniques. DATE 2010: 634-637 - [c18]Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino:
Aging effects of leakage optimizations for caches. ACM Great Lakes Symposium on VLSI 2010: 95-98 - [c17]Andrea Acquaviva, Andrea Calimera, Alberto Macii, Massimo Poncino, Enrico Macii, Matteo Giaconia, Claudio Parrella:
An integrated thermal estimation framework for industrial embedded platforms. ACM Great Lakes Symposium on VLSI 2010: 293-298 - [c16]Andrea Calimera, Enrico Macii, Massimo Poncino:
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells. ISCAS 2010: 785-788 - [c15]Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino:
Dynamic indexing: concurrent leakage and aging optimization for caches. ISLPED 2010: 343-348 - [c14]Andrea Calimera, Enrico Macii, Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda:
Generating power-hungry test programs for power-aware validation of pipelined processors. SBCCI 2010: 61-66
2000 – 2009
- 2009
- [j2]Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 1979-1993 (2009) - [c13]Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Enabling concurrent clock and power gating in an industrial design flow. DATE 2009: 334-339 - [c12]Andrea Calimera, Enrico Macii, Massimo Poncino:
NBTI-aware sleep transistor design for reliable power-gating. ACM Great Lakes Symposium on VLSI 2009: 333-338 - [c11]Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Placement-aware Clustering for Integrated Clock and Power Gating. ISCAS 2009: 1723-1726 - [c10]Andrea Calimera, Enrico Macii, Massimo Poncino:
NBTI-aware power gating for concurrent leakage and aging optimization. ISLPED 2009: 127-132 - [c9]Wei Liu, Andrea Calimera, Alberto Nannarelli, Enrico Macii, Massimo Poncino:
On-chip Thermal Modeling Based on SPICE Simulation. PATMOS 2009: 66-75 - [c8]Gaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. PATMOS 2009: 227-236 - 2008
- [j1]Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino:
Thermal-Aware Design Techniques for Nanometer CMOS Circuits. J. Low Power Electron. 4(3): 374-384 (2008) - [c7]Andrea Calimera, Luca Benini, Enrico Macii:
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints. DATE 2008: 973-978 - [c6]Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino:
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. DSD 2008: 298-303 - [c5]Andrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar:
Temperature-insensitive synthesis using multi-vt libraries. ACM Great Lakes Symposium on VLSI 2008: 5-10 - [c4]Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ISCAS 2008: 2761-2764 - [c3]Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino:
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. ISLPED 2008: 217-220 - 2007
- [c2]Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. DATE 2007: 1544-1549 - [c1]Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ACM Great Lakes Symposium on VLSI 2007: 501-504
Coauthor Index
Letícia Maria Veiras Bolzani
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
[j22] [c73] [c65] [j17] [c50] [c49] [c48] [c47] [c46] [c45] [j16] [c44] [c43] [c42] [c41] [c40] [c39] [j15] [j14] [j13] [c38] [c37] [j12] [j11] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j9] [j8] [j7] [c29] [c28] [c27] [c26] [c25] [j6] [c24] [c22] [c21] [c20] [j5] [j4] [j3] [c19] [c18] [c17] [c16] [c15] [c14] [j2] [c13] [c12] [c11] [c10] [c9] [c8] [j1] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
[j26] [j22] [c65] [j17] [c50] [c49] [c47] [c46] [j16] [c44] [c43] [c42] [c41] [c40] [j15] [j14] [j13] [c38] [c37] [j12] [j11] [c36] [c35] [c34] [c33] [c31] [c30] [j9] [j8] [j7] [c29] [c28] [c27] [c26] [c25] [j6] [c24] [c23] [c22] [c21] [c20] [j5] [j4] [j3] [c19] [c18] [c17] [c16] [c15] [j2] [c13] [c12] [c11] [c10] [c9] [c8] [j1] [c6] [c5] [c4] [c3] [c2] [c1]
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