"Improving Logic Optimization in Sequential Circuits using ..."

Walter Lau Neto et al. (2019)

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DOI: 10.1109/ISVLSI.2019.00049

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-24

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Walter Lau Neto, Xifan Tang, Max Austin, Luca G. Amarù, Pierre-Emmanuel Gaillardon:
Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. ISVLSI 2019: 224-229

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