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ORCIDIEEE Transactions on Circuits and Systems I: Regular Papers, Volume 63
Volume 63-I, Number 1, January 2016
- Oriel Shoshani
, Steven W. Shaw:
Phase Noise Reduction and Optimal Operating Conditions for a Pair of Synchronized Oscillators. 1-11 - Andrei Grebennikov:
High-Efficiency Class-E Power Amplifier With Shunt Capacitance and Shunt Filter. 12-22 - ByongChan Lim, Mark Horowitz:
Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models. 23-33 - Hamidreza Mafi, Mohammad Yavari, Hossein Shamsi:
Digital Calibration of DAC Unit Elements Mismatch in Pipelined ADCs. 34-45 - Sung-Wan Hong, Gyu-Hyeong Cho:
High-Gain Wide-Bandwidth Capacitor-Less Low-Dropout Regulator (LDO) for Mobile Applications Utilizing Frequency Response of Multiple Feedback Loops. 46-57 - José Luis Imaña:
High-Speed Polynomial Basis Multipliers Over GF(2m) for Special Pentanomials. 58-69 - Cheng-Yen Lee, Ping-Hsuan Hsieh, Chia-Hsiang Yang:
A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving. 70-79 - Ata Khorami, Mohammad Sharifkhani:
General Characterization Method and a Fast Load-Charge-Preserving Switching Procedure for the Stepwise Adiabatic Circuits. 80-90 - Jinil Chung, Kenneth Ramclam, Jongsun Park, Swaroop Ghosh:
Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design. 91-102 - Takao Hinamoto, Akimitsu Doi, Wu-Sheng Lu:
Minimization of Weighted Pole and Zero Sensitivity for State-Space Digital Filters. 103-113 - Nikita E. Barabanov, Romeo Ortega, Robert Griñó, Boris T. Polyak:
On Existence and Stability of Equilibria of Linear Time-Invariant Systems With Constant Power Loads. 114-121 - Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s. 122-133 - Qing Lu, Jianfeng Fan, Chiu-Wing Sham, Wai Man Tam, Francis C. M. Lau:
A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes. 134-145 - Hua Yang, Wallace Kit-Sang Tang, Guanrong Chen, Guo-Ping Jiang:
System Design and Performance Analysis of Orthogonal Multi-Level Differential Chaos Shift Keying Modulation Scheme. 146-156 - Junghyun Ham, Jongseok Bae, Hyungchul Kim, Mincheol Seo, Hwiseob Lee, Keum-Cheol Hwang, Kang-Yoon Lee, Cheon-Seok Park, Deukhyoun Heo, Youngoo Yang:
CMOS Power Amplifier Integrated Circuit With Dual-Mode Supply Modulator for Mobile Terminals. 157-167
Volume 63-I, Number 2, February 2016
- Mohsen Moezzi, Mehrdad Sharif Bakhtiar:
Design of LC Resonator for Low Phase Noise Oscillators. 169-180 - Naveen Suda, Jounghyuk Suh, Nagib Hakim, Yu Cao, Bertan Bakkaloglu:
A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation. 181-190 - Hongjie Zhu, Milin Zhang, Yuanming Suo, Trac D. Tran, Jan Van der Spiegel:
Design of a Digital Address-Event Triggered Compressive Acquisition Image Sensor. 191-199 - Dries Vercaemer, Pieter Rombouts:
Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators. 200-210 - Chetan Singh Thakur, Runchun Wang, Tara Julia Hamilton, Jonathan Tapson, André van Schaik:
A Low Power Trainable Neuromorphic Integrated Circuit That Is Tolerant to Device Mismatch. 211-221 - Noa Edri, Pascal Meinerzhagen, Adam Teman, Andreas Burg, Alexander Fish:
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs. 222-232 - Feng Feng, Jiajia Chen, Chip-Hong Chang:
Hypergraph Based Minimum Arborescence Algorithm for the Optimization and Reoptimization of Multiple Constant Multiplications. 233-244 - Xiaofeng Liao:
Dynamical Behavior of Chua's Circuit With Lossless Transmission Line. 245-255 - Silvia Giannini, Antonio Petitti, Donato Di Paola, Alessandro Rizzo:
Asynchronous Max-Consensus Protocol With Time Delays: Convergence Results and Applications. 256-264 - Atsutake Kosuge, Akira Okada, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver. 265-275 - Seungnam Choi, Hyunwoo Son, Jongshin Shin, Sang-Hyun Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization. 276-287 - Jian Wang, Kangli Zhang, Harald Kröll, Jibo Wei:
Design of QPP Interleavers for the Parallel Turbo Decoding Architecture. 288-299 - Jayant Charthad, Nemat Dolatsha, Angad Rekhi, Amin Arbabian:
System-Level Analysis of Far-Field Radio Frequency Power Delivery for mm-Sized Sensor Nodes. 300-311 - Federico Bizzarri, Angelo Brambilla, Federico Milano:
The Probe-Insertion Technique for the Detection of Limit Cycles in Power Systems. 312-321 - Antonio Trias, José Luis Marín:
The Holomorphic Embedding Loadflow Method for DC Power Systems and Nonlinear DC Circuits. 322-333
Volume 63-I, Number 3, March 2016
- Shao Yong Zheng, Zhao Wu Liu, Yong Mei Pan, Yongle Wu, Wing Shing Chan, Yuanan Liu:
Bandpass Filtering Doherty Power Amplifier With Enhanced Efficiency and Wideband Harmonic Suppression. 337-346 - Ehsan Ali, Christian Hangmann, Christian Hedayat, Fayrouz Haddad, Wenceslas Rahajandraibe, Ulrich Hilleringmann:
Event Driven Modeling and Characterization of the Second Order Voltage Switched Charge Pump PLL. 347-358 - Youchang Kim, Injoon Hong, Junyoung Park, Hoi-Jun Yoo:
A 0.5 V 54 µW Ultra-Low-Power Object Matching Processor for Micro Air Vehicle Navigation. 359-369 - Jongwook Sohn, Earl E. Swartzlander Jr.:
A Fused Floating-Point Four-Term Dot Product Unit. 370-378 - Paolo Maffezzoni, Bichoy Bahr, Zheng Zhang, Luca Daniel:
Reducing Phase Noise in Multi-Phase Oscillators. 379-388 - Alon Ascoli, Ronald Tetzlaff, Leon O. Chua, John Paul Strachan, Richard Stanley Williams:
History Erase Effect in a Non-Volatile Memristor. 389-400 - Qianxue Wang, Simin Yu, Chengqing Li, Jinhu Lu, Xiaole Fang, Christophe Guyeux, Jacques M. Bahi:
Theoretical Design and FPGA-Based Implementation of Higher-Dimensional Digital Chaotic Systems. 401-412 - Alberto Oliveri, Flavio Stellino, Guido Caluori, Mauro Parodi, Marco Storace:
Open-Loop Compensation of Hysteresis and Creep Through a Power-Law Circuit Model. 413-422 - Bo Zhou, Patrick Chiang:
Short-Range Low-Data-Rate FM-UWB Transceivers: Overview, Analysis, and Design. 423-435 - Onur Dizdar, Erdal Arikan:
A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic. 436-447
Volume 63-I, Number 4, April 2016
- Yan Song, Zhongming Xue, Yi Xie, Shiquan Fan, Li Geng:
A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC With Incremental Converting Algorithm for Energy Efficient Applications. 449-458 - Timothy A. Monk, Paul J. Hurst, Stephen H. Lewis:
Iterative Gain Enhancement in an Algorithmic ADC. 459-469 - Pablo Castro-Lisboa, Pablo Perez-Nicoli, Francisco Veirano, Fernando Silveira:
General Top/Bottom-Plate Charge Recycling Technique for Integrated Switched Capacitor DC-DC Converters. 470-481 - Kyongsu Lee, Jae-Yoon Sim:
A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling. 482-493 - Radit Smunyahirun, Eng Leong Tan:
Derivation of the Most Energy-Efficient Source Functions by Using Calculus of Variations. 494-502 - Xifan Tang, Gain Kim, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A Study on the Programming Structures for RRAM-Based FPGA Architectures. 503-516 - Ju-Hong Lee, Jiun-Shian Du:
The Phase Characteristics for the Stability of 2-D Nonsymmetric Half-Plane Digital Allpass Filters. 517-528 - Seyed Amir Reza Ahmadi Mehr, Massoud Tohidian, Robert Bogdan Staszewski:
Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise. 529-539 - Ikchan Jang, Yoonmyung Lee, SoYoung Kim, Jintae Kim:
Power-Performance Tradeoff Analysis of CML-Based High-Speed Transmitter Designs Using Circuit-Level Optimization. 540-550 - Jun Yang, Bin Wu, Shihua Li, Xinghuo Yu:
Design and Qualitative Robustness Analysis of an DOBC Approach for DC-DC Buck Converters With Unmatched Circuit Parameter Perturbations. 551-560
Volume 63-I, Number 5, May 2016
- Mario di Bernardo, Eduardo Antônio Barros da Silva, Philipp Häfliger, Gianluca Setti:
Guest Editorial Special Section on the 2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015). 565-566 - Paul P. Sotiriadis:
Spurs-Free Single-Bit-Output All-Digital Frequency Synthesizers With Forward and Feedback Spurs and Noise Cancellation. 567-576 - Georges G. E. Gielen, Jelle Van Rethy, Jorge Marin, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra:
Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies. 577-586 - Lucian-Vasile Stoica, Valentyn Solomko, Thorsten Baumheinrich, Renato Del Regno, Reece Beigh, Geoff Rickard, Paul Williams, Steve Riches:
A High Temperature Frequency Signal Conditioning Unit for Aeronautical Rotating Systems. 587-598 - Jie Zhang, Kerron Duncan, Yuanming Suo, Tao Xiong, Srinjoy Mitra, Trac Duy Tran, Ralph Etienne-Cummings:
Communication Channel Analysis and Real Time Compressed Sensing for High Density Neural Recording Devices. 599-608 - Vanessa Senger, Ronald Tetzlaff:
New Signal Processing Methods for the Development of Seizure Warning Devices in Epilepsy. 609-616 - Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Joshua Yang, Hai Li, Yiran Chen:
Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators. 617-628 - Yue Zhang, Chao Zhang, Jiang Nan, Zhizhong Zhang, Xueying Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Guangyu Sun, Weisheng Zhao:
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System. 629-638 - Gabriel A. Rincón-Mora, Siyu Yang:
Tiny Piezoelectric Harvesters: Principles, Constraints, and Power Conversion. 639-649 - Daniel K. Molzahn, Ian A. Hiskens:
Convex Relaxations of Optimal Power Flow Problems: An Illustrative Example. 650-660 - Tao Wang, Hsiao-Dong Chiang:
On the Number of System Separations in Electric Power Systems. 661-670 - Xun Liu, Philip K. T. Mok, Junmin Jiang, Wing-Hung Ki:
Analysis and Design Considerations of Integrated 3-Level Buck Converters. 671-682 - Tsung-Han Tsai, Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, Hsin-Shu Chen:
An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique. 683-692 - Yingyan Lin, Min-Sun Keel, Adam C. Faust, Aolin Xu, Naresh R. Shanbhag, Elyse Rosenbaum, Andrew C. Singer:
A Study of BER-Optimal ADC-Based Receiver for Serial Links. 693-704 - Jerry Lemberg, Marko Kosunen, Enrico Roverato, Mikko Martelius, Kari Stadius, Lauri Anttila, Mikko Valkama, Jussi Ryynänen:
Digital Interpolating Phase Modulator for Wideband Outphasing Transmitters. 705-715 - Abisai Ramirez-Perez, Ramón Parra-Michel, Alberto Rodriguez-Garcia, Luis F. Gonzalez-Perez:
A New Single h and Multi-h CPM Transmitter. 716-726 - Nai-Chung Kuo, Bo Zhao, Ali M. Niknejad:
Bifurcation Analysis in Weakly-Coupled Inductive Power Transfer Systems. 727-738
Volume 63-I, Number 6, June 2016
- Aliakbar Homayoun, Behzad Razavi:
On the Stability of Charge-Pump Phase-Locked Loops. 741-750 - Wasim Hussain, Hussein Fakhoury, Patricia Desgreys, Yves Blaquière, Yvon Savaria:
An Asynchronous Delta-Modulator Based A/D Converter for an Electronic System Prototyping Platform. 751-762 - Hesham Omran, Hamzah Alahmadi, Khaled N. Salama:
Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors. 763-772 - Omar El-Aassar, Mohamed El-Nozahi, Hani Fikry Ragai:
Loss Mechanisms and Optimum Design Methodology for Efficient mm-Waves Class-E PAs. 773-784 - Bahman Kheradmand Boroujeni, Georg Cornelius Schmidt, Daniel Höft, Maxi Bellmann, Katherina Haase, Koichi Ishida, Reza Shabanpour, Tilo Meister, Corrado Carta, Pol Ghesquière, Arved C. Hübler, Frank Ellinger:
A Fully-Printed Self-Biased Polymeric Audio Amplifier for Driving Fully-Printed Piezoelectric Loudspeakers. 785-794 - Zhijian Lu, Jing Jin, Tingting Mo, Jianjun Zhou:
Analysis of Input LCR Matched N-Path Filter. 795-805 - Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues:
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS. 806-817 - Jinling Xing, Alexander Serb, Ali Khiat, Radu Berdan, Hui Xu, Themistoklis Prodromakis:
An FPGA-Based Instrument for En-Masse RRAM Characterization With ns Pulsing Resolution. 818-826 - Alexander Serb, William Redman-White, Christos Papavassiliou, Themistoklis Prodromakis:
Practical Determination of Individual Element Resistive States in Selectorless RRAM Arrays. 827-835 - Eythan Familier, Ian Galton:
Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional-N PLLs. 836-847 - Saihua Xu, Yong Ching Lim, Jun Wei Lee:
Recursive Filters for Time-Interleaved ADC Mismatch Compensation. 848-858 - Nicholas Tzou, Debesh Bhatta, Xian Wang, Te-Hui Chen, Sen-Wen Hsiao, Barry J. Muldrey, Hyun Woo Choi, Abhijit Chatterjee:
Concurrent Multi-Channel Crosstalk Jitter Characterization Using Coprime Period Channel Stimulus. 859-870 - Bosco H. Leung:
Noise Spike Model in Relaxation Oscillators Based on Physical Phase Change. 871-882 - Ali Nikoofard, Siavash Kananian, Ali Fotowat-Ahmady:
Off-Resonance Oscillation, Phase Retention, and Orthogonality Modeling in Quadrature Oscillators. 883-894 - Joseph S. Friedman, Laurie E. Calvet, Pierre Bessière, Jacques Droulez, Damien Querlioz:
Bayesian Inference With Muller C-Elements. 895-904 - Antonio Buonomo, Alessandro Lo Schiavo:
Investigation of Modes in Double-Tuned LC-VCOs. 905-915 - Arnau Dòria-Cerezo, Josep M. Olm, Mario di Bernardo, Emmanuel Nuño:
Modelling and Control for Bounded Synchronization in Multi-Terminal VSC-HVDC Transmission Networks. 916-925
Volume 63-I, Number 7, July 2016
- Chin-Yu Lin, Tai-Cheng Lee:
A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique. 929-938 - Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology. 939-949 - Fu-To Lin, Shao-Yung Lu, Yu-Te Liao:
A 2.2 µW, -12 dBm RF-Powered Wireless Current Sensing Readout Interface IC With Injection-Locking Clock Generation. 950-959 - Sanghyun Heo, Hyunggun Ma, Joohyeb Song, Kyoungmin Park, Eun-Ho Choi, Jae Joon Kim, Franklin Bien:
72 dB SNR, 240 Hz Frame Rate Readout IC With Differential Continuous-Mode Parallel Architecture for Larger Touch-Screen Panel Applications. 960-971 - Milutin Stanacevic, Shuo Li, Gert Cauwenberghs:
Micropower Mixed-Signal VLSI Independent Component Analysis for Gradient Flow Acoustic Source Separation. 972-981 - Xin Fan, Mikkel B. Stegmann, Oliver Schrape, Steffen Zeidler, Isac G. Jensen, Jannich Thorsen, Tobias Bjerregaard, Milos Krstic:
Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling. 982-993 - Andreas Herkle, Joachim Becker, Maurits Ortmanns:
Exploiting Weak PUFs From Data Converter Nonlinearity - E.g., A Multibit CT ΔΣ Modulator. 994-1004 - Jaejoon Choi, Jaehwan Jung, In-Cheol Park:
Area-Efficient Approach for Generating Quantized Gaussian Noise. 1005-1013 - Saket Gupta, Carl Monzel, Daniel S. Reed, Yifei Zhang, Mark Winter, Myron Buer:
Bitcell-Based Design of On-Chip Process Variability Monitors for Sub-28 nm Memories. 1014-1022 - Younghwi Yang, Hanwool Jeong, Seung Chul Song, Joseph Wang, Geoffrey Yeap, Seong-Ook Jung:
Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology. 1023-1032 - Moshe Avital, Itamar Levi, Osnat Keren, Alexander Fish:
CMOS Based Gates for Blurring Power Information. 1033-1042 - Piotr Zbigniew Wieczorek:
Lightweight TRNG Based on Multiphase Timing of Bistables. 1043-1054 - Jérôme Juillard, Pierre Prache, Núria Barniol:
Analysis of Mutually Injection-Locked Oscillators for Differential Resonant Sensing. 1055-1066 - Riccardo Trinchero, Paolo Manfredi, Tongyu Ding, Igor S. Stievano:
Combined Parametric and Worst Case Circuit Analysis via Taylor Models. 1067-1078 - Qiang Song, Fang Liu, Guanghui Wen, Jinde Cao, Yang Tang:
Synchronization of Coupled Harmonic Oscillators via Sampled Position Data Control. 1079-1088 - Pengda Huang, Yongjiu Du, Yamin Li:
Stability Analysis and Hardware Resource Optimization in Channel Emulator Design. 1089-1100
Volume 63-I, Number 8, August 2016
- Stepan Sutula, Michele Dei, Lluís Terés, Francisco Serra-Graells:
Variable-Mirror Amplifier: A New Family of Process-Independent Class-AB Single-Stage OTAs for Low-Power SC Circuits. 1101-1110 - Cheng-Ru Ho, Mike Shuo-Wei Chen:
A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme. 1111-1122 - Jian-Yu Hsieh, Yi-Chun Huang, Po-Hung Kuo, Tao Wang, Shey-Shi Lu:
A 0.45-V Low-Power OOK/FSK RF Receiver in 0.18 μm CMOS Technology for Implantable Medical Applications. 1123-1130 - Hongjia Mo, Michael Peter Kennedy:
Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs Using Linear Feedback Shift Registers. 1131-1141 - Avishek Adhikary, Siddhartha Sen, Karabi Biswas:
Practical Realization of Tunable Fractional Order Parallel Resonator and Fractional Order Filters. 1142-1151 - Weize Yu, Selçuk Köse:
A Voltage Regulator-Assisted Lightweight AES Implementation Against DPA Attacks. 1152-1163 - Woong Choi, Jongsun Park:
A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design. 1164-1175 - Debajit Bhattacharya, Niraj K. Jha:
Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read Stability. 1176-1187 - Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Testable MUTEX Design. 1188-1199 - Darjn Esposito, Davide De Caro, Antonio Giuseppe Maria Strollo:
Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands. 1200-1209 - Choon Ki Ahn, Peng Shi, Michael V. Basin:
Deadbeat Dissipative FIR Filtering. 1210-1221 - Arturo Buscarino, Claudia Corradino, Luigi Fortuna, Mattia Frasca, Leon O. Chua:
Turing Patterns in Memristive Cellular Nonlinear Networks. 1222-1230 - Alberto Bernardini, Kurt James Werner, Augusto Sarti, Julius Orion Smith III:
Modeling nonlinear wave digital elements using the Lambert function. 1231-1242 - Min Xiao, Wei Xing Zheng, Guoping Jiang, Jinde Cao:
Stability and Bifurcation Analysis of Arbitrarily High-Dimensional Genetic Regulatory Networks With Hub Structure and Bidirectional Coupling. 1243-1254 - Fernando García-Redondo, Robert P. Gowers, Albert Crespo-Yepes, Marisa López-Vallejo, Liudi Jiang:
SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds. 1255-1264 - Hai-Tao Zhang, Bin Liu, Zhaomeng Cheng, Guanrong Chen:
Model Predictive Flocking Control of the Cucker-Smale Multi-Agent Model With Input Constraints. 1265-1275 - Ramon Gomez:
Theoretical Comparison of Direct-Sampling Versus Heterodyne RF Receivers. 1276-1282 - Daniel Günther, Rainer Leupers, Gerd Ascheid:
A Scalable, Multimode SVD Precoding ASIC Based on the Cyclic Jacobi Method. 1283-1294 - Mehdi Ayat, Sattar Mirzakuchaki, Aliasghar Beheshti Shirazi:
Design and Implementation of High Throughput, Robust, Parallel M-QAM Demodulator in Digital Communication Receivers. 1295-1304 - Bo Zhao, Nai-Chung Kuo, Ali M. Niknejad:
An Inductive-Coupling Blocker Rejection Technique for Miniature RFID Tag. 1305-1315 - Chiou-Yng Lee, Pramod Kumar Meher:
Comment on "Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm". 1316-1319
Volume 63-I, Number 9, September 2016
- Tetsuya Iizuka, Asad A. Abidi:
FET-R-C Circuits: A Unified Treatment - Part I: Signal Transfer Characteristics of a Single-Path. 1325-1336 - Tetsuya Iizuka, Asad A. Abidi:
FET-R-C Circuits: A Unified Treatment - Part II: Extension to Multi-Paths, Noise Figure, and Driving-Point Impedance. 1337-1348 - Davide Marano, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi:
Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs. 1349-1359 - Fang Tang, Shiping Li, Bo Wang, Amine Bermak, Xichuan Zhou, Shengdong Hu:
A Low Power Class-AB Audio Power Amplifier With Dynamic Transconductance Compensation in 55 nm CMOS Process. 1360-1369 - Zhangming Zhu, Jin Hu, Yutao Wang:
A 0.45 V, Nano-Watt 0.033% Line Sensitivity MOSFET-Only Sub-Threshold Voltage Reference With no Amplifiers. 1370-1380 - Xuqiang Zheng, Zhijun Wang, Fule Li, Feng Zhao, Shigang Yue, Chun Zhang, Zhihua Wang:
A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process. 1381-1392 - Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology. 1393-1403 - Sagar Ray, Mona Mostafa Hella:
A 30-75 dBΩ 2.5 GHz 0.13-μm CMOS Receiver Front-End With Large Input Capacitance Tolerance for Short-Range Optical Communication. 1404-1415 - Yue Chao, Howard C. Luong:
Analysis and Design of Wide-Band Millimeter-Wave Transformer-Based VCO and ILFDs. 1416-1425 - Lei Dong, Lifeng Wang, Cong Zhang, Qing-An Huang:
A Cyclic Scanning Repeater for Enhancing the Remote Distance of LC Passive Wireless Sensors. 1426-1433 - Vinal Patel, Vaibhav Gandhi, Shashank Heda, Nithin V. George:
Design of Adaptive Exponential Functional Link Network-Based Nonlinear Filters. 1434-1442 - Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross:
Multi-Mode Unrolled Architectures for Polar Decoders. 1443-1453 - Xiaoyang Liu, Zhigang Zeng, Shiping Wen:
Implementation of Memristive Neural Network With Full-Function Pavlov Associative Memory. 1454-1463 - Zhihuan Chen, Xiaohui Yuan, Yanbin Yuan, Herbert Ho-Ching Iu, Tyrone Fernando:
Parameter Identification of Chaotic and Hyper-Chaotic Systems Using Synchronization-Based Parameter Observer. 1464-1475 - Federico Bizzarri, Angelo Brambilla, Lorenzo Codecasa:
Harmonic Balance Based on Two-Step Galerkin Method. 1476-1486 - Firas Odai Hatem, T. Nandha Kumar, Haider A. F. Almurib:
A SPICE Model of the Ta2O5TaOx Bi-Layered RRAM. 1487-1498 - Daniele Romano, Giulio Antonini, Mattia D'Emidio, Daniele Frigioni, Alessandro Mori, Mauro Bandinelli:
Rigorous DC Solution of Partial Element Equivalent Circuit Models. 1499-1510 - Yuanqi Hu, Pantelis Georgiou:
An Automatic Gain Control System for ISFET Array Compensation. 1511-1520 - Federico Milano, Ioannis Dassios:
Small-Signal Stability Analysis for Non-Index 1 Hessenberg Form Systems of Delay Differential-Algebraic Equations. 1521-1530 - Suvankar Biswas, Lilly Huang, Vaibhav A. Vaidya, Krishnan Ravichandran, Ned Mohan, Sairaj V. Dhople:
Universal Current-Mode Control Schemes to Charge Li-Ion Batteries Under DC/PV Source. 1531-1542 - Hesam Sadeghi Gougheri, Mehdi Kiani:
Current-Based Resonant Power Delivery With Multi-Cycle Switching for Extended-Range Inductive Power Transmission. 1543-1552
Volume 63-I, Number 10, October 2016
- Dima Kilani, Mohammad Alhawari, Baker Mohammad, Hani H. Saleh, Mohammed Ismail:
An Efficient Switched-Capacitor DC-DC Buck Converter for Self-Powered Wearable Electronics. 1557-1566 - Sung-Wan Hong, Gyu-Hyeong Cho:
A Pseudo Single-Stage Amplifier With an Adaptively Varied Medium Impedance Node for Ultra-High Slew Rate and Wide-Range Capacitive-Load Drivability. 1567-1578 - Lutfi Albasha, Chris Clifton, Yoshikatsu Jingu, Alan Lawrenson, Hideshi Motoyama, Souheil Bensmida, Kevin A. Morris, Kazumasa Kohama:
An Ultra-Wideband Digitally Programmable Power Amplifier With Efficiency Enhancement for Cellular and Emerging Wireless Communication Standards. 1579-1591 - Sangjin Byun:
A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector. 1592-1604 - Tae Hwan Jin, Hong Gul Han, Tae Wook Kim:
Time-of-Arrival Measurement Using Adaptive CMOS IR-UWB Range Finder With Scalable Resolution. 1605-1615 - Shubin Liu, Yi Shen, Zhangming Zhu:
A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching. 1616-1627 - Jae-Won Nam, Mike Shuo-Wei Chen:
An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS. 1628-1638 - Tzu-Fan Wu, Sourya Dey, Mike Shuo-Wei Chen:
A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter. 1639-1651 - Kien Trinh Quang, Sergio Ruocco, Massimo Alioto:
Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read. 1652-1660 - Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu:
Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing. 1661-1672 - Stepan Lapshev, S. M. Rezaul Hasan:
New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements. 1673-1681 - Roozbeh Abdollahi, Khayrollah Hadidi, Abdollah Khoei:
A Simple and Reliable System to Detect and Correct Setup/Hold Time Violations in Digital Circuits. 1682-1689 - Seyed Mohammad Ali Zeinolabedin, Jun Zhou, Tony Tae-Hyoung Kim:
A Power and Area Efficient Ultra-Low Voltage Laplacian Pyramid Processing Engine With Adaptive Data Compression. 1690-1700 - Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters. 1701-1713 - Zirui Xing, Yuanqing Xia:
Distributed Federated Kalman Filter Fusion Over Multi-Sensor Unreliable Networked Systems. 1714-1725 - Le Zheng, Zhenzhi Wu, Mingoo Seok, Xiaodong Wang, Quanhua Liu:
High-Accuracy Compressed Sensing Decoder Based on Adaptive (ℓ0, ℓ1) Complex Approximate Message Passing: Cross-layer Design. 1726-1736 - Mario Garrido:
A New Representation of FFT Algorithms Using Triangular Matrices. 1737-1745 - Fei Lu, Rui Ma, Zongyu Dong, Li Wang, Chen Zhang, Chenkun Wang, Qi Chen, X. Shawn Wang, Feilong Zhang, Cheng Li, He Tang, Yuhua Cheng, Albert Z. Wang:
A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS. 1746-1757 - Minh-Tien Nguyen, Chadi Jabbour, Majid Homayouni, David Duperray, Pascal Triaire, Van Tam Nguyen:
System Design for Direct RF-to-Digital ΔΣ Receiver. 1758-1770 - Baoyu Hou, Xiang Li, Guanrong Chen:
Structural Controllability of Temporally Switching Networks. 1771-1781
Volume 63-I, Number 11, November 2016
- Emil otev, Cong Huang, Leo C. N. de Vreede, John R. Long, Wouter A. Serdijn, Chris J. M. Verhoeven:
Out-of-Band Immunity to Interference of Single-Ended Baseband Amplifiers Through IM2 Cancellation. 1785-1793 - Ming Yang, Gordon W. Roberts:
Synthesis of High Gain Operational Transconductance Amplifiers for Closed-Loop Operation Using a Generalized Controller-Based Compensation Method. 1794-1806 - Elena Cabrera-Bernal, Salvatore Pennisi, Alfio Dario Grasso, Antonio Torralba, Ramón González Carvajal:
0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier. 1807-1815 - Jiacheng Wang, Wang Ling Goh, Xin Liu, Jun Zhou:
A 12.77-MHz 31 ppm/°C On-Chip RC Relaxation Oscillator With Digital Compensation Technique. 1816-1824 - Glauco Rogerio Cugler Fiorante, Javad Ghasemi, Payman Zarkesh-Ha, Sanjay Krishna:
Spatio-Temporal Bias-Tunable Readout Circuit for On-Chip Intelligent Image Processing. 1825-1832 - Tiffany Moy, Warren Rieutort-Louis, Sigurd Wagner, James C. Sturm, Naveen Verma:
A Thin-Film, Large-Area Sensing and Compression System for Image Detection. 1833-1844 - Wei-Sung Chang, Tai-Cheng Lee:
A 5 GHz Fractional-N ADC-Based Digital Phase-Locked Loops With -243.8 dB FOM. 1845-1853 - Harald Homulle, Stefan Visser, Edoardo Charbon:
A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications. 1854-1865 - Sangwoo Lee, Woojin Jo, Seung-Woo Song, Youngcheol Chae:
A 300-µW Audio ΔΣ Modulator With 100.5-dB DR Using Dynamic Bias Inverter. 1866-1875 - Manuel J. Barragán, Rshdee Alhakim, Haralampos-G. D. Stratigopoulos, Matthieu Dubois, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal:
A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. 1876-1888 - Yunsoo Park, Jintae Kim, Chulwoo Kim:
A Scalable Bandwidth Mismatch Calibration Technique for Time-Interleaved ADCs. 1889-1897 - Allen Waters, Jason Muhlestein, Un-Ku Moon:
Analysis of Metastability Errors in Conventional, LSB-First, and Asynchronous SAR ADCs. 1898-1909 - Sandeep Mishra, Telajala Venkata Mahendra, Anup Dandapat:
A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications. 1910-1920 - Amit Kazimirsky, Shmuel Wimer:
Opportunistic Refreshing Algorithm for eDRAM Memories. 1921-1932 - Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro:
Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes. 1933-1943 - Raziyeh Salarifard, Siavash Bayat Sarmadi, Mohammad Farmani:
High-Throughput Low-Complexity Unified Multipliers Over GF(2m) in Dual and Triangular Bases. 1944-1953 - Wen Yan, Milos D. Ercegovac, He Chen:
An Energy-Efficient Multiplier With Fully Overlapped Partial Products Reduction and Final Addition. 1954-1963 - Paolo Maffezzoni, Bichoy Bahr, Zheng Zhang, Luca Daniel:
Analysis and Design of Boolean Associative Memories Made of Resonant Oscillator Arrays. 1964-1973 - Benoit Larras, Cyril Lahuec, Fabrice Seguin, Matthieu Arzel:
Ultra-Low-Energy Mixed-Signal IC Implementing Encoded Neural Networks. 1974-1985 - Moslem Heidarpour, Arash Ahmadi, Rashid Rashidzadeh:
A CORDIC Based Digital Hardware For Adaptive Exponential Integrate and Fire Neuron. 1986-1996 - Fernando Corinto, Mauro Forti:
Memristor Circuits: Flux - Charge Analysis Method. 1997-2009 - Hui Liu, Haibo Wan, Chi K. Tse, Jinhu Lu:
An Encryption Scheme Based on Synchronization of Two-Layered Complex Dynamical Networks. 2010-2021 - Martin Andraud, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu:
One-Shot Non-Intrusive Calibration Against Process Variations for Analog/RF Circuits. 2022-2035 - Hong-xiang Hu, Wenwu Yu, Guanghui Wen, Qi Xuan, Jinde Cao:
Reverse Group Consensus of Multi-Agent Systems in the Cooperation-Competition Network. 2036-2047 - Aleksandra Lekic, Dusan M. Stipanovic:
Hysteresis Switching Control of the Ćuk Converter. 2048-2061 - Jienan Chen, Zhenbing Zhang, Hao Lu, Jianhao Hu, Gerald E. Sobelman:
An Intra-Iterative Interference Cancellation Detector for Large-Scale MIMO Communications Based on Convex Optimization. 2062-2072 - Nai-Chung Kuo, Bo Zhao, Ali M. Niknejad:
Inductive Power Transfer Uplink Using Rectifier Second-Order Nonlinearity. 2073-2085 - Mayank Kumar, Rajesh Gupta:
Stability and Sensitivity Analysis of Uniformly Sampled DC-DC Converter With Circuit Parasitics. 2086-2097 - Amit Kumar Singha, Santanu Kapat:
A Unified Framework for Analysis and Design of a Digitally Current-Mode Controlled Buck Converter. 2098-2107
Volume 63-I, Number 12, December 2016
- Andrea Mazzanti, Christoph Studer, Filippo Neri, Josep M. Olm, Yichuang Sun:
Guest Editorial Special Issue on the 2016 IEEE International Symposium on Circuits and Systems (ISCAS 2016). 2109-2111 - Igor M. Filanovsky:
Property of Rational Functions Related to Band-Pass Transformation With Application to Symmetric Filters Design. 2112-2119 - Alessandro Vallero, Ioulia Tzouvadaki, Francesca Puppo, Marie-Agnes Doucey, Jean-François Delaloye, Giovanni De Micheli, Sandro Carrara:
Memristive Biosensors Integration With Microfluidic Platform. 2120-2127 - Rahul Pandey, Saurabh Mookerjea, Suman Datta:
Opportunities and Challenges of Tunnel FETs. 2128-2138 - Heba Abunahla, Baker Mohammad, Dirar Homouz, Curtis J. Okelly:
Modeling Valance Change Memristor Device: Oxide Thickness, Material Type, and Temperature Effects. 2139-2148 - Pei-Chen Lee, Jin-Yi Lin, Chih-Cheng Hsieh:
A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching. 2149-2157 - Hassan Sepehrian, Amin Yekani, Leslie A. Rusch, Wei Shi:
CMOS-Photonics Codesign of an Integrated DAC-Less PAM-4 Silicon Photonic Transmitter. 2158-2168 - Vedat Tavsanoglu:
Decomposition of the Nodal Conductance Matrix of a Planar Resistive Grid and Derivation of Its Eigenvalues and Eigenvectors Using the Kronecker Product and Sum With Application to CNN Image Filters. 2169-2179 - Changhyeon Kim, Kyeongryeol Bong, Sungpill Choi, Kyuho Jason Lee, Hoi-Jun Yoo:
A CMOS Image Sensor-Based Stereo Matching Accelerator With Focal-Plane Sparse Rectification and Analog Census Transform. 2180-2188 - Frank L. Maldonado Huayaney, Stephen Nease, Elisabetta Chicca:
Learning in Silicon Beyond STDP: A Neuromorphic Implementation of Multi-Factor Synaptic Plasticity With Calcium-Based Dynamics. 2189-2199 - Shoubhik Gupta, Hadi Heidari, Anastasios Vilouras, Leandro Lorenzelli, Ravinder Dahiya:
Device Modelling for Bendable Piezoelectric FET-Based Touch Sensing System. 2200-2208 - Kaship Sheikh, Shu-Jen Han, Lan Wei:
CNFET With Process Imperfection: Impact on Circuit-Level Yield and Device Optimization. 2209-2221 - Ahmedullah Aziz, Nicholas Jao, Suman Datta, Sumeet Kumar Gupta:
Analysis of Functional Oxide based Selectors for Cross-Point Memories. 2222-2235 - Poorna Marthi, Nazir Hossain, Huan Wang, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González:
Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations. 2236-2244 - Yuxiang Huan, Ning Ma, Jia Mao, Stefan Blixt, Zhonghai Lu, Zhuo Zou, Li-Rong Zheng:
A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications. 2245-2256 - Wu-Sheng Lu, Takao Hinamoto:
A Unified Approach to the Design of Interpolated and Frequency-Response-Masking FIR Filters. 2257-2266 - Abhronil Sengupta, Kaushik Roy:
A Vision for All-Spin Neural Networks: A Device to System Perspective. 2267-2277 - Ticao Jiao, Wei Xing Zheng, Shengyuan Xu:
On Stability of a Class of Switched Nonlinear Systems Subject to Random Disturbances. 2278-2289 - Junxiu Liu, Jim Harkin, Liam P. Maguire, Liam McDaid, John J. Wade, George Martin:
Scalable Networks-on-Chip Interconnected Architecture for Astrocyte-Neuron Networks. 2290-2303 - Zbigniew Galias:
Rigorous Analysis of Chua's Circuit With a Smooth Nonlinearity. 2304-2312 - Stephen Sunter, Krzysztof Jurga, Andrew Laidler:
Using Mixed-Signal Defect Simulation to Close the Loop Between Design and Test. 2313-2322 - Hao Zou, Yasser Moursy, Ramy Iskander, Alexander Steinmair, Heimo Gensinger, Ehrenfried Seebacher, Jean-Paul Chaput, Marie-Minerve Louërat:
Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology. 2323-2333 - Oscar Castañeda, Tom Goldstein, Christoph Studer:
Data Detection in Large Multi-Antenna Wireless Systems via Approximate Semidefinite Relaxation. 2334-2346 - Chun-Yi Liu, Meng-Siou Sie, Edmund Wen Jen Leong, Yu-Cheng Yao, Henry Lopez Davila, Chih-Wei Jen, Wei-Chang Liu, Shyh-Jye Jou:
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver. 2347-2356 - Michael Wu, Chris Dick, Joseph R. Cavallaro, Christoph Studer:
High-Throughput Data Detection for Massive MU-MIMO-OFDM Using Coordinate Descent. 2357-2367 - Seyyed Ali Hashemi, Carlo Condo, Warren J. Gross:
A Fast Polar Code List Decoder Architecture Based on Sphere Decoding. 2368-2380 - Manxin Chen, Kerui Li, Jiefeng Hu, Adrian Ioinovici:
Generation of a Family of Very High DC Gain Power Electronics Circuits Based on Switched-Capacitor-Inductor Cells Starting from a Simple Graph. 2381-2392
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