Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID19th ARC 2024: Aveiro, Portugal
- Iouliia Skliarova
, Piedad Brox Jiménez, Mário P. Véstias, Pedro C. Diniz:
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 20th International Symposium, ARC 2024, Aveiro, Portugal, March 20-22, 2024, Proceedings. Lecture Notes in Computer Science 14553, Springer 2024, ISBN 978-3-031-55672-2
Applications
- Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze:
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. 3-18 - Panagiotis Mpakos, Ioanna Tasou, Chloe Alverti, Panagiotis Miliadis, Pavlos Malakonakis, Dimitris Theodoropoulos, Georgios I. Goumas, Dionisios N. Pnevmatikatos, Nectarios Koziris:
Open-Source SpMV Multiplication Hardware Accelerator for FPGA-Based HPC Systems. 19-32 - Olle Hansson, Mahdieh Grailoo, Oscar Gustafsson, José L. Núñez-Yáñez:
Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training. 33-47 - Wadid Foudhaili, Anouar Nechi, Celine Thermann, Mohammad Al Johmani, Rainer Buchty, Mladen Berekovic, Saleh Mulhem:
Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach. 48-62 - Guilherme Silva, Pedro Silva, Gladston Moreira, Eduardo Luz:
Bridging the Gap in ECG Classification: Integrating Self-supervised Learning with Human-in-the-Loop Amid Medical Equipment Hardware Constraints. 63-74 - Torben Kalkhof, Carsten Heinz, Andreas Koch:
Enabling FPGA and AI Engine Tasks in the HPX Programming Framework for Heterogeneous High-Performance Computing. 75-89 - Henrique B. Brum, Mário P. Véstias, Horácio C. Neto:
LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization. 90-105 - Luis F. Rojas-Muñoz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Eros Camacho-Ruiz, Pablo Navarro-Torrero, Apurba Karmakar, Carlos Fernández García, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Alejandro Casado-Galán, Pau Ortega-Castro, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández, Piedad Brox:
Cryptographic Security Through a Hardware Root of Trust. 106-119 - Minoru Watanabe:
Analysis of Clock Tree Buffer Degradation Caused by Radiation. 120-133 - Murat Isik, Hiruna Vishwamith, Yusuf Sur, Kayode Inadagbo, I. Can Dikmen:
NEUROSEC: FPGA-Based Neuromorphic Audio Security. 134-147
Design Methods and Tools
- Allen Boston, Roman Gauchi, Pierre-Emmanuel Gaillardon:
Secure eFPGA Configuration: A System-Level Approach. 151-165 - Jonathan Strobl, Leonardo Solis-Vasquez, Yannick Lavan, Andreas Koch:
Graphtoy: Fast Software Simulation of Applications for AMD's AI Engines. 166-180 - Manuel Cerqueira da Silva, Luís Miguel Sousa, Nuno Paulino, João Bispo:
A DSL and MLIR Dialect for Streaming and Vectorisation. 181-190
Applications and Architectures
- Bardia Babaei, Dirk Koch:
Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ Devices. 193-209 - José L. Mira, Jesús Barba, Julián Caba, José Antonio de la Torre, Fernando Rincón, Soledad Escolar, Juan Carlos López:
High Performance Connected Components Accelerator for Image Processing in the Edge. 210-221 - Shine Parekkadan Sunny, Satyajit Das:
Spectral-Blaze: A High-Performance FFT-Based CNN Accelerator. 222-238
Special Session: Collaborative Research Projects
- An Braeken, Bruno da Silva, Laurent Segers, Johannes Knödtel, Marc Reichenbach, Cornelia Wulf, Sergio A. Pertuz, Diana Göhringer, Jo Vliegen, Md Masoom Rabbani, Nele Mentens:
Trusted Computing Architectures for IoT Devices. 241-254 - Asmita Adhikary, Abraham Basurto, Lejla Batina, Ileana Buhan, Joan Daemen, Silvia Mella, Nele Mentens, Stjepan Picek, Durga Lakshmi Ramachandran, Abolfazl Sajadi, Todor Stefanov, Dennis Vermoen, Nusa Zidaric:
PROACT - Physical Attack Resistance of Cryptographic Algorithms and Circuits with Reduced Time to Market. 255-266 - Sergio A. Pertuz, Cornelia Wulf, Najdet Charaf, Lester Kalms, Diana Göhringer:
A Flexible Mixed-Mesh FPGA Cluster Architecture for High Speed Computing. 267-281 - Vatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández:
A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator. 282-295 - Paolo Meloni, Paola Busia, Gianluca Leone, Luca Martis, Matteo Antonio Scrugli:
Exploiting FPGAs and Spiking Neural Networks at the Micro-Edge: The EdgeAI Approach. 296-302
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-26 18:38 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
