default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID32nd ASAP 2021: Virtual Event, USA
- 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2021, Virtual Conference, USA, July 7-9, 2021. IEEE 2021, ISBN 978-1-6654-2701-2
- Luca Bertaccini, Luca Benini, Francesco Conti:
To Buffer, or Not to Buffer? A Case Study on FFT Accelerators for Ultra-Low-Power Multicore Clusters. 1-8 - Yu Wang, Peng Li:
Algorithm and Hardware Co-Design for FPGA Acceleration of Hamiltonian Monte Carlo Based No-U-Turn Sampler. 9-16 - Shihao Song, Twisha Titirsha, Anup Das
:
Improving Inference Lifetime of Neuromorphic Systems via Intelligent Synapse Mapping. 17-24 - Ben Marshall, Daniel Page, Thinh Hung Pham:
A lightweight ISE for ChaCha on RISC-V. 25-32 - Dong Wen, Jingfei Jiang, Jinwei Xu, Kang Wang, Tao Xiao, Yang Zhao, Yong Dou:
RFC-HyPGCN: A Runtime Sparse Feature Compress Accelerator for Skeleton-Based GCNs Action Recognition Model with Hybrid Pruning. 33-40 - Tomohiro Ueno, Atsushi Koshiba, Kentaro Sano:
Virtual Circuit-Switching Network with Flexible Topology for High-Performance FPGA Cluster. 41-48 - Vimal Chacko, Jason Helge Anderson:
Power, Performance and Area Consequences of Multi-Context Support in CGRAs. 49-52 - Lukas Sommer, Michael Halkenhäuser, Cristian Axenie, Andreas Koch:
SPNC: Accelerating Sum-Product Network Inference on CPUs and GPUs. 53-56 - Grant Brown, Valerio Tenace, Pierre-Emmanuel Gaillardon:
NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks. 57-60 - Yu Qian, Baolei Cheng, Jianxi Fan, Yifeng Wang, Ruofan Jiang:
Edge-disjoint spanning trees in the line graph of hypercubes. 61-64 - Shihang Wang, Jianghan Zhu, Qi Wang, Can He, Terry Tao Ye:
Customized Instruction on RISC-V for Winograd-Based Convolution Acceleration. 65-68 - Yanpeng Cao, Chengcheng Wang, Changjun Song, Yongming Tang, He Li:
Real-Time Super-Resolution System of 4K-Video Based on Deep Learning. 69-76 - Mingshuo Liu, Shiyi Luo, Kevin Han, Bo Yuan, Ronald F. DeMara, Yu Bai:
An Efficient Real-Time Object Detection Framework on Resource-Constricted Hardware Devices via Software and Hardware Co-design. 77-84 - Hongwu Peng, Shanglin Zhou, Scott Weitze, Jiaxin Li, Sahidul Islam, Tong Geng, Ang Li, Wei Zhang, Minghu Song, Mimi Xie, Hang Liu, Caiwen Ding:
Binary Complex Neural Network Acceleration on FPGA : (Invited Paper). 85-92 - Stylianos I. Venieris, Ioannis Panopoulos, Ilias Leontiadis, Iakovos S. Venieris:
How to Reach Real-Time AI on Consumer Devices? Solutions for Programmable and Custom Architectures. 93-100 - Yuanjia Xu, Heng Wu, Wenbo Zhang, Chen Yang, Yuewen Wu, Heran Gao, Tao Wang:
Talos: A Weighted Speedup-Aware Device Placement of Deep Learning Models. 101-108 - Masashi Ogaki, Yukinori Sato:
Hodgkin-Huxley-Based Neural Simulation with Networks Connecting to Near-Neighbor Neurons. 109-116 - Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk:
Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. 117-124 - Krishna Teja Chitty-Venkata, Arun K. Somani:
Array-Aware Neural Architecture Search. 125-132 - Hyunmin Jeong, Deming Chen:
TwinDNN: A Tale of Two Deep Neural Networks. 133-140 - Liping Zhang, Qin Lu:
Image caption generation method based on an interaction mechanism and scene concept selection module. 141-148 - Cheng Tan, Nicolas Bohm Agostini, Jeff Zhang, Marco Minutoli, Vito Giovanni Castellana, Chenhao Xie, Tong Geng, Ang Li, Kevin J. Barker, Antonino Tumeo:
OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays. 149-155 - Jason Helge Anderson, Rami Beidas, Vimal Chacko, Hsuan Hsiao, Xiaoyi Ling, Omar Ragheb, Xinyuan Wang, Tianyi Yu:
CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper). 156-162 - Rogério Paludo, Leonel Sousa:
Number Theoretic Transform Architecture suitable to Lattice-based Fully-Homomorphic Encryption. 163-170 - Sukarn Agarwal, Shounak Chakraborty:
ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. 171-174 - Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang:
DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography. 175-178 - Thinh Hung Pham, Ben Marshall, Alexander Fell, Siew-Kei Lam, Daniel Page:
XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage. 179-186 - Jishnu Banerjee, Sahidul Islam, Wei Wei, Chen Pan, Dakai Zhu, Mimi Xie:
Memory-aware Efficient Deep Learning Mechanism for IoT Devices. 187-194 - Ben Li, Jingweijia Tan, Kaige Yan:
AERO: Towards Energy-Efficient Autonomous Flight in MAVs Using Approximate Execution. 196-202 - Mingjian Sun, Yuan Li, Song Chen, Yi Kang:
A Low Power Branch Prediction for Deep Learning on RISC-V Processor. 203-206 - Huanwen Zhang, Yan Wang, Jianxi Fan, Ruyan Guo:
Parallel Construction of Independent Spanning Trees on Folded Crossed Cubes. 207-210 - Sizhe Zhang, Ruixuan Wang, Jeff Jun Zhang, Abbas Rahimi, Xun Jiao:
Assessing Robustness of Hyperdimensional Computing Against Errors in Associative Memory : (Invited Paper). 211-217 - Jeff Jun Zhang, Nicolas Bohm Agostini, Shihao Song, Cheng Tan, Ankur Limaye, Vinay Amatya, Joseph B. Manzano, Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Gu-Yeon Wei, David Brooks:
Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis. 218-225 - Yoshiki Fujiwara, Shinya Takamaeda-Yamazaki:
ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design. 226-233 - Yuchen Qiu, Chao Xiao, LingHui Peng, Junhui Wang, Ziyang Kang, Shiming Li, Lei Wang:
A Novel Ring-based Small-World NoC for Neuromorphic Processor. 234-241 - Xinyuan Wang, Tianyi Yu, Hsuan Hsiao, Jason Helge Anderson:
Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays. 242-249 - Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones:
An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers. 250-257 - Xinheng Liu, Yao Chen, Cong Hao, Ashutosh Dhar, Deming Chen:
WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs. 258-265 - En-Yu Yang, Tianyu Jia, David Brooks, Gu-Yeon Wei:
FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference. 266-273
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-01-15 23:56 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
