default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID17th LATS 2016: Foz do Iguacu, Brazil
- 17th Latin-American Test Symposium, LATS 2016, Foz do Iguacu, Brazil, April 6-8, 2016. IEEE 2016, ISBN 978-1-5090-1331-9
- Krishnendu Chakrabarty:
The hype, myths, and realities of testing 2.5D/3D integrated circuits. 1 - Bernd Becker
:
Known unknowns - Knowledge in the presence of unknowns. 1 - Erik Larsson, Farrokh Ghani Zadegan:
Accessing on-chip instruments through the life-time of systems. 2-4 - Subhasish Mitra:
Transforming nanodevices into nanosystems: The N3XT 1, 000X. 6 - Akhilesh Jaiswal, Kaushik Roy:
Spin transfer torque memories for on-chip caches: Prospects and perspectives. 7 - Bruna F. Flesch, Bianca Brand, Rodrigo Marques de Figueiredo, Lucio Rene Prade, Marcio Rosa da Silva:
Proposal of a functional safety methodology applied to fault tolerance in FPGA applications. 8-13 - Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey:
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables. 14-19 - Zoran Stamenkovic, Vladimir Petrovic:
A comprehensive approach to fault tolerance: Device, circuit, and system techniques. 20 - J. Barboza, J. Basualdo, Julio Pérez Acle:
Auxiliary IP blocks for early dependability analysis of small processor based systems. 21-26 - Jose Isaza-Gonzalez, Alejandro Serrano-Cases, Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez:
Dependability evaluation of COTS microprocessors via on-chip debugging facilities. 27-32 - Mario Schölzel, Tobias Koal, Sebastian Müller, Stefan Scharoba, Stephanie Roder, Heinrich Theodor Vierhaus:
A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processors. 33-38 - Rafael B. Schivittz, Denis Teixeira Franco, Cristina Meinhardt, Paulo F. Butzen:
A probabilistic model for stuck-on faults in combinational logic gates. 39-44 - Alessandro Danese, Jacopo Mocci, Graziano Pravadelli:
Fault model qualification by assertion mining. 45-50 - Kelson Gent, Michael S. Hsiao:
A control path aware metric for grading functional test vectors. 51-56 - Stefano Esposito, Serhiy Avramenko, Massimo Violante:
On the consolidation of mixed criticalities applications on multicore architectures. 57-62 - Anelise Kologeski, Henrique Colao Zanuz, Fernanda Lima Kastensmidt:
Using traffic monitoring to tolerate multiple faults in 3D NoCs. 63-68 - Konstantin Shibin, Sergei Devadze, Artur Jutman:
On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs. 69-74 - Thiago Copetti, Guilherme Medeiros Machado, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar:
Gate-level modelling of NBTI-induced delays under process variations. 75-80 - Freddy Forero, Andres F. Gomez, Víctor H. Champac:
A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage. 81-86 - M. Tulio Martins, G. Cardoso Medeiros, Thiago Copetti, Fabian Vargas, Letícia Maria Bolzani Poehls:
Analyzing NBTI impact on SRAMs with resistive-open defects. 87-92 - Werner Nedel, Fernanda Lima Kastensmidt, José Rodrigo Azambuja:
Evaluating the effects of single event upsets in soft-core GPGPUs. 93-98 - Eduardo Chielle, Boyang Du, Fernanda Lima Kastensmidt, Sergio Cuenca-Asensi, Luca Sterpone, Matteo Sonza Reorda:
Hybrid soft error mitigation techniques for COTS processor-based systems. 99-104 - Charalambos Konstantinou, Marios Sazos, Michail Maniatakos:
Attacking the smart grid using public information. 105-110 - Daniel Fusco, Tiago R. Balen:
Radiation effects in low power and ultra low power voltage references. 111-116 - Konstantin O. Petrosyants, Lev M. Sambursky, Igor A. Kharitonov, Boris G. Lvov:
Fault simulation in radiation-hardened SOI CMOS VLSIs using universal compact MOSFET model. 117-122 - Guilherme Schwanke Cardoso, Tiago R. Balen:
Performance evaluation of radiation hardened analog circuits based on Enclosed Layout geometry. 123-128 - Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell:
Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect. 129-134 - M. De Carvalho, Maurício Altieri, L. Puricelli, Renato P. Butzen, Renato P. Ribas, Eric E. Fabris:
On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design. 135-140 - Rogerio Paludo, Djones Lettnin:
A methodology for early functional verification of embedded software combining virtual platforms and bounded model checking. 141-146 - Luiz Gustavo Casagrande, Fernanda Lima Kastensmidt:
Soft error analysis in embedded software developed with & without operating system. 147-152 - Christian Bartsch, Nico Rödel, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz:
A HW-dependent software model for cross-layer fault analysis in embedded systems. 153-158 - Daniele Coati, Rosario Distefano, Nicola Bombieri, Franco Fummi, Michela Mirenda, Carlo Laudanna, Rosalba Giugno:
A SystemC-based platform for assertion-based verification and mutation analysis in systems biology. 159-164 - Walter Soto Encinas, Francisco Romulo da Silva Araujo, Harney Abrahim:
Infrastructure for formal and dynamic verification of peripheral programming model. 165-170 - Mauricio de Oliveira Barros, Andrea Weber:
System-level diagnosis for WSN: A heuristic. 171-176 - Artjom Jasnetski, Raimund Ubar, Anton Tsertov:
On automatic software-based self-test program generation based on high-level decision diagrams. 177 - Afef Kchaou, W. El Hadj Youssef, Rached Tourki, Fraidy Bouesse, Pablo Ramos, Raoul Velazco:
A deep analysis of SEU consequences in the internal memory of LEON3 processor. 178 - Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt:
Soft error analysis at sequential and parallel applications in ARM Cortex-A9 dual-core. 179 - Eduardo Liebl, Cristina Meinhardt, Paulo F. Butzen:
Reliability analysis of majority voters under permanent faults. 180 - Harini Bhamidipati, Daniel G. Saab, Jacob A. Abraham:
Single Trojan injection model generation and detection. 181 - Suvadeep Banerjee, Abhijit Chatterjee, Jacob A. Abraham:
Checksum based error detection in linearized representations of non linear control systems. 182 - Michael A. Kochte, Hans-Joachim Wunderlich:
Dependable on-chip infrastructure for dependable MPSOCs. 183-188 - Eduardo Wächter, Francisco F. S. Barreto, Vinicius Fochi, Alexandre M. Amory, Fernando Gehm Moraes:
A layered approach for fault tolerant NoC-based MPSoCs - Special session: Dependable MPSoCs. 189-194 - Pierre-Emmanuel Gaillardon, Romain Magni, Luca Gaetano Amarù, Mehdi Hasan, Ross Walker, Berardi Sensale Rodriguez, Jean-Frédéric Christmann, Edith Beigné:
Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications. 195-200
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-09-26 23:46 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
