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ORCIDDietmar Fey
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- affiliation: University of Erlangen-Nuremberg, Germany
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2020 – today
- 2024
[j37]Farhad Ebrahimi-Azandaryani
, Dietmar Fey:
ExTern: Boosting RISC-V core performance using ternary encoding. Microprocess. Microsystems 107: 105058 (2024)- [c144]Johannes Kliemt, Markus Fritscher, Dietmar Fey:
Comparison of a Binary Signed-Digit Adder with Conventional Binary Adder Circuits on Layout Level. ARCS 2024: 236-248 - [e4]Dietmar Fey, Benno Stabernack, Stefan Lankes, Mathias Pacher, Thilo Pionteck:
Architecture of Computing Systems - 37th International Conference, ARCS 2024, Potsdam, Germany, May 14-16, 2024, Proceedings. Lecture Notes in Computer Science 14842, Springer 2024, ISBN 978-3-031-66145-7 [contents] - 2023
- [j36]Burkhard Ringlein, François Abel, Dionysios Diamantopoulos, Beat Weiss, Christoph Hagleitner, Dietmar Fey:
Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures. IEEE Comput. Archit. Lett. 22(1): 9-12 (2023) - [j35]Dietmar Fey:
Memristive computing in Germany. it Inf. Technol. 65(1-2): 1-2 (2023) - [j34]Shima Hosseinzadeh, Marius Klemm, Georg Fischer, Dietmar Fey:
Optimizing multi-level ReRAM memory for low latency and low energy consumption. it Inf. Technol. 65(1-2): 52-64 (2023) - [c143]Shima Hosseinzadeh, Amirhossein Parvaresh, Dietmar Fey:
Optimization of OLAP In-Memory Database Management Systems with Processing-In-Memory Architecture. ARCS 2023: 264-278 - [c142]Burkhard Ringlein, François Abel, Dionysios Diamantopoulos, Beat Weiss, Christoph Hagleitner, Dietmar Fey:
DOSA: Organic Compilation for Neural Network Inference on Distributed FPGAs. EDGE 2023: 43-50 - [c141]John Reuben, Dietmar Fey, Stefan Slesazeck:
A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories. MOCAST 2023: 1-4 - [c140]Stefan Slesazeck, Suzanne Lancaster, John Reuben, Shima Hosseinzadeh, Dietmar Fey, Thomas Mikolajick:
Hyper Dimensional Computing with Ferroelectric Tunneling Junctions. NANOARCH 2023: 3:1-3:2 - [c139]Amirhossein Parvaresh, Shima Hosseinzadeh, Dietmar Fey:
Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study. NANOARCH 2023: 28:1-28:6 - [c138]Johannes Kliemt, Dietmar Fey:
Work in Progress: Extending Virtual Prototypes of Microprocessor Architectures with Accuracy Tracing. SIMULTECH 2023: 409-416 - 2022
- [c137]Lars Schwenger, Philipp Holzinger, Dietmar Fey, Hector Gerardo Muñoz Hernandez, Marc Reichenbach:
EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis. SAMOS 2022: 43-57 - [c136]Farehe Giahi, Sebastian Rachuj, Dietmar Fey:
Investigating SAMV Regarding its Suitability For FPGAs. SOCC 2022: 1-6 - [i14]Thomas Heller, Hartmut Kaiser, Patrick Diehl, Dietmar Fey, Marc Alexander Schweitzer:
Closing the Performance Gap with Modern C++. CoRR abs/2206.06302 (2022) - 2021
- [j33]Marc Reichenbach, Johannes Knödtel, Sebastian Rachuj, Dietmar Fey:
RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems. IEEE Access 9: 43684-43700 (2021) - [j32]Anne D. Koelewijn, Musa L. Audu, Antonio J. del Ama, Annalisa Colucci, Josep M. Font-Llagunes, Antonio Gogeascoechea, Sandra K. Hnat, Nathan S. Makowski, Juan C. Moreno, Mark J. Nandor, Roger D. Quinn, Marc Reichenbach, Ryan-David Reyes, Massimo Sartori, Surjo R. Soekadar, Ronald J. Triolo, Mareike Vermehren, Christian Wenger, Utku S. Yavuz, Dietmar Fey, Philipp Beckerle:
Adaptation Strategies for Personalized Gait Neuroprosthetics. Frontiers Neurorobotics 15: 750519 (2021) - [c135]Burkhard Ringlein, François Abel, Dionysios Diamantopoulos, Beat Weiss, Christoph Hagleitner, Marc Reichenbach, Dietmar Fey:
A Case for Function-as-a-Service with Disaggregated FPGAs. CLOUD 2021: 333-344 - [c134]Dietmar Fey, John Reuben, Stefan Slesazeck:
Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic. ICECS 2021: 1-6 - [c133]Steffen Vaas, Peter Ulbrich, Christian Eichler, Peter Wägemann, Marc Reichenbach, Dietmar Fey:
Taming Non-Deterministic Low-Level I/O: Predictable Multi-Core Real-Time Systems by SoC Co-Design. ISORC 2021: 43-52 - [c132]John Reuben, Dietmar Fey:
Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles. ISVLSI 2021: 157-163 - [c131]Markus Fritscher, Johannes Knödtel, Daniel Reiser, Maen Mallah, Stefan Pechmann, Dietmar Fey, Marc Reichenbach:
Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. LASCAS 2021: 1-4 - [c130]Johannes Lex, Ulrich Margull, Dietmar Fey, Ralph Mader:
Fault Tolerance in Heterogeneous Automotive Real-time Systems. Echtzeit 2021: 73-82 - 2020
- [j31]Dietmar Fey, Wolfgang Karl, Theo Ungerer:
Memristoren für zukünftige Rechnersysteme. Inform. Spektrum 43(1): 57-58 (2020) - [j30]Herbert Jordan, Philipp Gschwandtner, Peter Thoman, Peter Zangerl, Alexander Hirsch, Thomas Fahringer, Thomas Heller, Dietmar Fey:
The allscale framework architecture. Parallel Comput. 99: 102648 (2020) - [j29]Johannes Hofmann, Christie L. Alappat, Georg Hager, Dietmar Fey, Gerhard Wellein:
Bridging the Architecture Gap: Abstracting Performance-Relevant Properties of Modern Server Processors. Supercomput. Front. Innov. 7(2): 54-78 (2020) - [c129]Shima Hosseinzadeh, Mehrdad Biglari, Dietmar Fey:
TReMo: A Model for Ternary ReRAM-Based Memories with Adjustable Write-Verification Capabilities. DSD 2020: 44-48 - [c128]Dietmar Fey, John Reuben:
Direct state transfer in MLC based memristive ReRAM devices for ternary computing. ECCTD 2020: 1-5 - [c127]Burkhard Ringlein, François Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, Dietmar Fey:
ZRLMPI: A Unified Programming Model for Reconfigurable Heterogeneous Computing Clusters. FCCM 2020: 220 - [c126]Johannes Knödtel, Markus Fritscher, Daniel Reiser, Dietmar Fey, Marco Breiling, Marc Reichenbach:
A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories. MOCAST 2020: 1-6 - [c125]Burkhard Ringlein, François Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, Dietmar Fey:
Programming Reconfigurable Heterogeneous Computing Clusters Using MPI With Transpilation. H2RC@SC 2020: 1-9 - [c124]Sebastian Rachuj, Dietmar Fey, Marc Reichenbach:
Impact of Performance Estimation on Fast Processor Simulators. SimuTools (2) 2020: 79-93
2010 – 2019
- 2019
- [j28]Marc Reichenbach, Philipp Holzinger, Konrad Häublein, Tobias Lieske, Paul Blinzer, Dietmar Fey:
Heterogeneous Computing Utilizing FPGAs - A New and Flexible Approach Integrating Dedicated Hardware Accelerators into Common Computing Platforms. J. Signal Process. Syst. 91(7): 745-757 (2019) - [j27]Steffen Vaas, Peter Ulbrich, Marc Reichenbach, Dietmar Fey:
Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands. J. Signal Process. Syst. 91(7): 773-786 (2019) - [j26]Tobias Lieske, Wilfried Uhring, Norbert Dumas, Anastasia Ioanna Skilitski, Jérémie Léonard, Dietmar Fey:
Embedded Fluorescence Lifetime Determination for High-Throughput, Low-Photon-Number Applications. J. Signal Process. Syst. 91(7): 819-831 (2019) - [c123]Sebastian Rachuj, Marc Reichenbach, Dietmar Fey:
A Generic Functional Simulation of Heterogeneous Systems. ARCS 2019: 128-141 - [c122]Burkhard Ringlein, François Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, Dietmar Fey:
System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration. FPL 2019: 293-300 - [c121]Markus Fritscher, Johannes Knödtel, Marc Reichenbach, Dietmar Fey:
Simulating Memristive Systems in Mixed-Signal Mode using Commercial Design Tools. ICECS 2019: 225-228 - [c120]Rashid Ali, Maen Mallah, Martin Leyh, Philipp Holzinger, Marco Breiling, Marc Reichenbach, Dietmar Fey:
A Hardware Inference Accelerator for Temporal Convolutional Networks. NORCAS 2019: 1-7 - [c119]John Reuben, Dietmar Fey:
A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM. NORCAS 2019: 1-6 - [c118]Alexander Ditter, Michael Tielemann, Dietmar Fey:
Bridging the Gap between High-Performance, Cloud and Service-Oriented Computing. FAS*W@SASO/ICAC 2019: 68-69 - [i13]Johannes Hofmann, Christie L. Alappat, Georg Hager, Dietmar Fey, Gerhard Wellein:
Bridging the Architecture Gap: Abstracting Performance-Relevant Properties of Modern Server Processors. CoRR abs/1907.00048 (2019) - 2018
- [j25]Christopher Soell, Marc Reichenbach, Juergen Roeber, Amelie Hagelauer, Robert Weigel, Dietmar Fey:
Case study on memristor-based multilevel memories. Int. J. Circuit Theory Appl. 46(1): 99-112 (2018) - [j24]Dietmar Fey, Frank Hannig:
Special issue on heterogeneous real-time image processing. J. Real Time Image Process. 14(3): 513-515 (2018) - [j23]Christian Hartmann, Konrad Häublein, Marc Reichenbach, Dietmar Fey:
IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures. J. Real Time Image Process. 14(3): 549-564 (2018) - [j22]Christian Hartmann, Dietmar Fey:
An extended analysis of memory hierarchies for efficient implementations of image processing applications. J. Real Time Image Process. 14(3): 713-728 (2018) - [j21]Daniel Wust, Dietmar Fey, Johannes Knödtel:
A programmable ternary CPU using hybrid CMOS/memristor circuits. Int. J. Parallel Emergent Distributed Syst. 33(4): 387-407 (2018) - [j20]Said Hamdioui, Pierre-Emmanuel Gaillardon, Dietmar Fey, Tajana Simunic Rosing:
Guest Editorial Memristive-Device-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2581-2583 (2018) - [c117]Sebastian Rachuj, Christian Herglotz, Marc Reichenbach, André Kaup, Dietmar Fey:
A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model. ARCS 2018: 85-96 - [c116]Herbert Jordan, Thomas Heller, Philipp Gschwandtner, Peter Zangerl, Peter Thoman, Dietmar Fey, Thomas Fahringer:
The AllScale Runtime Application Model. CLUSTER 2018: 445-455 - [c115]Marc Reichenbach, Lukas Liebischer, Steffen Vaas, Dietmar Fey:
Comparison of Lane Detection Algorithms for ADAS Using Embedded Hardware Architectures. DASIP 2018: 48-53 - [c114]Wolfgang Bauer, Philipp Holzinger, Marc Reichenbach, Steffen Vaas, Paul Hartke, Dietmar Fey:
Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems. Euro-Par Workshops 2018: 733-744 - [c113]Sebastian Rachuj, Marc Reichenbach, Steffen Vaas, Dietmar Fey:
Autonomous Driving in the Curriculum of Computer Architecture. EWME 2018: 11-16 - [c112]Anderson M. Maliszewski, Dalvan Griebler, Claudio Schepke, Alexander Ditter, Dietmar Fey, Luiz Gustavo Fernandes:
The NAS Benchmark Kernels for Single and Multi-Tenant Cloud Instances with LXC/KVM. HPCS 2018: 359-366 - [c111]Tobias Lieske, Mehrdad Biglari, Dietmar Fey:
Multi-level memristive voltage divider: programming scheme trade-offs. MEMSYS 2018: 259-268 - [c110]Mehrdad Biglari, Tobias Lieske, Dietmar Fey:
High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States. NANOARCH 2018: 19-24 - [c109]Johannes Knödtel, Wolffhardt Schwabe, Tobias Lieske, Marc Reichenbach, Dietmar Fey:
A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs. PATMOS 2018: 46-53 - [c108]Philipp Holzinger, Marc Reichenbach, Dietmar Fey:
A new generic HLS approach for heterogeneous computing: on the feasibility of high-level synthesis in HSA-compatible systems. SAMOS 2018: 18-27 - [c107]Johannes Hofmann, Georg Hager, Dietmar Fey:
On the Accuracy and Usefulness of Analytic Energy Models for Contemporary Multicore Processors. ISC 2018: 22-43 - [d1]Herbert Jordan, Thomas Heller, Philipp Gschwandtner, Peter Zangerl, Peter Thoman, Dietmar Fey, Thomas Fahringer:
Dataset for "The AllScale Runtime Application Model" publication. Zenodo, 2018
- [i12]Johannes Hofmann, Georg Hager, Dietmar Fey:
On the accuracy and usefulness of analytic energy models for contemporary multicore processors. CoRR abs/1803.01618 (2018) - 2017
- [j19]Johannes Hofmann, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, Gerhard Wellein:
Performance analysis of the Kahan-enhanced scalar product on current multi-core and many-core processors. Concurr. Comput. Pract. Exp. 29(9) (2017) - [j18]Steffen Limmer, Dietmar Fey:
Comparison of common parallel architectures for the execution of the island model and the global parallelization of evolutionary algorithms. Concurr. Comput. Pract. Exp. 29(9) (2017) - [j17]Benjamin Pfundt, Marc Reichenbach, Dietmar Fey:
Comprehensive curriculum for reconfigurable heterogeneous computer architecture education. IET Circuits Devices Syst. 11(4): 292-298 (2017) - [j16]Marc Reichenbach, Maximilian Kasparek, Konrad Häublein, Jan Niklas Bauer, Mohammad Alawieh, Dietmar Fey:
Fast heterogeneous computing architectures for smart antennas. J. Syst. Archit. 76: 76-88 (2017) - [j15]Frank Hannig, João M. P. Cardoso, Dietmar Fey:
Introduction to the special issue on architecture of computing systems. J. Syst. Archit. 77: 1-2 (2017) - [c106]Tobias Lieske, Wilfried Uhring, Norbert Dumas, Jérémie Léonard, Dietmar Fey:
Embedded fluorescence lifetime determination for high throughput real-time droplet sorting with microfluidics. DASIP 2017: 1-6 - [c105]Marc Reichenbach, Philipp Holzinger, Konrad Häublein, Tobias Lieske, Paul Blinzer, Dietmar Fey:
LibHSA: One step towards mastering the era of heterogeneous hardware accelerators using FPGAs. DASIP 2017: 1-6 - [c104]Steffen Vaas, Peter Ulbrich, Marc Reichenbach, Dietmar Fey:
The best of both: High-performance anc deterministic real-time executive by application-specific multi-core SoCs. DASIP 2017: 1-6 - [c103]Alexander Ditter, Gabriel Graf, Dietmar Fey:
Fe2vCl2: From Bare Metal to High Performance Computing on Virtual Clusters and Cloud Infrastructure. CCB@EuroSys 2017: 3:1-3:7 - [c102]Mehrdad Biglari, Dietmar Fey:
Memristive voltage divider: a bipolar ReRAM-based unit for non-volatile flip-flops. MEMSYS 2017: 217-222 - [c101]Daniel Wust, Mehrdad Biglari, Johannes Knödtel, Marc Reichenbach, Christopher Söll, Dietmar Fey:
Prototyping memristors in digital system with an FPGA-based testing environment. PATMOS 2017: 1-7 - [c100]Tobias Lieske, Benjamin Pfundt, Steffen Vaas, Marc Reichenbach, Dietmar Fey:
System on chip generation for multi-sensor and sensor fusion applications. SAMOS 2017: 20-29 - [c99]Johannes Hofmann, Georg Hager, Gerhard Wellein, Dietmar Fey:
An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors. ISC 2017: 294-314 - [c98]Hoang Anh Du Nguyen, Jintao Yu, Lei Xie, Mottaqiallah Taouil, Said Hamdioui, Dietmar Fey:
Memristive devices for computing: Beyond CMOS and beyond von Neumann. VLSI-SoC 2017: 1-10 - [i11]Dietmar Fey:
Evaluating Ternary Adders using a hybrid Memristor / CMOS approach. CoRR abs/1701.00065 (2017) - [i10]Johannes Hofmann, Georg Hager, Gerhard Wellein, Dietmar Fey:
An analysis of core- and chip-level architectural features in four generations of Intel server processors. CoRR abs/1702.07554 (2017) - 2016
- [c97]Konrad Häublein, Christian Hartmann, Marc Reichenbach, Dietmar Fey:
Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks. ARC 2016: 303-311 - [c96]Johannes Hofmann, Dietmar Fey, Jan Eitzinger, Georg Hager, Gerhard Wellein:
Analysis of Intel's Haswell Microarchitecture Using the ECM Model and Microbenchmarks. ARCS 2016: 210-222 - [c95]Steffen Limmer, Dietmar Fey:
Investigation of strategies for an increasing population size in multi-objective CMA-ES. CEC 2016: 476-483 - [c94]Benjamin Pfundt, Marc Reichenbach, Christian Hartmann, Konrad Häublein, Dietmar Fey:
Teaching heterogeneous computer architectures using smart camera systems. EWME 2016: 1-6 - [c93]Arne Hendricks, Thomas Heller, Andreas Schäfer, Maximilian Kasparek, Dietmar Fey:
Evaluating Performance and Energy-Efficiency of a Parallel Signal Correlation Algorithm on Current Multi and Manycore Architectures. ICCS 2016: 1566-1576 - [c92]Steffen Vaas, Marc Reichenbach, Dietmar Fey:
An Application-Specific Instruction Set Processor for Power Quality Monitoring. IPDPS Workshops 2016: 181-188 - [c91]Franz Richter-Gottfried, Patrick Kreutzer, Alexander Ditter, Max Schneider, Dietmar Fey:
C++ Classes and Templates for OpenCL Kernels with PATOS. IWOCL 2016: 22:1-22:3 - [c90]Dietmar Fey, Marc Reichenbach, Christopher Söll, Mehrdad Biglari, Jürgen Röber, Robert Weigel:
Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits. MEMSYS 2016: 442-454 - [c89]Tobias Lieske, Marc Reichenbach, Burkhard Ringlein, Dietmar Fey:
Dataflow optimization for programmable embedded image preprocessing accelerators. ReConFig 2016: 1-8 - [c88]Steffen Vaas, Marc Reichenbach, Ulrich Margull, Dietmar Fey:
The R2-D2 toolchain - Automated porting of safety-critical applications to FPGAs. ReConFig 2016: 1-7 - [c87]Konrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Ozkan, Dietmar Fey, Frank Hannig, Jürgen Teich:
Hybrid code description for developing fast and resource efficient image processing architectures. SAMOS 2016: 211-218 - [c86]Arne Hendricks, Thomas Heller, Herbert Jordan, Peter Thoman, Thomas Fahringer, Dietmar Fey:
The AllScale Runtime Interface - Theoretical Foundation and Concept. MTAGS@SC 2016: 13-19 - [c85]Johannes Hofmann, Dietmar Fey:
An ECM-based Energy-Efficiency Optimization Approach for Bandwidth-Limited Streaming Kernels on Recent Intel Xeon Processors. E2SC@SC 2016: 31-38 - [c84]Dominik Schoenwetter, Alexander Ditter, Dietmar Fey, Ralph Mader:
Improving instruction accurate simulation for parallel automotive applications. SIES 2016: 211-214 - [c83]Dominik Schoenwetter, Alexander Ditter, Vadym Aizinger, Balthasar Reuter, Dietmar Fey:
Cache Aware Instruction Accurate Simulation of a 3-D Coastal Ocean Model on Low Power Hardware. SIMULTECH 2016: 129-137 - [c82]Bruno Kleinert, Franziska Schäfer, Jupiter Bakakeu, Simone Weiß, Dietmar Fey:
Hardware-software Co-simulation of Self-organizing Smart Home Networks - Who am I and Where Are the Others?. SIMULTECH 2016: 304-311 - [c81]Bruno Kleinert, Simone Weiß, Franziska Schäfer, Jupiter Bakakeu, Dietmar Fey:
Adaptive Synchronization Interface for Hardware-Software Co-Simulation based on SystemC and QEMU. SimuTools 2016: 28-36 - [c80]Thomas Heller, Hartmut Kaiser, Patrick Diehl, Dietmar Fey, Marc Alexander Schweitzer:
Closing the Performance Gap with Modern C++. ISC Workshops 2016: 18-31 - [e3]Frank Hannig, João M. P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich:
Architecture of Computing Systems - ARCS 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings. Lecture Notes in Computer Science 9637, Springer 2016, ISBN 978-3-319-30694-0 [contents] - [i9]Johannes Hofmann, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, Gerhard Wellein:
Performance analysis of the Kahan-enhanced scalar product on current multi- and manycore processors. CoRR abs/1604.01890 (2016) - [i8]Johannes Hofmann, Dietmar Fey:
An ECM-based energy-efficiency optimization approach for bandwidth-limited streaming kernels on recent Intel Xeon processors. CoRR abs/1609.03347 (2016) - 2015
- [j14]Oliver Reiche, Konrad Häublein, Marc Reichenbach, Moritz Schmid, Frank Hannig, Jürgen Teich, Dietmar Fey:
Synthesis and optimization of image processing accelerators using domain knowledge. J. Syst. Archit. 61(10): 646-658 (2015) - [c79]Marc Reichenbach, Maximilian Kasparek, Mohammad Alawieh, Konrad Häublein, Dietmar Fey:
Real-time correlation for locating systems utilizing heterogeneous computing architectures. DASIP 2015: 1-8 - [c78]Dietmar Fey, Jonathan Martschinke:
Architecture and simulation of a hybrid memristive multiplier network using redundant number representation. IJCNN 2015: 1-6 - [c77]Christian Herglotz, Jürgen Seiler, André Kaup, Arne Hendricks, Marc Reichenbach, Dietmar Fey:
Estimation of Non-functional Properties for Embedded Hardware with Application to Image Processing. IPDPS Workshops 2015: 190-195 - [c76]Johannes Hofmann, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, Gerhard Wellein:
Performance Analysis of the Kahan-Enhanced Scalar Product on Current Multicore Processors. PPAM (1) 2015: 63-73 - [c75]Marc Reichenbach, Tobias Lieske, Steffen Vaas, Konrad Häublein, Dietmar Fey:
FAUPU - A design framework for the development of programmable image processing architectures. ReConFig 2015: 1-8 - [c74]Marc Reichenbach, Benjamin Pfundt, Dietmar Fey:
Framework for parameter analysis of FPGA-based image processing architectures. SAMOS 2015: 96-102 - [c73]Hartmut Kaiser, Thomas Heller, Daniel Bourgeois, Dietmar Fey:
Higher-level parallelization for local and distributed asynchronous task-based programming. ESPM@SC 2015: 29-37 - [c72]Dominik Schoenwetter, Alexander Ditter, Bruno Kleinert, Arne Hendricks, Vadym Aizinger, Dietmar Fey:
Virtualization Guided Tsunami and Storm Surge Simulations for Low Power Architectures. SIMULTECH (Selected Papers) 2015: 99-114 - [c71]Dominik Schoenwetter, Alexander Ditter, Bruno Kleinert, Arne Hendricks, Vadym Aizinger, Harald Köstler, Dietmar Fey:
Tsunami and Storm Surge Simulation Using Low Power Architectures - Concept and Evaluation. SIMULTECH 2015: 377-382 - [c70]Dominik Schoenwetter, Ronald Veldema, Dietmar Fey:
FREACSIM: a framework for creating and simulating real-time capable network on chip systems and applications. SimuTools 2015: 208-217 - [c69]