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ORCIDPaolo Ienne
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- affiliation: Swiss Federal Institute of Technology in Lausanne, Switzerland
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2020 – today
- 2020
[j43]Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu:
Many-Core Clique Enumeration with Fast Set Intersections. Proc. VLDB Endow. 13(11): 2676-2690 (2020)- [c153]Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort. ASAP 2020: 133-140 - [c152]Lana Josipovic, Andrea Guerrieri, Paolo Ienne:
Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. FPGA 2020: 1-10 - [c151]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. FPGA 2020: 150-160 - [c150]Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella:
Buffer Placement and Sizing for High-Performance Dataflow Circuits. FPGA 2020: 186-196 - [c149]Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson:
Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA 2020: 288-298 - [c148]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. FPL 2020: 153-161 - [c147]Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu:
Parallelizing Maximal Clique Enumeration on Modern Manycore Processors. IPDPS Workshops 2020: 211-214
2010 – 2019
- 2019
- [j42]Andrea Guerrieri
, Sahand Kashani-Akhavan, Mikhail Asiatici, Paolo Ienne:
Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips. IEEE Access 7: 103938-103947 (2019) - [c146]Lana Josipovic, Andrea Guerrieri, Paolo Ienne:
Speculative Dataflow Circuits. FPGA 2019: 162-171 - [c145]Anastasiia Kucherenko, Stefan Nikolic, Paolo Ienne:
On Feasibility of FPGAs Without Dedicated Programmable Interconnect Structure. FPGA 2019: 188 - [c144]Mikhail Asiatici, Paolo Ienne:
Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs. FPGA 2019: 310-319 - [c143]Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Finding a Needle in the Haystack of Hardened Interconnect Patterns. FPL 2019: 31-37 - [c142]Mikhail Asiatici, Paolo Ienne:
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. FPL 2019: 254-262 - [c141]Gabor Csordas, Mikhail Asiatici, Paolo Ienne:
In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA. FPT 2019: 188-196 - [c140]Lana Josipovic, Atri Bhattacharyya, Andrea Guerrieri, Paolo Ienne:
Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs. FPT 2019: 197-205 - 2018
- [c139]Andrea Guerrieri, Sahand Kashani-Akhavan, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne:
A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing. AHS 2018: 74-81 - [c138]Lana Josipovic, Radhika Ghosal, Paolo Ienne:
Dynamically Scheduled High-level Synthesis. FPGA 2018: 127-136 - [c137]Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS5)(Abstract Only). FPGA 2018: 294 - [c136]Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne:
LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only). FPGA 2018: 295 - [c135]João Vieira, Nuno Roma, Pedro Tomás, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
Exploiting Compute Caches for Memory Bound Vector Operations. SBAC-PAD 2018: 197-200 - [p2]Ana Petkovska, Alan Mishchenko, David Novo, Muhsen Owaida, Paolo Ienne:
Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver. Advanced Logic Synthesis 2018: 169-188 - 2017
- [j41]Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Virtualized Execution Runtime for FPGA Accelerators in the Cloud. IEEE Access 5: 1900-1910 (2017) - [j40]João Andrade, Nithin George, Kimon Karras, David Novo, Frederico Pratas, Leonel Sousa, Paolo Ienne, Gabriel Falcão, Vítor Silva:
Design Space Exploration of LDPC Decoders Using High-Level Synthesis. IEEE Access 5: 14600-14615 (2017) - [j39]Zidong Du, Shaoli Liu, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Qi Guo, Xiaobing Feng, Yunji Chen, Olivier Temam:
An Accelerator for High Efficient Vision Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 227-240 (2017) - [j38]Lana Josipovic, Philip Brisk, Paolo Ienne:
An Out-of-Order Load-Store Queue for Spatial Computing. ACM Trans. Embed. Comput. Syst. 16(5s): 125:1-125:19 (2017) - [c134]Lana Josipovic, Philip Brisk, Paolo Ienne:
From C to elastic circuits. ACSSC 2017: 121-125 - [c133]Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne:
Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. DAC 2017: 5:1-5:6 - [c132]Lana Josipovic, Philip Brisk, Paolo Ienne:
An Out-of-Order Load-Store Queue for Spatial Computing. FCCM 2017: 134 - [c131]Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang:
NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. FPGA 2017: 135-140 - [c130]Grace Zgheib, Paolo Ienne:
Evaluating FPGA clusters under wide ranges of design parameters. FPL 2017: 1-8 - [c129]Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI 2017: 131-136 - 2016
- [j37]Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad:
Introduction: Special Section on Architecture of Future Many Core Systems. Microprocess. Microsystems 46: 219-220 (2016) - [j36]Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad:
Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems. IEEE Trans. Computers 65(4): 1006-1009 (2016) - [j35]Paolo Ienne, Jean-Pierre Talpin:
Guest Editorial: Special Issue on Models and Methodologies for System Design. ACM Trans. Embed. Comput. Syst. 15(2): 29:1-29:2 (2016) - [j34]Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi:
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3489-3498 (2016) - [c128]Francesco Regazzoni, Paolo Ienne:
Instruction Set Extensions for secure applications. DATE 2016: 1529-1534 - [c127]Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne:
FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. FPGA 2016: 80-89 - [c126]Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Designing a virtual runtime for FPGA accelerators in the cloud. FPL 2016: 1-2 - [c125]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
Preface. FPL 2016: 1 - [c124]Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko:
Fast hierarchical NPN classification. FPL 2016: 1-4 - [c123]Lana Josipovic, Nithin George, Paolo Ienne:
Enriching C-based High-Level Synthesis with parallel pattern templates. FPT 2016: 177-180 - [c122]Grace Zgheib, Paolo Ienne:
Automatic wire modeling to explore novel FPGA architectures. FPT 2016: 181-184 - [c121]Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne:
Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD 2016: 4 - [c120]Wei Hu, Andrew Becker, Armita Ardeshiricham, Yu Tai, Paolo Ienne, Dejun Mu, Ryan Kastner:
Imprecise security: quality and complexity tradeoffs for hardware information flow tracking. ICCAD 2016: 95 - [c119]Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli:
Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT 2016: 212-227 - [e4]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016. IEEE 2016, ISBN 978-2-8399-1844-2 [contents] - 2015
- [j33]Ali Galip Bayrak, Francesco Regazzoni, David Novo, Philip Brisk, François-Xavier Standaert, Paolo Ienne:
Automatic Application of Power Analysis Countermeasures. IEEE Trans. Computers 64(2): 329-341 (2015) - [j32]Xavier Jimenez, David Novo, Paolo Ienne:
Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash. ACM Trans. Embed. Comput. Syst. 14(2): 28:1-28:22 (2015) - [j31]Muhsen Owaida, Gabriel Falcão, João Andrade, Christos D. Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, Paolo Ienne:
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs. ACM Trans. Embed. Comput. Syst. 14(2): 33:1-33:23 (2015) - [c118]Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu:
Retraining-based timing error mitigation for hardware neural networks. DATE 2015: 593-596 - [c117]João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders. FCCM 2015: 97 - [c116]João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. FPL 2015: 1-8 - [c115]Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, Paolo Ienne:
Automatic support for multi-module parallelism from computational patterns. FPL 2015: 1-8 - [c114]Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne:
A technology mapper for depth-constrained FPGA logic cells. FPL 2015: 1-8 - [c113]Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne:
Improved carry chain mapping for the VTR flow. FPT 2015: 80-87 - [c112]Andrew Becker, Djordje Maksimovic, David Novo, Mohsen Ewaida, Andreas G. Veneris, Barbara Jobstmann, Paolo Ienne:
FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction. Haifa Verification Conference 2015: 259-275 - [c111]Zidong Du, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Xiaobing Feng, Yunji Chen, Olivier Temam:
ShiDianNao: shifting vision processing closer to the sensor. ISCA 2015: 92-104 - [c110]Panagiotis Skrimponis, Georgios Zindros, Ioannis Parnassos, Muhsen Owaida, Nikolaos Bellas, Paolo Ienne:
Exploring Automatically Generated Platforms in High Performance FPGAs. PARCO 2015: 563-570 - [e3]Yunji Chen, Paolo Ienne, Qing Ji:
Advanced Parallel Processing Technologies - 11th International Symposium, APPT 2015, Jinan, China, August 20-21, 2015, Proceedings. Lecture Notes in Computer Science 9231, Springer 2015, ISBN 978-3-319-23215-7 [contents] - 2014
- [j30]Walid A. Najjar, Paolo Ienne:
Reconfigurable Computing. IEEE Micro 34(1): 4-6 (2014) - [j29]Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage. ACM Trans. Archit. Code Optim. 11(2): 15:1-15:26 (2014) - [j28]Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 62-75 (2014) - [c109]Jing Huang, Yuanjie Huang, Olivier Temam, Paolo Ienne, Yunji Chen, Chengyong Wu:
A low-cost memory interface for high-throughput accelerators. CASES 2014: 11:1-11:10 - [c108]Andrew Becker, David Novo, Paolo Ienne:
SKETCHILOG: Sketching combinational circuits. DATE 2014: 1-4 - [c107]David Novo, Nazanin Farahpour, Paolo Ienne, Ubaid Ahmad, Francky Catthoor:
Energy efficient MIMO processing: A case study of opportunistic run-time approximations. DATE 2014: 1-6 - [c106]Xavier Jimenez, David Novo, Paolo Ienne:
Wear unleveling: improving NAND flash lifetime by balancing page endurance. FAST 2014: 47-59 - [c105]Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne:
Revisiting and-inverter cones. FPGA 2014: 45-54 - [c104]Nithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne:
Hardware system synthesis from Domain-Specific Languages. FPL 2014: 1-8 - [c103]Ana Petkovska, David Novo, Alan Mishchenko, Paolo Ienne:
Constrained interpolation for guided logic synthesis. ICCAD 2014: 462-469 - 2013
- [j27]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 681-694 (2013) - [c102]Andrew Becker, David Novo, Paolo Ienne:
Automated circuit elaboration from incomplete architectural descriptions. ACSSC 2013: 391-395 - [c101]Ali Galip Bayrak, Francesco Regazzoni, David Novo, Paolo Ienne:
Sleuth: Automated Verification of Software Power Analysis Countermeasures. CHES 2013: 293-310 - [c100]David Novo, Sara El Alaoui, Paolo Ienne:
Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems. DATE 2013: 15-20 - [c99]Xavier Jimenez, David Novo, Paolo Ienne:
Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime. DATE 2013: 226-229 - [c98]Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne:
An EDA-friendly protection scheme against side-channel attacks. DATE 2013: 410-415 - [c97]Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis:
Fast and accurate BER estimation methodology for I/O links based on extreme value theory. DATE 2013: 503-508 - [c96]Madhura Purnaprajna, Paolo Ienne:
A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. FCCM 2013: 53-56 - [c95]Yuanjie Huang, Paolo Ienne, Olivier Temam, Yunji Chen, Chengyong Wu:
Elastic CGRAs. FPGA 2013: 171-180 - [c94]Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA 2013: 279 - [c93]Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow And-Inverter Cones. FPL 2013: 1-4 - [c92]Nithin George, David Novo, Tiark Rompf, Martin Odersky, Paolo Ienne:
Making domain-specific hardware synthesis tools cost-efficient. FPT 2013: 120-127 - [c91]Lunkai Zhang, Mingzhe Zhang, Lingjun Fan, Da Wang, Paolo Ienne:
Spontaneous Reload Cache: Mimicking a Larger Cache with Minimal Hardware Requirement. NAS 2013: 31-40 - [c90]David Novo, I. Tzimi, Ubaid Ahmad, Paolo Ienne, Francky Catthoor:
Cracking the complexity of fixed-point refinement in complex wireless systems. SiPS 2013: 18-23 - 2012
- [j26]Ali Galip Bayrak, Nikola Velickovic, Paolo Ienne, Wayne P. Burleson:
An architecture-independent instruction shuffler to protect against side-channel attacks. ACM Trans. Archit. Code Optim. 8(4): 20:1-20:19 (2012) - [j25]Madhura Purnaprajna, Paolo Ienne:
Making wide-issue VLIW processors viable on FPGAs. ACM Trans. Archit. Code Optim. 8(4): 33:1-33:16 (2012) - [j24]Elisardo Antelo, David Hough, Paolo Ienne:
Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 61(8): 1057-1058 (2012) - [c89]Xavier Jimenez, David Novo, Paolo Ienne:
Software controlled cell bit-density to improve NAND flash lifetime. DAC 2012: 229-234 - [c88]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective flexibility: Breaking the rigidity of datapath merging. DATE 2012: 1543-1548 - [c87]Shuai Jiao, Paolo Ienne, Xiaochun Ye, Da Wang, Dongrui Fan, Ninghui Sun:
CRAW/P: A Workload Partition Method for the Efficient Parallel Simulation of Manycores. Euro-Par 2012: 102-114 - [c86]Gabriel Falcão, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne:
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. FCCM 2012: 224-231 - [c85]Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne:
Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. FPGA 2012: 119-128 - [c84]Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk:
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264 - [c83]Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Counting stream registers: An efficient and effective snoop filter architecture. ICSAMOS 2012: 120-127 - [p1]Francesco Regazzoni, Luca Breveglieri, Paolo Ienne, Israel Koren:
Interaction Between Fault Attack Countermeasures and the Resistance Against Power Analysis Attacks. Fault Analysis in Cryptography 2012: 257-272 - 2011
- [j23]Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne:
Compressor tree synthesis on commercial high-performance FPGAs. ACM Trans. Reconfigurable Technol. Syst. 4(4): 39:1-39:19 (2011) - [c82]Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert, Paolo Ienne:
A first step towards automatic application of power analysis countermeasures. DAC 2011: 230-235 - [c81]Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici:
Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. DAC 2011: 1014-1019 - [c80]Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne:
Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA 2011: 237-246 - [c79]Hadi Parandeh-Afshar, Paolo Ienne:
Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs. FPL 2011: 225-231 - [e2]Elisardo Antelo, David Hough, Paolo Ienne:
20th IEEE Symposium on Computer Arithmetic, ARITH 2011, Tübingen, Germany, 25-27 July 2011. IEEE Computer Society 2011, ISBN 978-0-7695-4318-5 [contents] - [e1]Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca:
22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1291-3 [contents] - 2010
- [j22]Ajay K. Verma, Philip Brisk, Paolo Ienne:
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 341-354 (2010) - [j21]Philip Brisk, Ajay K. Verma, Paolo Ienne:
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1096-1109 (2010) - [j20]Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Paolo Ienne:
Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 578-590 (2010) - [c78]Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul:
A high-level synthesis flow for custom instruction set extensions for application-specific processors. ASP-DAC 2010: 707-712 - [c77]Hadi Parandeh-Afshar, Paolo Ienne:
Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. FCCM 2010: 229-236 - [c76]Amit Verma, Ajay K. Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL 2010: 19-24 - [c75]Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. HiPEAC 2010: 126-140 - [c74]Xiaochun Ye, Dongrui Fan, Wei Lin, Nan Yuan, Paolo Ienne:
High performance comparison-based sorting algorithm on many-core GPUs. IPDPS 2010: 1-10
2000 – 2009
- 2009
- [j19]Philip Brisk, Ajay K. Verma, Paolo Ienne:
Optimistic chordal coloring: a coalescing heuristic for SSA form programs. Des. Autom. Embed. Syst. 13(1-2): 115-137 (2009) - [j18]Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne:
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Trans. Comput. Sci. 4: 230-243 (2009) - [j17]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 13:1-13:36 (2009) - [j16]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. ACM Trans. Reconfigurable Technol. Syst. 2(3): 19:1-19:42 (2009) - [c73]Ajay K. Verma, Philip Brisk, Paolo Ienne:
Challenges in Automatic Optimization of Arithmetic Circuits. IEEE Symposium on Computer Arithmetic 2009: 213-218 - [c72]Amit Verma, Ajay K. Verma, Philip Brisk, Paolo Ienne:
Hybrid LZA: a near optimal implementation of the leading zero anticipator. ASP-DAC 2009: 203-209 - [c71]Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES 2009: 205-219 - [c70]Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon:
Way Stealing: cache-assisted automatic instruction set extensions. DAC 2009: 31-36 - [c69]Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne:
FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. FCCM 2009: 267-270 - [c68]