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ORCIDYinhe Han 0001
Person information
- affiliation: Chinese Academy of Sciences, Institute of Computing Technology, Research Center for Intelligent Computing Systems, Beijing, China
- affiliation: Chinese Academy of Sciences, Institute of Computing Technology, State Key Laboratory of Computer Architecture, Beijing, China
- affiliation (PhD 2006): Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China
Other persons with the same name
- Yinhe Han — disambiguation page
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Journal Articles
- 2024
[j79]Yuxin Yang
, Xiaoming Chen, Yinhe Han:
JANM-IK: Jacobian Argumented Nelder-Mead Algorithm for Inverse Kinematics and its Hardware Acceleration. IEEE Comput. Archit. Lett. 23(1): 45-48 (2024)- [j78]Xiaoyu Zhang, Zerun Li, Rui Liu, Xiaoming Chen, Yinhe Han:
GAS: General-Purpose In-Memory-Computing Accelerator for Sparse Matrix Multiplication. IEEE Trans. Computers 73(6): 1427-1441 (2024) - [j77]Lian Liu, Ying Wang, Xiandong Zhao, Weiwei Chen, Huawei Li, Xiaowei Li, Yinhe Han:
An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1497-1510 (2024) - [j76]Wanqian Li, Yinhe Han, Xiaoming Chen:
Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators. ACM Trans. Design Autom. Electr. Syst. 29(1): 21:1-21:24 (2024) - 2023
- [j75]Chengsi Gao, Ying Wang, Yinhe Han, Weiwei Chen, Lei Zhang:
IVP: An Intelligent Video Processing Architecture for Video Streaming. IEEE Trans. Computers 72(1): 264-277 (2023) - [j74]Rui Liu, Xiaoyu Zhang, Zhiwen Xie, Xinyu Wang, Zerun Li, Xiaoming Chen, Yinhe Han, Minghua Tang:
FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2889-2902 (2023) - [j73]Bosheng Liu, Zhuoshen Jiang, Yalan Wu, Jigang Wu, Xiaoming Chen, Peng Liu, Qingguo Zhou, Yinhe Han:
Frequency-Domain Inference Acceleration for Convolutional Neural Networks Using ReRAMs. IEEE Trans. Parallel Distributed Syst. 34(12): 3133-3146 (2023) - 2022
- [j72]Hang Xiao, Haobo Xu, Ying Wang, Yujie Wang, Yinhe Han:
LINAC: A Spatially Linear Accelerator for Convolutional Neural Networks. IEEE Comput. Archit. Lett. 21(1): 29-32 (2022) - [j71]Xiaohan Ma, Ying Wang, Yujie Wang, Xuyi Cai, Yinhe Han:
Survey on chiplets: interface, interconnect and integration methodology. CCF Trans. High Perform. Comput. 4(1): 43-52 (2022) - [j70]Hang Xiao, Haobo Xu, Xiaoming Chen, Yujie Wang, Yinhe Han:
Fast and High-Accuracy Approximate MAC Unit Design for CNN Computing. IEEE Embed. Syst. Lett. 14(3): 155-158 (2022) - [j69]Feng Min, Ying Wang, Haobo Xu, Junpei Huang, Yujie Wang, Xingqi Zou, Meixuan Lu, Yinhe Han:
Dadu-SV: Accelerate Stereo Vision Processing on NPU. IEEE Embed. Syst. Lett. 14(4): 191-194 (2022) - [j68]Zihao Sun, Yu Hu, Longxing Yang, Shun Lu, Jilin Mei, Yinhe Han, Xiaowei Li:
STC-NAS: Fast neural architecture search with source-target consistency. Neurocomputing 497: 227-238 (2022) - [j67]Yalan Wu, Jigang Wu, Peng Liu, Yinhe Han, Thambipillai Srikanthan:
Reconfiguration algorithms for synchronous communication on switch based degradable arrays. Parallel Comput. 111: 102901 (2022) - [j66]Weidong Cao, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, Li Jiang:
Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals. IEEE Trans. Computers 71(9): 2142-2155 (2022) - [j65]Bosheng Liu, Xiaoming Chen, Yinhe Han, Jigang Wu, Liang Chang, Peng Liu, Haobo Xu:
Search-Free Inference Acceleration for Sparse Convolutional Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2156-2169 (2022) - [j64]Weiwei Chen, Ying Wang, Ying Xu, Chengsi Gao, Yinhe Han, Lei Zhang:
Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 3993-4003 (2022) - [j63]Xiaoyu Zhang, Rui Liu, Tao Song, Yuxin Yang, Yinhe Han, Xiaoming Chen:
Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5071-5084 (2022) - [j62]Haobo Xu, Yuxin Yang, Feng Min, Junpei Huang, Xiaoming Chen, Yinhe Han, Ninghui Sun:
Toward Efficient Computing for Robotics: From a Circuit and System View. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3051-3056 (2022) - [j61]Yalan Wu, Jigang Wu, Long Chen, Jiaquan Yan, Yinhe Han:
Load Balance Guaranteed Vehicle-to-Vehicle Computation Offloading for Min-Max Fairness in VANETs. IEEE Trans. Intell. Transp. Syst. 23(8): 11994-12013 (2022) - 2021
- [j60]Xingqi Zou, Sheng Xu, Xiaoming Chen, Liang Yan, Yinhe Han:
Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology. Sci. China Inf. Sci. 64(6) (2021) - [j59]Feng Min, Haobo Xu, Ying Wang, Yujie Wang, Jiajun Li, Xingqi Zou, Bei Li, Yinhe Han:
Dadu-Eye: A 5.3 TOPS/W, 30 fps/1080p High Accuracy Stereo Vision Accelerator. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4207-4220 (2021) - [j58]Peng Liu, Zhiqiang You, Jigang Wu, Bosheng Liu, Yinhe Han, Krishnendu Chakrabarty:
Fault Modeling and Efficient Testing of Memristor-Based Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4444-4455 (2021) - [j57]Lian Yao, Peng Liu, Jigang Wu, Yinhe Han, Yuehang Zhong, Zhiqiang You:
Integrating Two Logics Into One Crossbar Array for Logic Gate Design. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2987-2991 (2021) - [j56]Peng Liu, Zhiqiang You, Jigang Wu, Michael Elimu, Weizheng Wang, Shuo Cai, Yinhe Han:
Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory. IEEE Trans. Emerg. Top. Comput. 9(2): 745-758 (2021) - [j55]Peipei Yin, Chenghua Wang, Haroon Waris, Weiqiang Liu, Yinhe Han, Fabrizio Lombardi:
Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning. IEEE Trans. Sustain. Comput. 6(4): 612-625 (2021) - 2020
- [j54]Hang Lu, Mingzhe Zhang, Yinhe Han, Qi Wang, Huawei Li, Xiaowei Li:
Architecting Effectual Computation for Machine Learning Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2654-2667 (2020) - [j53]Bosheng Liu, Xiaoming Chen, Yinhe Han, Haobo Xu:
Swallow: A Versatile Accelerator for Sparse Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4881-4893 (2020) - 2019
- [j52]Sheng Xu, Xiaoming Chen, Ying Wang, Yinhe Han, Xuehai Qian, Xiaowei Li:
PIMSim: A Flexible and Detailed Processing-in-Memory Simulator. IEEE Comput. Archit. Lett. 18(1): 6-9 (2019) - [j51]Bosheng Liu, Xiaoming Chen, Yinhe Han, Jiajun Li, Haobo Xu, Xiaowei Li:
Accelerating DNN-based 3D point cloud processing for mobile computing. Sci. China Inf. Sci. 62(11): 212206:1-212206:11 (2019) - [j50]Shichang Zhang, Ying Wang, Xiaoming Chen, Yinhe Han, Yujie Wang, Xiaowei Li:
Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator. IEICE Electron. Express 16(14): 20190145 (2019) - [j49]Xiaoming Chen, Kai Ni, Michael T. Niemier, Yinhe Han, Suman Datta, Xiaobo Sharon Hu:
Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(5): 1780-1793 (2019) - [j48]Xiaoming Chen, Danny Ziyi Chen, Yinhe Han, Xiaobo Sharon Hu:
moDNN: Memory Optimal Deep Neural Network Training on Graphics Processing Units. IEEE Trans. Parallel Distributed Syst. 30(3): 646-661 (2019) - 2018
- [j47]Faqiang Sun, Guihai Yan, Xin He, Huawei Li, Yinhe Han:
CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency. J. Comput. Sci. Technol. 33(1): 131-144 (2018) - [j46]Shiqi Lian, Ying Wang, Yinhe Han:
DimRouter: A Multi-Mode Router Architecture for Higher Energy-Proportionality of On-Chip Networks. J. Comput. Sci. Technol. 33(5): 984-997 (2018) - [j45]Yiming Zeng, Yu Hu, Shice Liu, Jing Ye, Yinhe Han, Xiaowei Li, Ninghui Sun:
RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving. IEEE Robotics Autom. Lett. 3(4): 3434-3440 (2018) - [j44]Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li:
A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1265-1277 (2018) - 2017
- [j43]Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li:
Retention-Aware DRAM Assembly and Repair for Future FGR Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 705-718 (2017) - [j42]Xin He, Shuhao Jiang, Wenyan Lu, Guihai Yan, Yinhe Han, Xiaowei Li:
Exploiting the Potential of Computation Reuse Through Approximate Computing. IEEE Trans. Multi Scale Comput. Syst. 3(3): 152-165 (2017) - [j41]Hang Lu, Guihai Yan, Yinhe Han, Xiaowei Li:
PowerTrader: Enforcing Autonomous Power Management for Future Large-Scale Many-Core Processors. IEEE Trans. Multi Scale Comput. Syst. 3(4): 283-295 (2017) - [j40]Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng, Xiaowei Li:
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1285-1296 (2017) - 2016
- [j39]Xin He, Guihai Yan, Yinhe Han, Xiaowei Li:
Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing. J. Comput. Sci. Technol. 31(2): 253-266 (2016) - [j38]Song Jin, Yinhe Han, Songwei Pei:
Statistical energy optimization on voltage-frequency island based MPSoCs in the presence of process variations. Microelectron. J. 54: 23-31 (2016) - [j37]Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li:
An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores. IEEE Trans. Computers 65(2): 367-381 (2016) - [j36]Song Jin, Songwei Pei, Yinhe Han, Huawei Li:
A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands. ACM Trans. Design Autom. Electr. Syst. 21(2): 27:1-27:14 (2016) - [j35]Guihai Yan, Jun Ma, Yinhe Han, Xiaowei Li:
EcoUp: Towards Economical Datacenter Upgrading. IEEE Trans. Parallel Distributed Syst. 27(7): 1968-1981 (2016) - [j34]Yinhe Han, Jianbo Dong, Kaiheng Weng, Ying Wang, Xiaowei Li:
Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 92-102 (2016) - [j33]Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li:
VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 858-870 (2016) - [j32]Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li:
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1613-1625 (2016) - 2015
- [j31]Bosheng Liu, Ying Wang, Zhiqiang You, Yinhe Han, Xiaowei Li:
A signal degradation reduction method for memristor ratioed logic (MRL) gates. IEICE Electron. Express 12(8): 20150062 (2015) - [j30]Ying Wang, Yinhe Han, Lei Zhang, Binzhang Fu, Cheng Liu, Huawei Li, Xiaowei Li:
Economizing TSV Resources in 3-D Network-on-Chip Design. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 493-506 (2015) - [j29]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li:
Data Remapping for Static NUCA in Degradable Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 879-892 (2015) - [j28]Hang Lu, Binzhang Fu, Ying Wang, Yinhe Han, Guihai Yan, Xiaowei Li:
RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 3053-3064 (2015) - 2014
- [j27]Peng Chen, Lei Zhang, Yinhe Han, Yunji Chen:
A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications. J. Comput. Sci. Technol. 29(2): 239-246 (2014) - [j26]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li:
Reinventing Memory System Design for Many-Accelerator Architecture. J. Comput. Sci. Technol. 29(2): 273-280 (2014) - [j25]Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li:
SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor. ACM Trans. Design Autom. Electr. Syst. 20(1): 8:1-8:16 (2014) - [j24]Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li:
ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 113-126 (2014) - [j23]Dawen Xu, Huawei Li, Amirali Ghofrani, Kwang-Ting Cheng, Yinhe Han, Xiaowei Li:
Test-Quality Optimization for Variable $n$ -Detections of Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1738-1749 (2014) - 2013
- [j22]Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li:
TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design. J. Comput. Sci. Technol. 28(1): 119-128 (2013) - [j21]Yinhe Han, Cheng Liu, Hang Lu, Wen-Bo Li, Lei Zhang, Xiaowei Li:
RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router. J. Comput. Sci. Technol. 28(6): 1045-1053 (2013) - [j20]Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li:
Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 239-249 (2013) - [j19]Song Jin, Yinhe Han, Huawei Li, Xiaowei Li:
Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 821-833 (2013) - 2012
- [j18]Song Jin, Yinhe Han:
M-IVC: Applying multiple input vectors to co-optimize aging and leakage. Microelectron. J. 43(11): 838-847 (2012) - 2011
- [j17]Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li:
A New Multiple-Round Dimension-Order Routing for Networks-on-Chip. IEICE Trans. Inf. Syst. 94-D(4): 809-821 (2011) - [j16]Song Jin, Yinhe Han, Huawei Li, Xiaowei Li:
Statistical lifetime reliability optimization considering joint effect of process variation and aging. Integr. 44(3): 185-191 (2011) - [j15]Guihai Yan, Yinhe Han, Xiaowei Li:
ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation. IEEE Trans. Computers 60(9): 1219-1232 (2011) - [j14]Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li:
MicroFix: Using timing interpolation and delay sensors for power reduction. ACM Trans. Design Autom. Electr. Syst. 16(2): 16:1-16:21 (2011) - [j13]Guihai Yan, Yinhe Han, Xiaowei Li:
SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1627-1640 (2011) - 2010
- [j12]Jianliang Gao, Yinhe Han, Xiaowei Li:
A Novel Post-Silicon Debug Mechanism Based on Suspect Window. IEICE Trans. Inf. Syst. 93-D(5): 1175-1185 (2010) - [j11]Jun Liu, Yinhe Han, Xiaowei Li:
Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power. IEICE Trans. Inf. Syst. 93-D(8): 2223-2232 (2010) - [j10]Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan, Xiaowei Li:
Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling. J. Syst. Archit. 56(10): 534-542 (2010) - 2009
- [j9]Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li:
On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1173-1186 (2009) - 2008
- [j8]Guihai Yan, Yinhe Han, Xiaowei Li, Hui Liu:
BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission. IEICE Trans. Electron. 91-C(10): 1690-1697 (2008) - 2007
- [j7]Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, You-Sheng Zhang:
Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment. J. Comput. Sci. Technol. 22(5): 673-680 (2007) - [j6]Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra:
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 531-540 (2007) - 2006
- [j5]Yinhe Han, Huawei Li, Xiaowei Li, Anshuman Chandra:
Response compaction for system-on-a-chip based on advanced convolutional codes. Sci. China Ser. F Inf. Sci. 49(2): 262-272 (2006) - [j4]Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen:
Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. IEICE Trans. Inf. Syst. 89-D(10): 2616-2625 (2006) - [j3]Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra:
Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes. IEEE Trans. Instrum. Meas. 55(2): 389-399 (2006) - 2005
- [j2]Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen:
Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. IEICE Trans. Inf. Syst. 88-D(9): 2126-2134 (2005) - [j1]Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra:
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. J. Comput. Sci. Technol. 20(2): 201-209 (2005)
Conference and Workshop Papers
- 2024
- [c127]Xiaoyang Lu, Boyu Long, Xiaoming Chen, Yinhe Han, Xian-He Sun:
ACES: Accelerating Sparse Matrix Multiplication with Adaptive Execution Flow and Concurrency-Aware Cache Optimizations. ASPLOS (3) 2024: 71-85 - [c126]Haoran Wang, Lei Wang, Haobo Xu, Ying Wang, Yuming Li, Yinhe Han:
PrimePar: Efficient Spatial-temporal Tensor Partitioning for Large Transformer Model Training. ASPLOS (3) 2024: 801-817 - [c125]Yuhui Hao, Yiming Gan, Bo Yu, Qiang Liu, Yinhe Han, Zishen Wan, Shaoshan Liu:
ORIANNA: An Accelerator Generation Framework for Optimization-based Robotic Applications. ASPLOS (2) 2024: 813-829 - [c124]Yibo Du, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han:
GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction. DATE 2024: 1-6 - [c123]Wanqian Li, Xiaotian Sun, Xinyu Wang, Lei Wang, Yinhe Han, Xiaoming Chen:
PIMSYN: Synthesizing Processing-in-Memory CNN Accelerators. DATE 2024: 1-6 - [c122]Xinyu Wang, Xiaotian Sun, Yinhe Han, Xiaoming Chen:
PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators. DATE 2024: 1-2 - 2023
- [c121]Bosheng Liu, Hongyi Liang, Jigang Wu, Xiaoming Chen, Peng Liu, Yinhe Han:
Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing Approach. ASP-DAC 2023: 733-738 - [c120]Cangyuan Li, Ying Wang, Huawei Li, Yinhe Han:
APPEND: Rethinking ASIP Synthesis in the Era of AI. DAC 2023: 1-6 - [c119]Xiaotian Sun, Xinyu Wang, Wanqian Li, Lei Wang, Yinhe Han, Xiaoming Chen:
PIMCOMP: A Universal Compilation Framework for Crossbar-based PIM DNN Accelerators. DAC 2023: 1-6 - [c118]Xiaoyu Zhang, Zerun Li, Rui Liu, Xiaoming Chen, Yinhe Han:
FSPA: An FeFET-based Sparse Matrix-Dense Vector Multiplication Accelerator. DAC 2023: 1-6 - [c117]Chengsi Gao, Ying Wang, Cheng Liu, Mengdi Wang, Weiwei Chen, Yinhe Han, Lei Zhang:
Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity. DATE 2023: 1-6 - [c116]Shixin Zhao, Songyun Qu, Ying Wang, Yinhe Han:
ENASA: Towards Edge Neural Architecture Search based on CIM acceleration. DATE 2023: 1-2 - [c115]Haoran Wang, Haobo Xu, Ying Wang, Yinhe Han:
CTA: Hardware-Software Co-design for Compressed Token Attention Mechanism. HPCA 2023: 429-441 - [c114]Boyu Long, Libo Shen, Xiaoyu Zhang, Yinhe Han, Xian-He Sun, Xiaoming Chen:
Meltrix: A RRAM-Based Polymorphic Architecture Enhanced by Function Synthesis. ICCAD 2023: 1-9 - [c113]Libo Shen, Boyu Long, Rui Liu, Xiaoyu Zhang, Yinhe Han, Xiaoming Chen:
LIM-GEN: A Data-Guided Framework for Automated Generation of Heterogeneous Logic-in-Memory Architecture. ICCAD 2023: 1-9 - [c112]Yilun Zhao, Yu Chen, He Li, Ying Wang, Kaiyan Chang, Bingmeng Wang, Bing Li, Yinhe Han:
Full State Quantum Circuit Simulation Beyond Memory Limit. ICCAD 2023: 1-9 - [c111]Yibo Du, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han:
PANG: A Pattern-Aware GCN Accelerator for Universal Graphs. ICCD 2023: 263-266 - [c110]Rui Tang, Xiaoyu Zhang, Rui Liu, Zhejian Luo, Xiaoming Chen, Yinhe Han:
Hardware-Software Co-Design for Content-Based Sparse Attention. ICCD 2023: 415-418 - [c109]Yuxin Yang, Xiaoming Chen, Yinhe Han:
Dadu-RBD: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines. MICRO 2023: 297-309 - 2022
- [c108]Zerun Li, Xiaoming Chen, Yinhe Han:
Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems. ASP-DAC 2022: 238-243 - [c107]Xiaoming Chen, Yinhe Han:
Solving Least-Squares Fitting in $O(1)$ Using RRAM-based Computing-in-Memory Technique. ASP-DAC 2022: 339-344 - [c106]Rui Liu, Xiaoyu Zhang, Xiaoming Chen, Yinhe Han, Minghua Tang:
FeMIC: Multi-Operands in-Memory Computing Based on FeFETs. ASP-DAC 2022: 678-683 - [c105]Zerun Li, Xiaoming Chen, Yinhe Han:
GraphRing: an HMC-ring based graph processing framework with optimized data movement. DAC 2022: 1063-1068 - [c104]Hang Xiao, Haobo Xu, Xiaoming Chen, Yujie Wang, Yinhe Han:
P3S: A High Accuracy Probabilistic Prediction Processing System for CNN Acceleration. ACM Great Lakes Symposium on VLSI 2022: 237-242 - [c103]Wanqian Li, Yinhe Han, Xiaoming Chen:
Energy-Efficient In-SRAM Accumulation for CMOS-based CNN Accelerators. ACM Great Lakes Symposium on VLSI 2022: 293-298 - [c102]Zhenyu Quan, Xiaoming Chen, Yinhe Han:
AIC-Bench: Workload Selection Methodology for Benchmarking AI Chips. HPCC/DSS/SmartCity/DependSys 2022: 687-694 - [c101]Zhiwen Xie, Yinhe Han, Xiaoming Chen:
PME: Processing-in-memory Masking and Encoding for Secure NVM. HPCC/DSS/SmartCity/DependSys 2022: 1501-1508 - [c100]Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li:
GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. ICCAD 2022: 42:1-42:9 - [c99]Zihao Sun, Yu Hu, Shun Lu, Longxing Yang, Jilin Mei, Yinhe Han, Xiaowei Li:
AGNAS: Attention-Guided Micro and Macro-Architecture Search. ICML 2022: 20777-20789 - [c98]Longxing Yang, Yu Hu, Shun Lu, Zihao Sun, Jilin Mei, Yinhe Han, Xiaowei Li:
Searching for BurgerFormer with Micro-Meso-Macro Space Design. ICML 2022: 25055-25069 - [c97]Jingyu Niu, Yu Hu, Wei Li, Guangyan Huang, Yinhe Han, Xiaowei Li:
Closing the Dynamics Gap via Adversarial and Reinforcement Learning for High-Speed Racing. IJCNN 2022: 1-10 - [c96]Xuyi Cai, Ying Wang, Xiaohan Ma, Yinhe Han, Lei Zhang:
DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture. MICRO 2022: 1396-1413 - 2021
- [c95]Longxing Yang, Yu Hu, Shun Lu, Zihao Sun, Jilin Mei, Yiming Zeng, Zhiping Shi, Yinhe Han, Xiaowei Li:
DDSAS: Dynamic and Differentiable Space-Architecture Search. ACML 2021: 284-299 - [c94]Xiaoming Chen, Yuping Wu, Yinhe Han:
FePIM: Contention-Free In-Memory Computing Based on Ferroelectric Field-Effect Transistors. ASP-DAC 2021: 114-119 - [c93]Bosheng Liu, Zhuoshen Jiang, Jigang Wu, Xiaoming Chen, Yinhe Han, Peng Liu:
F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM. DAC 2021: 571-576 - [c92]Tao Song, Xiaoming Chen, Xiaoyu Zhang, Yinhe Han:
BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory System. DAC 2021: 1033-1038 - [c91]Tao Song, Xiaoming Chen, Yinhe Han:
Eliminating Iterations of Iterative Methods: Solving Large-Scale Sparse Linear System in O(1) with RRAM-based In-Memory Accelerator. ACM Great Lakes Symposium on VLSI 2021: 71-76 - [c90]Wei Li, Yu Hu, Yinhe Han, Xiaowei Li:
KFS-LIO: Key-Feature Selection for Lightweight Lidar Inertial Odometry. ICRA 2021: 5042-5048 - [c89]Liang Yan, Mingzhe Zhang, Rujia Wang, Xiaoming Chen, Xingqi Zou, Xiaoyang Lu, Yinhe Han, Xian-He Sun:
CoPIM: A Concurrency-aware PIM Workload Offloading Architecture for Graph Applications. ISLPED 2021: 1-6 - [c88]Xiaoming Chen, Tao Song, Yinhe Han:
RRAM-based Analog In-Memory Computing : Invited Paper. NANOARCH 2021: 1-6 - 2020
- [c87]Zhao Wang, Yijin Guan, Guangyu Sun, Dimin Niu, Yuhao Wang, Hongzhong Zheng, Yinhe Han:
GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks. ACA 2020: 73-86 - [c86]Bosheng Liu, Xiaoming Chen, Yinhe Han, Ying Wang, Jiajun Li, Haobo Xu, Xiaowei Li:
Search-free Accelerator for Sparse Convolutional Neural Networks. ASP-DAC 2020: 524-529 - [c85]Beibei Jin, Yu Hu, Qiankun Tang, Jingyu Niu, Zhiping Shi, Yinhe Han, Xiaowei Li:
Exploring Spatial-Temporal Multi-Frequency Analysis for High-Fidelity and Temporal-Consistency Video Prediction. CVPR 2020: 4553-4562 - [c84]Chaoqun Chu, Yanzhi Wang, Yilong Zhao, Xiaolong Ma, Shaokai Ye, Yunyan Hong, Xiaoyao Liang, Yinhe Han, Li Jiang:
PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture. DAC 2020: 1-6 - [c83]Yongchen Wang, Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li:
An Efficient Deep Learning Accelerator for Compressed Video Analysis. DAC 2020: 1-6 - [c82]Yuxin Yang, Xiaoming Chen, Yinhe Han:
Dadu-CD: Fast and Efficient Processing-in-Memory Accelerator for Collision Detection. DAC 2020: 1-6 - [c81]Sheng Xu, Xiaoming Chen, Xuehai Qian, Yinhe Han:
TUPIM: A Transparent and Universal Processing-in-Memory Architecture for Unmodified Binaries. ACM Great Lakes Symposium on VLSI 2020: 199-204 - [c80]Yuxin Yang, Shiqi Lian, Xiaoming Chen, Yinhe Han:
Accelerating RRT Motion Planning Using TCAM. ACM Great Lakes Symposium on VLSI 2020: 481-486 - [c79]Xiaoming Chen, Yinhe Han, Yu Wang:
Communication Lower Bound in Convolution Accelerators. HPCA 2020: 529-541 - [c78]Yinhe Han, Yuxin Yang, Xiaoming Chen, Shiqi Lian:
DaDu Series - Fast and Efficient Robot Accelerators. ICCAD 2020: 165:1-165:8 - [c77]Jingyu Niu, Yu Hu, Beibei Jin, Yinhe Han, Xiaowei Li:
Two-Stage Safe Reinforcement Learning for High-Speed Autonomous Racing. SMC 2020: 3934-3941 - 2019
- [c76]Sheng Xu, Xiaoming Chen, Ying Wang, Yinhe Han, Xiaowei Li:
CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems. ASP-DAC 2019: 140-145 - [c75]Jiajun Li, Ying Wang, Bosheng Liu, Yinhe Han, Xiaowei Li:
Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators. ASP-DAC 2019: 323-328 - [c74]Bosheng Liu, Xiaoming Chen, Ying Wang, Yinhe Han, Jiajun Li, Haobo Xu, Xiaowei Li:
Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators. ASP-DAC 2019: 733-738 - [c73]Xiaoyi Sun, Krishnendu Chakrabarty, Ruirui Huang, Yiquan Chen, Bing Zhao, Hai Cao, Yinhe Han, Xiaoyao Liang, Li Jiang:
System-level hardware failure prediction using deep learning. DAC 2019: 20 - [c72]Xiaoming Chen, Longxiang Yin, Bosheng Liu, Yinhe Han:
Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques. DAC 2019: 238 - [c71]Haobo Xu, Ying Wang, Yujie Wang, Jiajun Li, Bosheng Liu, Yinhe Han:
ACG-Engine: An Inference Accelerator for Content Generative Neural Networks. ICCAD 2019: 1-7 - [c70]Xiaoyu Zhang, Xiaoming Chen, Yinhe Han:
FeMAT: Exploring In-Memory Processing in Multifunctional FeFET-Based Memory Array. ICCD 2019: 541-549 - [c69]Huawei Li, Xiaowei Li, Yinhe Han:
China Test Conference (CTC) - Extending the Global Test Forum to China. ITC 2019: 1-4 - [c68]Yipei Yang, Jing Ye, Xiaowei Li, Yinhe Han, Huawei Li, Yu Hu:
Implementation of Parametric Hardware Trojan in FPGA. ITC-Asia 2019: 37-42 - 2018
- [c67]Sheng Xu, Ying Wang, Yinhe Han, Xiaowei Li:
PIMCH: Cooperative memory prefetching in processing-in-memory architecture. ASP-DAC 2018: 209-214 - [c66]Shiqi Lian, Yinhe Han, Xiaoming Chen, Ying Wang, Hang Xiao:
Dadu-P: a scalable accelerator for robot motion planning in a dynamic environment. DAC 2018: 109:1-109:6 - [c65]Ying Wang, Zhenyu Quan, Jiajun Li, Yinhe Han, Huawei Li, Xiaowei Li:
A retrospective evaluation of energy-efficient object detection solutions on embedded devices. DATE 2018: 709-714 - [c64]Shice Liu, Yu Hu, Yiming Zeng, Qiankun Tang, Beibei Jin, Yinhe Han, Xiaowei Li:
See and Think: Disentangling Semantic Scene Completion. NeurIPS 2018: 261-272 - 2017
- [c63]Cheng Wang, Ying Wang, Yinhe Han, Lili Song, Zhenyu Quan, Jiajun Li, Xiaowei Li:
CNN-based object detection solutions for embedded heterogeneous multicore SoCs. ASP-DAC 2017: 105-110 - [c62]Xin He, Guihai Yan, Faqiang Sun, Yinhe Han, Xiaowei Li:
ApproxEye: Enabling approximate computation reuse for microrobotic computer vision. ASP-DAC 2017: 402-407 - [c61]Shiqi Lian, Ying Wang, Yinhe Han, Xiaowei Li:
BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems. ASP-DAC 2017: 738-743 - [c60]Shiqi Lian, Yinhe Han, Ying Wang, Yungang Bao, Hang Xiao, Xiaowei Li, Ninghui Sun:
Dadu: Accelerating Inverse Kinematics for High-DOF Robots. DAC 2017: 59:1-59:6 - [c59]Wenyan Lu, Guihai Yan, Jiajun Li, Shijun Gong, Yinhe Han, Xiaowei Li:
FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks. HPCA 2017: 553-564 - 2016
- [c58]Xin He, Guihai Yan, Yinhe Han, Xiaowei Li:
ACR: Enabling computation reuse for approximate computing. ASP-DAC 2016: 643-648 - [c57]Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li:
DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. DAC 2016: 37:1-37:6 - [c56]Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li:
DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. DAC 2016: 110:1-110:6 - [c55]Lili Song, Ying Wang, Yinhe Han, Xin Zhao, Bosheng Liu, Xiaowei Li:
C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization. DAC 2016: 123:1-123:6 - [c54]Faqiang Sun, Huawei Li, Yinhe Han, Guihai Yan, Jun Ma:
PowerCap: Leverage Performance-Equivalent Resource Configurations for power capping. IGSC 2016: 1-8 - 2015
- [c53]Hang Lu, Guihai Yan, Yinhe Han, Ying Wang, Xiaowei Li:
ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation. ASP-DAC 2015: 142-147 - [c52]Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li:
RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory. DAC 2015: 19:1-19:6 - [c51]Ying Wang, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li:
ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. DAC 2015: 47:1-47:6 - [c50]Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li:
A case of precision-tunable STT-RAM memory design for approximate neural network. ISCAS 2015: 1534-1537 - [c49]Song Jin, Songwei Pei, Yinhe Han, Huawei Li:
On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island. VLSI-DAT 2015: 1-4 - 2014
- [c48]Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li:
Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores. ASP-DAC 2014: 394-399 - [c47]Song Jin, Yinhe Han, Songwei Pei:
Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraints. ASP-DAC 2014: 720-725 - [c46]Ying Wang, Yinhe Han, Huawei Li:
A low power DRAM refresh control scheme for 3D memory cube. COOL Chips 2014: 1-3 - [c45]Xin He, Guihai Yan, Yinhe Han, Xiaowei Li:
SuperRange: Wide operational range power delivery design for both STV and NTV computing. DATE 2014: 1-6 - [c44]Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li:
Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube. ICCAD 2014: 295-300 - 2013
- [c43]Hang Lu, Guihai Yan, Yinhe Han, Binzhang Fu, Xiaowei Li:
RISO: relaxed network-on-chip isolation for cloud processors. DAC 2013: 38:1-38:6 - [c42]Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li:
SmartCap: user experience-oriented power adaptation for smartphone's application processor. DATE 2013: 57-60 - [c41]Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li:
Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction. ISCAS 2013: 337-340 - [c40]Yinhe Han, Song Jin, Jibing Qiu, Qiang Xu, Xiaowei Li:
On predicting NBTI-induced circuit aging by isolating leakage change. ISQED 2013: 46-52 - 2012
- [c39]Jianliang Gao, Jianxin Wang, Yinhe Han, Lei Zhang, Xiaowei Li:
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems. DATE 2012: 27-32 - [c38]Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao Liang:
AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture. HPCA 2012: 287-298 - 2011
- [c37]Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li:
Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip. ASP-DAC 2011: 357-362 - [c36]Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li:
A resilient on-chip router design through data path salvaging. ASP-DAC 2011: 437-442 - [c35]Yuanqing Cheng, Lei Zhang, Yinhe Han, Jun Liu, Xiaowei Li:
Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC. Asian Test Symposium 2011: 181-186 - [c34]Jianbo Dong, Lei Zhang, Yinhe Han, Ying Wang, Xiaowei Li:
Wear rate leveling: lifetime enhancement of PRAM with endurance variation. DAC 2011: 972-977 - [c33]Jianliang Gao, Yinhe Han, Xiaowei Li:
Eliminating data invalidation in debugging multiple-clock chips. DATE 2011: 691-696 - [c32]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li:
Flex memory: Exploiting and managing abundant off-chip optical bandwidth. DATE 2011: 968-973 - [c31]Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li:
An abacus turn model for time/space-efficient reconfigurable routing. ISCA 2011: 259-270 - 2010
- [c30]Song Jin, Yinhe Han, Huawei Li, Xiaowei Li:
P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework. Asian Test Symposium 2010: 117-120 - [c29]Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li:
Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. DATE 2010: 933-936 - [c28]Lei Zhang, Yue Yu, Jianbo Dong, Yinhe Han, Shangping Ren, Xiaowei Li:
Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors. DATE 2010: 1566-1571 - [c27]Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li:
Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. ISCA 2010: 485-496 - [c26]Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li:
nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. ITC 2010: 343-352 - [c25]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li:
Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. PRDC 2010: 70-76 - 2009
- [c24]Zichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu:
A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. Asian Test Symposium 2009: 219-224 - [c23]Jun Liu, Yinhe Han, Xiaowei Li:
Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power. Asian Test Symposium 2009: 319-324 - [c22]Song Jin, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, Guihai Yan:
M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. Asian Test Symposium 2009: 437-442 - [c21]Guihai Yan, Yinhe Han, Xiaowei Li:
A unified online Fault Detection scheme via checking of Stability Violation. DATE 2009: 496-501 - [c20]Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li:
MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency. ISLPED 2009: 395-400 - [c19]Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan, Xiaowei Li:
Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy. PRDC 2009: 17-22 - [c18]Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li:
A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. PRDC 2009: 276-281 - [c17]Jianliang Gao, Yinhe Han, Xiaowei Li:
A New Post-Silicon Debug Approach Based on Suspect Window. VTS 2009: 85-90 - 2008
- [c16]Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li:
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. DATE 2008: 891-896 - 2007
- [c15]Shaohua Lei, Yinhe Han, Xiaowei Li:
Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic. ATS 2007: 323-328 - 2006
- [c14]Yu Hu, Cheng Li, Jia Li, Yinhe Han, Xiaowei Li, Wei Wang, Hua-Wei Li, Laung-Terng Wang, Xiaoqing Wen:
Test data compression based on clustered random access scan. ATS 2006: 231-236 - [c13]Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han:
Fast Packet Classification using Group Bit Vector. GLOBECOM 2006 - [c12]Jie Don, Yu Hu, Yinhe Han, Xiaowei Li:
An on-chip combinational decompressor for reducing test data volume. ISCAS 2006 - 2005
- [c11]Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li:
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. ASP-DAC 2005: 53-58 - [c10]Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra:
Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. Asian Test Symposium 2005: 372-377 - [c9]Yanzhuo Tan, Yinhe Han, Xiaowei Li, Feiyin Lu, Yuchuan Chen:
Validation analysis and test flow optimization of VLSI chip. ISCAS (6) 2005: 5666-5669 - [c8]Ji Li, Yinhe Han, Xiaowei Li:
Deterministic and low power BIST based on scan slice overlapping. ISCAS (6) 2005: 5670-5673 - [c7]Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li:
Using MUXs Network to Hide Bunches of Scan Chains. ISQED 2005: 238-243 - [c6]Xiaotao Chang, Dongrui Fan, Yinhe Han, Zhimin Zhang:
SoC Leakage Power Reduction Algorithm by Input Vector Control. SoC 2005: 86-89 - 2004
- [c5]Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra:
Rapid and Energy-Efficient Testing for Embedded Cores. Asian Test Symposium 2004: 8-13 - [c4]Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li:
Pair Balance-Based Test Scheduling for SOCs. Asian Test Symposium 2004: 236-241 - [c3]Yinhe Han, Xiaowei Li:
Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test. ESA/VLSI 2004: 374-381 - [c2]Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra:
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. DFT 2004: 298-305 - 2003
- [c1]Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra:
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. Asian Test Symposium 2003: 440-445
Informal and Other Publications
- 2024
- [i10]Xinyu Wang, Xiaotian Sun, Yinhe Han, Xiaoming Chen:
PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators. CoRR abs/2402.18089 (2024) - [i9]Wanqian Li, Xiaotian Sun, Xinyu Wang, Lei Wang, Yinhe Han, Xiaoming Chen:
PIMSYN: Synthesizing Processing-in-memory CNN Accelerators. CoRR abs/2402.18114 (2024) - [i8]Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li:
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. CoRR abs/2403.11202 (2024) - 2023
- [i7]Hanqi Jiang, Cheng Zeng, Runnan Chen, Shuai Liang, Yinhe Han, Yichao Gao, Conglin Wang:
Depth-NeuS: Neural Implicit Surfaces Learning for Multi-view Reconstruction Based on Depth Information Optimization. CoRR abs/2303.17088 (2023) - [i6]Kaiyan Chang, Ying Wang, Haimeng Ren, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li:
ChipGPT: How far are we from natural language hardware design. CoRR abs/2305.14019 (2023) - [i5]Xiaotian Sun, Xinyu Wang, Wanqian Li, Lei Wang, Yinhe Han, Xiaoming Chen:
PIMCOMP: A Universal Compilation Framework for Crossbar-based PIM DNN Accelerators. CoRR abs/2307.01475 (2023) - [i4]Yuxin Yang, Xiaoming Chen, Yinhe Han:
RBDCore: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines. CoRR abs/2307.02274 (2023) - 2022
- [i3]Weidong Cao, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, Li Jiang:
Neural-PIM: Efficient Processing-In-Memory with Neural Approximation of Peripherals. CoRR abs/2201.12861 (2022) - 2020
- [i2]Beibei Jin, Yu Hu, Qiankun Tang, Jingyu Niu, Zhiping Shi, Yinhe Han, Xiaowei Li:
Exploring Spatial-Temporal Multi-Frequency Analysis for High-Fidelity and Temporal-Consistency Video Prediction. CoRR abs/2002.09905 (2020) - 2019
- [i1]Xiaoming Chen, Yinhe Han, Yu Wang:
Communication Lower Bound in Convolution Accelerators. CoRR abs/1911.05662 (2019)
Coauthor Index
[j79] [j78] [j76] [j74] [j73] [j70] [j65] [j63] [j62] [j60] [j53] [j52] [j51] [j50] [j49] [j48] [c127] [c123] [c122] [c121] [c119] [c118] [c114] [c113] [c110] [c109] [c108] [c107] [c106] [c105] [c104] [c103] [c102] [c101] [c94] [c93] [c92] [c91] [c89] [c88] [c86] [c82] [c81] [c80] [c79] [c78] [c76] [c74] [c72] [c70] [c66] [i10] [i9] [i5] [i4] [i1]
[j54] [j47] [j44] [j43] [j40] [j36] [j33] [j32] [j30] [j29] [j26] [j24] [j23] [j19] [j17] [j16] [j9] [j6] [j5] [j4] [j3] [j2] [j1] [c120] [c100] [c83] [c69] [c68] [c65] [c57] [c56] [c54] [c52] [c51] [c50] [c49] [c46] [c44] [c41] [c32] [c31] [c30] [c29] [c26] [c25] [c24] [c22] [c18] [c13] [c11] [c7] [c5] [c4] [c2] [c1] [i6]
[j77] [j68] [j54] [j52] [j51] [j50] [j45] [j44] [j43] [j42] [j41] [j40] [j39] [j37] [j35] [j34] [j33] [j32] [j31] [j30] [j29] [j28] [j25] [j24] [j23] [j22] [j21] [j20] [j19] [j17] [j16] [j15] [j14] [j13] [j12] [j11] [j10] [j9] [j8] [j7] [j6] [j5] [j4] [j3] [j2] [j1] [c100] [c99] [c98] [c97] [c95] [c90] [c86] [c85] [c83] [c77] [c76] [c75] [c74] [c69] [c68] [c67] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c53] [c52] [c51] [c50] [c48] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c5] [c4] [c3] [c2] [c1] [i6] [i2]
[j77] [j75] [j72] [j71] [j69] [j64] [j59] [j52] [j50] [j46] [j44] [j43] [j40] [j34] [j33] [j32] [j31] [j30] [j29] [j28] [j26] [c126] [c120] [c117] [c116] [c115] [c112] [c111] [c100] [c96] [c86] [c83] [c76] [c75] [c74] [c71] [c67] [c66] [c65] [c63] [c61] [c60] [c57] [c56] [c55] [c53] [c52] [c51] [c50] [c46] [c44] [c41] [c34] [c32] [c25] [i8] [i6]
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