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"A signal degradation reduction method for memristor ratioed logic (MRL) gates."

Bosheng Liu et al. (2015)

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DOI: 10.1587/ELEX.12.20150062

access: open

type: Journal Article

metadata version: 2023-05-23

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  - journals/ieiceee/LiuWYHL15
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  - https://dblp.org/rec/journals/ieiceee/LiuWYHL15
Bosheng Liu, Ying Wang, Zhiqiang You, Yinhe Han, Xiaowei Li:
A signal degradation reduction method for memristor ratioed logic (MRL) gates. IEICE Electron. Express 12(8): 20150062 (2015)

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