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"TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design."

Yuanqing Cheng et al. (2013)

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DOI: 10.1007/S11390-013-1316-6

access: closed

type: Journal Article

metadata version: 2023-05-23

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  dblp key:
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  - https://dblp.org/rec/journals/jcst/ChengZHL13
Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li:
TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design. J. Comput. Sci. Technol. 28(1): 119-128 (2013)

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