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ORCIDTao Lv 0001
Person information
- affiliation: Chinese Academy of Sciences, State Key Laboratory of Computer Architecture, Beijing, China
Other persons with the same name
- Tao Lv — disambiguation page
- Tao Lyu 0002
![[0000-0001-5162-8103]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-5162-8103")
(aka: Tao Lv 0002) — Nottingham Trent University, School of Animal Rural & Environmental Sciences, UK (and 2 more) - Tao Lv 0003 — Beijing University of Posts and Telecommunications, School of Software Engineering, China
- Tao Lv 0004 — Harbin Institute of Technology, Shenzhen Graduate School, China
- Tao Lv 0005 — Tongji University, College of Electronics and Information Engineering, Shanghai, China
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2010 – 2019
- 2016
[j5]Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, Sandip Kundu:
Abstraction-Guided Simulation Using Markov Analysis for Functional Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2): 285-297 (2016)- [j4]Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li:
Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(6): 999-1011 (2016) - 2014
- [c12]Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li:
Functional test generation guided by steady-state probabilities of abstract design. DATE 2014: 1-4 - 2013
- [j3]Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
Test Path Selection for Capturing Delay Failures Under Statistical Timing Model. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1210-1219 (2013) - [c11]Yanhong Zhou, Tiancheng Wang, Tao Lv, Huawei Li, Xiaowei Li:
Path Constraint Solving Based Test Generation for Hard-to-Reach States. Asian Test Symposium 2013: 239-244 - 2010
- [c10]Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
Graph partition based path selection for testing of small delay defects. ASP-DAC 2010: 499-504 - [c9]Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
An Efficient Algorithm for Finding a Universal Set of Testable Long Paths. Asian Test Symposium 2010: 319-324 - [c8]Tao Zhang, Tao Lv, Xiaowei Li:
An abstraction-guided simulation approach using Markov models for microprocessor verification. DATE 2010: 484-489 - [c7]Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
On generation of a universal path candidate set containing testable long paths. ITC 2010: 816 - [c6]Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
Fast path selection for testing of small delay defects considering path correlations. VTS 2010: 3-8
2000 – 2009
- 2009
- [c5]Tao Lv, Huawei Li, Xiaowei Li:
Automatic Selection of Internal Observation Signals for Design Verification. VTS 2009: 203-208 - 2007
- [c4]Tao Lv, Tong Xu, Yang Zhao, Huawei Li, Xiaowei Li:
Bug analysis and corresponding error models in real designs. HLDVT 2007: 59-64 - 2006
- [j2]Tao Lv, Jianping Fan, Xiaowei Li, Ling-Yi Liu:
Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification. J. Electron. Test. 22(3): 273-285 (2006) - [c3]Tao Lv, Ling-Yi Liu, Yang Zhao, Huawei Li, Xiaowei Li:
An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains. ATS 2006: 89-94 - 2005
- [j1]Wei Lu, Xiu-Tao Yang, Tao Lv, Xiaowei Li:
An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement Coverage. J. Comput. Sci. Technol. 20(6): 875-884 (2005) - 2004
- [c2]Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li:
Pair Balance-Based Test Scheduling for SOCs. Asian Test Symposium 2004: 236-241 - 2003
- [c1]Tao Lv, Jianping Fan, Xiaowei Li:
An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains. Asian Test Symposium 2003: 161-167
Coauthor Index
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