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ORCIDIntegration, Volume 70
Volume 70, January 2020
- Maxim Shepovalov, Venkatesh Akella:
FPGA and GPU-based acceleration of ML workloads on Amazon cloud - A case study using gradient boosted decision tree library. 1-9
- Milan Copic, Rainer Leupers, Gerd Ascheid:
Reducing idle time in event-triggered software execution via runnable migration and DPM-Aware scheduling. 10-20 - Lei Xie, Hao Cai, Chao Wang, Jun Yang:
Towards an automated design flow for memristor based VLSI circuits. 21-31 - Xingquan Li
, Bei Yu, Jianli Chen, Wenxing Zhu:
DSA guiding template assignment with multiple redundant via and dummy via insertion. 32-42 - Toshinari Itoko, Rudy Raymond, Takashi Imamichi, Atsushi Matsuo:
Optimization of quantum circuit mapping using gate transformation and commutation. 43-50 - Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi:
A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. 51-59
- Yanbin Li, Ming Tang, Yuguang Li, Huanguo Zhang:
A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs. 60-69 - Qi Xu, Song Chen, Hao Geng, Bo Yuan, Bei Yu, Feng Wu, Zhengfeng Huang:
Fault tolerance in memristive crossbar-based neuromorphic computing systems. 70-79 - Mohammad Moradinezhad Maryan, Reza Rezaei Siahrood, Seyed Javad Azhari, Abdolreza Rahmati:
A high-precision current-mode multifunction analog cell suitable for computational signal processing. 80-89 - Shaoyi Peng, Ertugrul Demircan, Mehul D. Shroff, Sheldon X.-D. Tan:
Full-chip wire-oriented back-end-of-line TDDB hotspot detection and lifetime analysis. 90-98 - Mohammadreza Esmali Nojehdeh, Mustafa Altun:
Systematic synthesis of approximate adders and multipliers with accurate error calculations. 99-107 - Zheng Shiji, Guoquan Wu:
A folded-cascode mixer for mixing-spur suppressions in a 2.4-to-5.8 GHz transmitter. 108-115 - Mohammad Khaleqi Qaleh Jooq, Ali Mir, Sattar Mirzakuchaki, Ali Farmani:
Design and performance analysis of wrap-gate CNTFET-based ring oscillators for IoT applications. 116-125 - Arindrajit Ghosh, Uddalak Bhattacharya, Manish Kumar, Swapna Banerjee:
Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology. 126-137 - Sauvagya Ranjan Sahoo, Kamalakanta Mahapatra:
A novel area efficient on-chip RO-Sensor for recycled IC detection. 138-150 - Chaoping Zhang, Robert Gallichan, David M. Budgett, Daniel McCormick:
A precision low-power analog front end in 180 nm CMOS for wireless implantable capacitive pressure sensors. 151-158 - Roberto Giorgio Rizzo, Andrea Calimera, Jun Zhou:
Corrigendum to"Approximate error detection-correction for efficient adaptive voltage Over-Scaling"[Integration 63 (2018) 220-231]. 159
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