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ORCIDSAMOS 2017: Pythagorion, Greece
- Yale N. Patt, S. K. Nandy:
2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2017, Pythagorion, Greece, July 17-20, 2017. IEEE 2017, ISBN 978-1-5386-3437-0
Session 1: Architectures and Accelerators
- Anoop Bhagyanath, Klaus Schneider
:
Exploring different execution paradigms in exposed datapath architectures with buffered processing units. 1-10 - Charalampos Vatsolakis, Dionisios N. Pnevmatikatos:
RACOS: Transparent access and virtualization of reconfigurable hardware accelerators. 11-19 - Tobias Lieske, Benjamin Pfundt, Steffen Vaas, Marc Reichenbach, Dietmar Fey:
System on chip generation for multi-sensor and sensor fusion applications. 20-29 - Habib ul Hasan Khan, Jens Rettkowski, Mohamed Eldafrawy, Diana Göhringer:
An event-based Network-on-Chip debugging system for FPGA-based MPSoCs. 30-37
Session 2: Modelling and Simulation
- Jun Xiao, Andy D. Pimentel, Giuseppe Lipari:
SysRT: A modular multiprocessor RTOS simulator for early design space exploration. 38-45 - Zhuoran Zhao, Vasileios Tsoutsouras, Dimitrios Soudris, Andreas Gerstlauer:
Network/system co-simulation for design space exploration of IoT applications. 46-53 - Geraldo F. Oliveira, Paulo C. Santos, Marco A. Z. Alves, Luigi Carro:
A generic processing in memory cycle accurate simulator under hybrid memory cube architecture. 54-61 - Christian Menard, Jerónimo Castrillón, Matthias Jung, Norbert Wehn:
System simulation with gem5 and SystemC: The keystone for full interoperability. 62-69
Session 3: ASIPs and Hardware Accelerators
- Christoforos Kachris, Elias Koromilas, Ioannis Stamelos, Dimitrios Soudris:
SPynq: Acceleration of machine learning applications over Spark on Pynq. 70-77 - Julian Hartig, Guillermo Payá Vayá, Nico Mentzer, Holger Blume:
Balanced application-specific processor system for efficient SIFT-feature detection. 78-87 - Lukas Gerlach, Guillermo Payá Vayá, Shuang Liu, Moritz Weißbrich, Holger Blume, Daniel Marquardt, Simon Doclo:
Analyzing the trade-off between power consumption and beamforming algorithm performance using a hearing aid ASIP. 88-96
Session 4: Neural Networks
- Syed M. A. H. Jafri, Ahmed Hemani, Dimitrios Stathis:
Can a reconfigurable architecture beat ASIC as a CNN accelerator? 97-104 - Kuo-You Peng, Sheng-Yu Fu, Yu-Ping Liu, Wei-Chung Hsu:
Adaptive runtime exploiting sparsity in tensor of deep learning neural network on heterogeneous systems. 105-112 - Johan Mes, Ester Stienstra, Xuefei You, Sumeet S. Kumar, Amir Zjajo, Carlo Galuzzi, Rene van Leuken:
Neuromorphic self-organizing map design for classification of bioelectric-timescale signals. 113-120
Session 5: Application Analysis and Optimization
- Alexander Stegmeier, Sebastian Kehr, Dave George, Christian Bradatsch, Milos Panic, Bert Bodekker, Theo Ungerer:
Evaluation of fine-grained parallelism in AUTOSAR applications. 121-128 - Dimitris Theodoropoulos, Nikolaos Alachiotis, Dionisios N. Pnevmatikatos:
FPGA-based evaluation platform for disaggregated computing. 129-136 - Yang Ma, Prajith Ramakrishnan Geethakumari, Georgios Smaragdos, Sander Lindeman, Vincenzo Romano, Mario Negrello, Ioannis Sourdis, Laurens W. J. Bosman, Chris I. De Zeeuw, Zaid Al-Ars, Christos Strydis:
Towards real-time whisker tracking in rodents for studying sensorimotor disorders. 137-145 - Harry Sidiropoulos, Ioannis Koutras, Dimitrios Soudris, Kostas Siozios:
Algorithmic and memory optimizations on multiple application mapping onto FPGAs. 146-153
Session 6: Compiler Optimizations
- Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Extraction of recursion level parallelism for embedded multicore systems. 154-162 - A. P. Arif Ali, Erven Rohou:
Dynamic function specialization. 163-170 - Heikki O. Kultala, Pekka Jääskeläinen, Johannes IJzerman, Lasse Lehtonen, Timo Viitanen, Markku J. Mäkitalo, Jarmo H. Takala:
Exposed datapath optimizations for loop scheduling. 171-178 - Florian Giesemann, Guillermo Payá Vayá, Lukas Gerlach, Holger Blume, Fabian Pflug, Gabriele von Voigt:
Using a genetic algorithm approach to reduce register file pressure during instruction scheduling. 179-187
Session 7: Application Mapping and Scheduling
- Sima Sinaei, Omid Fatemi, Andy D. Pimentel:
Run-time mapping algorithm for dynamic workloads using process merging transformations. 188-195 - Gereon Onnebrink, Florian Walbroel, Jonathan Klimt, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo, Stefan Schürmans, Xiaotao Chen, YwhPyng Harn:
DVFS-enabled power-performance trade-off in MPSoC SW application mapping. 196-202 - Sobhan Niknam, Todor P. Stefanov:
Energy-efficient scheduling of throughput-constrained streaming applications by periodic mode switching. 203-212 - Hamza Deroui, Karol Desnos, Jean-François Nezan, Alix Munier Kordon:
Relaxed subgraph execution model for the throughput evaluation of IBSDF graphs. 213-220
Special Session on: Virtual Prototyping of Parallel and Embedded Systems (VIPES)
- Matthias Jung, Kira Kraft, Norbert Wehn:
A new state model for DRAMs using Petri Nets. 221-226 - Yuranan Kitrungrotsakul, Kiyofumi Tanaka, Masanobu Hashimoto, Shuichi Onishi:
Virtual environment for developing real-time image processing for vehicle control. 227-232 - Jasmin Jahic, Thomas Kuhn, Matthias Jung, Norbert Wehn:
Supervised testing of concurrent software in embedded systems. 233-238 - Andreas Emeretlis, T. Tsakoulis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros:
Task graph mapping and scheduling on heterogeneous architectures under communication constraints. 239-244
Special Session on: Architectures and design tools for secure embedded systems
- Francesco Regazzoni:
Special session on architectures and design tools for secure embedded systems. 245 - Christos Andrikos, Giorgos Rassias, Liran Lerman, Kostas Papagiannopoulos, Lejla Batina:
Location-based leakages: New directions in modeling and exploiting. 246-252 - Suman Sau, Jawad Haj-Yahya, Ming Ming Wong, Kwok-Yan Lam, Anupam Chattopadhyay:
Survey of secure processors. 253-260 - Pedro Miguens Matutino, Juvenal Araujo, Leonel Sousa, Ricardo Chaves:
Pipelined FPGA coprocessor for elliptic curve cryptography based on residue number system. 261-268 - Nele Mentens:
Hiding side-channel leakage through hardware randomization: A comprehensive overview. 269-272 - Felipe Valencia, Ayesha Khalid, Elizabeth O'Sullivan, Francesco Regazzoni:
The design space of the number theoretic transform: A survey. 273-277
Special Session on: Energy-efficient and accelerated servers
- Ioannis Stamoulias, Christoforos Kachris, Dimitrios Soudris:
Hardware accelerators for financial applications in HDL and High Level Synthesis. 278-285 - Arman Iranfar, Federico Terraneo, William Andrew Simon, Leon Dragic, Igor Piljic, Marina Zapater, William Fornaciari, Mario Kovac, David Atienza:
Thermal characterization of next-generation workloads on heterogeneous MPSoCs. 286-291 - Konstantinos Tovletoglou, Dimitrios S. Nikolopoulos, Georgios Karakonstantis:
Access-aware DRAM failure-rate estimation under relaxed refresh operations. 292-299 - Dimitris Syrivelis, Andrea Reale, Kostas Katrinis, Ilias Syrigos, Maciej Bielski, Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos, Georgios Zervas:
A software-defined architecture and prototype for disaggregated memory rack scale systems. 300-307 - Cristina Silvano, Giovanni Agosta, Jorge G. Barbosa, Andrea Bartolini, Andrea Rosario Beccari, Luca Benini, João Bispo, João M. P. Cardoso, Carlo Cavazzoni, Stefano Cherubin, Radim Cmar, Davide Gadioli, Candida Manelfi, Jan Martinovic, Ricardo Nobre, Gianluca Palermo, Martin Palkovic, Pedro Pinto, Erven Rohou, Nico Sanna, Katerina Slaninová:
The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems. 308-316
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