default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID9th VLSI Design 1996: Bangalore, India
- 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India. IEEE Computer Society 1996, ISBN 0-8186-7228-5
Tutorial Pages
- Kaushik Roy, R. K. Roy:
Low Power Design. 2 - Kurt Keutzer, Sharad Malik
:
Register Transfer Level Synthesis: From Theory to Practice. 2 - Bapiraju Vinnakota, Ramesh Harjani:
Mixed-Signal Design for Test. 2 - A. Ratan Gupta, V. Visvanathan:
VLSI Implementation of DSP Architectures. 3 - Rajesh Gupta:
Hardware Software Co-Design of Embedded Systems. 3 - Jacob A. Abraham, Gopi Ganapathy:
Practical Test and DFT for Next Generation VLSI. 3
'95 Keynote Address
- Vishwani D. Agrawal:
Science, Technology, and the Indian Society. 6-9
'96 Keynote Address
- Thomas J. Engibou:
The New Electronics Industry. 10
Session 1: Plenary Session: Invited Address
- Robert W. Brodersen, Rajeev Jain:
VLSI in Mobile Communication. 11-13
Session 2: VLSI for Mobile Communication I
- Mani B. Srivastava:
Medium access control and air-interface subsystem for an indoor wireless ATM network. 14-18 - A. Sriram, Fadi J. Kurdahi:
Behavioral Modeling of an ATM Switch using SpecCharts. 19-22 - Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen:
A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. 23-28 - Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Design tradeoffs in high speed multipliers and FIR filters. 29-32
Session 3: Placement and Routing
- Jin-Tai Yan:
A simple yet effective genetic approach for the orientation assignment on cell-based layout. 33-36 - John A. Chandy, Prithviraj Banerjee:
Parallel simulated annealing strategies for VLSI cell placement. 37-42 - Sandip Das, Bhargab B. Bhattacharya:
Channel routing in Manhattan-diagonal model. 43-48 - Si-Qing Zheng, Joon Shik Lim, S. Sitharama Iyengar:
Routing using implicit connection graphs [VLSI design. 49-52
Session 4: Built-In Self-Test and Diagnosis
- Tapan J. Chakraborty, Vishwani D. Agrawal:
Design for high-speed testability of stuck-at faults. 53-56 - Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
A Novel BIST Architecture With Built-in Self Check. 57-60 - Sukumar Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri:
Programmable cellular automata based testbed for fault diagnosis in VLSI circuits. 61-64 - Koppolu Sasidhar, Abhijit Chatterjee:
Hierarchical Probablistic Diagnosis of MCMs on Large-Area Substrates. 65-68
Session 5: Hardware/Software Co-Design
- D. V. Poornaiah, P. V. Ananda Mohan:
A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. 69-72 - J. Shu, Thomas Charles Wilson, Dilip K. Banerji:
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation. 73-76 - Rainer Leupers, Peter Marwedel:
Instruction-Set Modeling for ASIP Code Generation. 77-80 - Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig:
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. 81-84
Session 6: Analog Circuits
- A. B. Bhattacharyya, Ram Singh Rana, S. K. Guha, Rajendar Bahl, Sneh Anand, M. J. Zarabi, P. A. Govindacharyulu, Vivek Gupta, Vivek Mohan, Jatin Roy, Amul Atri:
A micropower analog hearing aid on low voltage CMOS digital process. 85-89 - C. Srinivasan, K. Radhakrishna Rao:
A 20MHz CMOS Variable Gain Amplifier. 90-93 - Andrea Boni, Carlo Morandi:
Low-Power, Low-Voltage BiCMOS Comparators for Approximately 200MHz, 8bit Operation. 94-98 - J. Weiss, B. Majoux, Gérard Bouvier:
A Very High Gain Bandwidth Product Fully Differential Amplifier. 99-102
Session 7: Automatic Test Pattern Generation
- Paul J. Thadikaran, Sreejit Chakravarty:
Fast Algorithms for Computer IDDQ Tests for Combination Circuits. 103-106 - Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
On More Efficient Combinational ATPG Using Functional Learning. 107-110 - Arun Balakrishnan, Srimat T. Chakradhar:
Sequential Circuits with combinational Test Generation Complexity. 111-117 - C. P. Ravikumar, Rajamani Rajarajan:
Genetic Algorithms for Scan Path Design. 118-121
Session 8: High-Level Synthesis I
- Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose:
Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach. 122-125 - Srinivas Katkoori, Ranga Vemuri, Jay Roy:
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis. 126-132 - Johnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani:
A Rule-Based Approach for Improving Allocation of Filter Structures in HLS. 133-139 - Santonu Sarkar, Anupam Basu, Arun K. Majumdar:
Representation and Synthesis of Interface of a Circuit for its Reuse. 140-145
Session 9: High-Performance Circuits
- Natesan Venkateswaran, Dinesh Bhatia:
Clock-Skew Constrained Cell Placement. 146-149 - Rohini Gupta, Byron Krauter, Lawrence T. Pileggi:
On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects. 150-155 - R. P. Suresh, P. Venugopal, S. Tamizh Selvam, S. Potla:
Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET. 156-161 - Yinghua Min, Zhuxing Zhao, Zhongcheng Li:
An Analytical Delay Model Based on Boolean Process. 162-165
Session 10: Sequential Automatic Test Pattern Generation
- Timothy John Lambert, Kewal K. Saluja:
Methods for Dynamic Test Vector compaction in Sequential Test Generation. 166-169 - Anand Raghunathan, Srimat T. Chakradhar:
Dynamic test Sequence compaction for Sequential Circuits. 170-173 - Dhruva R. Chakrabarti, Ajai Jain:
An Efficient Test Generation Technique for Sequential Circuits with Repetitive Sub-Circuits. 174-177 - Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy:
Synchronous Test Generation Model for Asynchronous Circuits. 178-185
Session 12: High-Level Synthesis II
- Krzysztof Bilinski, Erik L. Dagless, Jonathan M. Saul:
Behavioral Synthesis of Complex Parallel Controllers. 186-191 - Raghava V. Cherabuddi, Jijun Chen, Magdy A. Bayoumi:
A Graph-Based Approach to the Synthesis of Multi-Chip Module Architectures. 192-197 - Naren Narasimhan, Ranga Vemuri, Jay Roy:
Synchronous Controller Models for Synthesis from Communicating VHDL Processes. 198-204 - C. P. Ravikumar, Vikram Saxena:
Synthesis of Testable Pipelined Datapaths Using Genetic Search. 205-210
Session 13: Field-Programmable Gate Arrays
- Ashutosh Singla, Thomas M. Conte:
Bipartitioning for Hybrid FPGA-Software Simulatio. 211-214 - Takayuki Suyama, Hiroshi Sawada, Akira Nagoya:
LUT-based FPGA Technology Mapping using Permissible Functions. 215-218 - Lizy Kurian John:
VaWiRAM: a variable width random access memory module. 219-224 - Fran Hanchek, Shantanu Dutt:
Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs. 225-229
Session 14: Mixed-Signal Design and Test
- Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi:
Low-cost DC built-in self-test of linear analog circuits using checksums. 230-233 - Pradip Mandal, V. Visvanathan:
Design of high performance two stage CMOS cascode op-amps with stable biasing. 234-237 - Abu Khari bin A'Ain, A. H. Bratt, A. P. Dorey:
Testing Analogue Circuits by A C Power Supply Voltage. 238-241 - Rajesh Ramadoss, Michael L. Bushnell:
Test generation for mixed-signal devices using signal flow graphs. 242-248
Session 15: Logic Design and Synthesis
- Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A study of composition schemes for mixed apply/compose based construction of ROBDDs. 249-253 - Irith Pomeranz, Sudhakar M. Reddy:
On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits. 254-259 - Debesh Kumar Das, Bhargab B. Bhattacharya:
Does retiming affect redundancy in sequential circuits? 260-263 - Nripendra N. Biswas, C. Srikanth, James Jacob:
Cubical CAMP for minimization of Boolean functions. 264-269
Session 16: Architecture
- Subarna Bhattacharjee, J. Bhattacharya, U. Raghavendra, Debashis Saha, Parimal Pal Chaudhuri:
A VLSI architecture for cellular automata based parallel data compression. 270-275 - M. P. Sebastian, P. S. Nagendra Rao, Lawrence Jenkins:
VLSI/WSI Designs for Folded Cube-Connected Cycles Architectures. 276-279 - Vamsi Krishna, Abdel Ejnioui, N. Ranganathan:
A tree matching chip. 280-285 - S. Ramanathan, V. Visvanathan:
A systolic architecture for LMS adaptive filtering with minimal adaptation delay. 286-289
Session 17: Logic and Fault Simulation
- Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas:
Statistical path delay fault coverage estimation for synchronous sequential circuits. 290-295 - Arun Balakrishnan, Srimat T. Chakradhar:
Retiming with logic duplication transformation: theory and an application to partial scan. 296-302 - Peter M. Maurer:
Is Compiled Simulation Really Faster than Interpreted Simulation? 303-306 - S. Sundaram, Lalit M. Patnaik:
Distributed logic simulation: time-first evaluation vs. event driven algorithms. 307-310
Session 18: VLSI in Communications and Applications
- S. Samel, Bert Gyselinckx, Ivo Bolsens, Hugo De Man:
Designing Systems On Silicon: A Digital Spread Spectrum Pager. 311-312 - Shriram Kulkarni, Pinaki Mazumder, George I. Haddad:
A high-speed 32-bit parallel correlator for spread spectrum communication. 313-315 - S. Mitra, S. Das, Parimal Pal Chaudhuri, Sukumar Nandi:
Architecture of a VLSI Chip for Modeling Amino Acid Sequence in Proteins. 316-317 - Ranjeet Ranade, Sanjay Bhandari, A. N. Chandorkar:
VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder. 318-319 - Santanu Chattopadhyay, S. Mitra, Parimal Pal Chaudhuri:
Cellular automata based architecture of a database query processor. 320-321 - Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar:
A multiplier generator for Xilinx FPGAs. 322-323
Session 19: Low-Power and Analog Design
- C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora:
Estimation of Power from Module-level Netlists. 324-325 - Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee:
Instruction Level Power Analysis and Optimization of Software. 326-328 - Suresh Rajgopal:
Challenges in Low Power Microprocessor Design. 329-330 - Sudhir Aggarwal:
An Enhanced Macromodel for a CMOS Operational Amplifier for HDL Implementation. 331-332 - S. K. Gupta, M. M. Hasan:
KANSYS: a CAD tool for analog circuit synthesis. 333-334
Session 20: Test and Logic Synthesis
- G. Enrique Fernandez, R. Sridhar:
Dual rail static CMOS architecture for wave pipelining. 335-336 - Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak:
Syndrome signature in output compaction for VLSI BIST. 337-338 - Arunita Jaekel, Graham A. Jullien, Subir Bandyopadhyay:
Multilevel Factorization Technique for Pass Transistor Logic. 339-340 - Vishwani D. Agrawal, David Lee:
Characteristic polynomial method for verification and test of combinational circuits. 341-342 - Narayanan Vijaykrishnan, N. Ranganathan:
SUBGEN: a genetic approach for subcircuit extraction. 343-345
Session 21: Low-Power Design
- Jatan C. Shah, Sachin S. Sapatnekar:
Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs. 346-351 - Anantha P. Chandrakasan:
Ultra low power digital signal processing. 352-357 - Navin Chaddha, Mohan Vishwanath:
A low power video encoder with power, memory and bandwidth scalability. 358-363 - Chuan-Yu Wang, Kaushik Roy:
Maximum power estimation for CMOS circuits using deterministic and statistic approaches. 364-369 - Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Low power realization of FIR filters using multirate architectures. 370-375
Session 22: Asynchronous Circuits, Retiming, and Paritioning
- Alain Guyot, Marc Renaudin, Bachar El-Hassan, Volker Levering:
Self timed division and square-root extraction. 376-381 - Radhakrishna Nagalla, Graham R. Hellestrand:
Elimination of Dynamic Hazards from Signal Transition Graphs. 382-388 - Sung-Bum Park, Takashi Nanya:
Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications. 389-392 - Prathima Agrawal, Balakrishnan Narendran, Narayanan Shivakumar:
Multi-way partitioning of VLSI circuits. 393-399 - Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya:
Geometric bipartitioning problem and its applications to VLSI. 400-405
Session 23: Delay Testing
- Ramesh C. Tekumalla, Premachandran R. Menon:
Identifying Redundant Path Delay Faults in Sequential Circuits. 406-411 - Mukund Sivaraman, Andrzej J. Strojwas:
Diagnosis of parametric path delay faults. 412-417 - Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal:
On test coverage of path delay faults. 418-421 - Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
Improving accuracy in path delay fault coverage estimation. 422-425 - Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal:
Parallel concurrent path-delay fault simulation using single-input change patterns. 426-431
Panel Discussion
- Anantha P. Chandrakasan, Kurt Keutzer, A. Khandekar, S. L. Maskara, B. D. Pradhan, Mani B. Srivastava:
Mobile Communications: Demands on VLSI Technology, Design and CAD. 432-436
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-20 22:21 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
