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ORCIDHLSS 1994: Niagra-on-the-Lake, ON, Canada
- Pierre G. Paulin:
Proceedings of the 7th International Symposium on High Level Synthesis, HLSS'94, Niagra-on-the-Lake, ON, Canada, May 18-20, 1994. ACM 1994, ISBN 0-8186-5785-5 - Giovanni Mancini:
Hardware/software co-verification in ATM. 1-7 - Asawaree Kalavade, Edward A. Lee:
A methodology for simulation and synthesis of mixed hardware/software systems. 10 - Johan Van Praet, Gert Goossens, Dirk Lanneer, Hugo De Man:
Instruction set definition and instruction selection for ASIPs. 11-16 - Dirk Lanneer, Marco Cornero, Gert Goossens, Hugo De Man:
Data routing: a paradigm for efficient data-path synthesis and code generation. 17-22 - Marco A. Escalante, Nikitas J. Dimopoulos:
Timing analysis for synthesis in microprocessor interface design. 23-28 - Lawrence F. Arnstein, Donald E. Thomas:
Applications of attributed-behavior synthesis. 29-34 - Samit Chaudhuri, Robert A. Walker:
Computing lower bounds on functional units before scheduling. 36-41 - Doron Mintz, Carlos Dangelo:
Timing estimation for behavioral descriptions. 42-47 - Albert van der Werf, Jef L. van Meerbergen, Emile H. L. Aarts, Wim F. J. Verhaegh, Paul E. R. Lippens:
Efficient timing constraint derivation for optimal retiming high speed processing units. 48-53 - Pravil Gupta, Alice C. Parker:
SMASH: a program for scheduling memory-intensive application-specific hardware. 54-59 - Ivan P. Radivojevic, Forrest Brewer
:
Ensemble representation and techniques for exact control-dependent scheduling. 60-65 - Leon Stok:
Is high-level synthesis marketable? (panel). 66 - F. Kenneth Zadeck:
State-of-the-art compiler optimization. 67-68 - Thomas Charles Wilson, Gary Gréwal, Ben Halley, Dilip K. Banerji:
An integrated approach to retargetable code generation. 70-75 - Koen Schoofs, Gert Goossens, Hugo De Man:
Bit-alignment for retargetable code generators. 76-81 - Wei-Kai Cheng, Youn-Long Lin:
Code generation for a DSP processor. 82-87 - Rainer Leupers, Wolfgang Schenk, Peter Marwedel:
Retargetable assembly code generation by bootstrapping. 88-93 - Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala:
CodeSyn: a retargetable code synthesis system (abstract). 94 - Ravibala Singh, John Knight:
Concurrent testing in high-level synthesis. 96-103 - Prabhakar Kudva, Venkatesh Akella:
Testing two-phase transition signaling based self-timed circuits in a synthesis environment. 104-111 - Chih-Tung Chen, Alice C. Parker:
A hybrid numeric/symbolic program for checking functional and timing compatibility of synthesized designs. 112-117 - Ruchir Puri, Jun Gu:
A divide-and-conquer approach for asynchronous interface synthesis. 118-125 - Ramesh Karri, Karin Högstedt, Alex Orailoglu:
Rapid prototyping of fault-tolerant VLSI systems. 126-131 - Peter Marwedel:
ASICs vs ASIPs (panel). 132 - Peter Gutberlet, Wolfgang Rosenstiel:
Specification of interface components for synchronous data paths. 134-139 - Michael Sheliga, Edwin Hsing-Mean Sha:
Global node reduction of linear systems using ratio analysis. 140-145 - Martin Janssen, Francky Catthoor, Hugo De Man:
A specification invariant technique for operation cost minimisation in flow-graphs. 146-151 - D. Sreenivasa Rao, Fadi J. Kurdahi:
Controller and datapath trade-offs in hierarchical RT-level synthesis. 152-157 - Steve C.-Y. Huang, Wayne H. Wolf:
How datapath allocation affects controller delay. 158-163 - Roger P. Ang, Nikil D. Dutt:
An algorithm for the allocation of functional units from realistic RT component libraries. 164-169
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