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Lerong Cheng
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2010 – 2019
- 2014
- [j16]Lerong Cheng, Wenyao Xu, Fengbo Ren, Fang Gong, Puneet Gupta, Lei He:
Statistical timing and power analysis of VLSI considering non-linear dependence. Integr. 47(4): 487-498 (2014) - 2012
- [j15]Lerong Cheng, Wenyao Xu, Fang Gong, Yan Lin, Ho-Yan Wong, Lei He:
Statistical Timing and Power Optimization of Architecture and Device for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 5(2): 9:1-9:19 (2012) - [j14]Lerong Cheng, Fang Gong, Wenyao Xu, Jinjun Xiong, Lei He, Majid Sarrafzadeh:
Fourier Series Approximation for Max Operation in Non-Gaussian and Quadratic Statistical Static Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1383-1391 (2012) - 2011
- [j13]Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He:
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 388-401 (2011) - 2010
- [j12]Fei He, Lerong Cheng, Xiaoyu Song, Guowu Yang:
An Analytical Congestion Model with Bounded-Bend Detours. J. Circuits Syst. Comput. 19(2): 479-490 (2010) - [c13]Lerong Cheng, Puneet Gupta, Lei He:
On confidence in characterization and application of variation models. ASP-DAC 2010: 751-756 - [c12]Tuck-Boon Chan, Aashish Pant, Lerong Cheng, Puneet Gupta:
Design dependent process monitoring for back-end manufacturing cost reduction. ICCAD 2010: 116-122
2000 – 2009
- 2009
- [j11]Lerong Cheng, Jinjun Xiong, Lei He:
Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 130-140 (2009) - [j10]Lerong Cheng, Puneet Gupta, Lei He:
Efficient Additive Statistical Leakage Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1777-1781 (2009) - [c11]Lerong Cheng, Puneet Gupta, Lei He:
Accounting for non-linear dependence using function driven component analysis. ASP-DAC 2009: 474-479 - [c10]Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He:
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. DAC 2009: 104-109 - 2008
- [j9]Lerong Cheng, Xiaoyu Song, Guowu Yang, William N. N. Hung, Zhiwei Tang, Shaodi Gao:
A fast congestion estimator for routing with bounded detours. Integr. 41(3): 360-370 (2008) - [c9]Lerong Cheng, Jinjun Xiong, Lei He:
Non-Gaussian statistical timing analysis using second-order polynomial fitting. ASP-DAC 2008: 298-303 - [c8]Lerong Cheng, Yan Lin, Lei He:
Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. FPGA 2008: 159-168 - 2007
- [j8]Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He:
Device and Architecture Cooptimization for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1211-1221 (2007) - [c7]Lerong Cheng, Jinjun Xiong, Lei He:
Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources. DAC 2007: 250-255 - 2006
- [j7]Fei He, Xiaoyu Song, Ming Gu, Lerong Cheng, Guowu Yang, Zhiwei Tang, Jiaguang Sun:
A combinatorial congestion estimation approach with generalized detours. Comput. Math. Appl. 51(6-7): 1113-1126 (2006) - [j6]Ming Gu, Fei He, Lerong Cheng, Xiaoyu Song, Guowu Yang:
Congestion estimation for hexagonal routing. Int. J. Comput. Math. 83(3): 263-272 (2006) - [c6]Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton:
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. FPL 2006: 1-6 - 2005
- [j5]Fei He, Ming Gu, Xiaoyu Song, Zhiwei Tang, Guowu Yang, Lerong Cheng:
Probabilistic Estimation for Routing Space. Comput. J. 48(6): 667-676 (2005) - [j4]Fei He, Lerong Cheng, Guowu Yang, Xiaoyu Song, Ming Gu, Jia-Guang Sun:
On Theoretical Upper Bounds for Routing Estimation. J. Univers. Comput. Sci. 11(6): 916-925 (2005) - [j3]Yih-Chyun Jenq, Lerong Cheng:
Digital spectrum of a nonuniformly sampled two-dimensional signal and its reconstruction. IEEE Trans. Instrum. Meas. 54(3): 1180-1187 (2005) - [c5]Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He:
Device and architecture co-optimization for FPGA power reduction. DAC 2005: 915-920 - [c4]Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He:
FPGA device and architecture evaluation considering process variations. ICCAD 2005: 19-24 - [c3]Fei He, Xiaoyu Song, Lerong Cheng, Guowu Yang, Zhiwei Tang, Ming Gu, Jia-Guang Sun:
A Hierachical Method for Wiring and Congestion Prediction. ISVLSI 2005: 307-308 - 2004
- [j2]Lerong Cheng, William N. N. Hung, Guowu Yang, Xiaoyu Song:
Congestion estimation for 3-D circuit architectures. IEEE Trans. Circuits Syst. II Express Briefs 51-II(12): 655-659 (2004) - [j1]William N. N. Hung, Xiaoyu Song, T. Kam, Lerong Cheng, Guowu Yang:
Routability checking for three-dimensional architectures. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1371-1374 (2004) - [c2]Lerong Cheng, Xiaoyu Song, Guowu Yang, Zhiwei Tang:
A fast congestion estimator for routing with bounded detours. ASP-DAC 2004: 666-670 - [c1]Lerong Cheng, William N. N. Hung, Guowu Yang, Xiaoyu Song:
Congestion Estimation for 3D Routing. ISVLSI 2004: 239-240
Coauthor Index
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