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ORCIDISSCC 2019: San Francisco, CA, USA
- IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019. IEEE 2019, ISBN 978-1-5386-8531-0
- Yann LeCun:
Deep Learning Hardware: Past, Present, and Future. 12-19 - Hoi-Jun Yoo:
Intelligence on Silicon: From Deep-Neural-Network Accelerators to Brain Mimicking AI-SoCs. 20-26 - Meint Smit, Kevin A. Williams, Jos van der Tol:
Integration of Photonics and Electronics. 29-34 - Vida Ilderem:
5G Wireless Communication: An Inflection Point. 35-39 - James A. Kahle, Jaime Moreno, Daniel Dreps:
Summit and Sierra: Designing AI/HPC Supercomputers. 42-43 - Sander Smets, Toon Goedemé
, Anurag Mittal, Marian Verhelst:
A 978GOPS/W Flexible Streaming Processor for Real-Time Image Processing Applications in 22nm FDSOI. 44-46 - Utsav Banerjee, Abhishek Pathak, Anantha P. Chandrakasan:
An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things. 46-48 - Vinayak Honkote, Dileep Kurian, Sriram Muthukumar, Dibyendu Ghosh, Satish Yada, Kartik Jain, Bradley Jackson, Ilya Klotchkov, Mallikarjuna Rao Nimmagadda, Shreela Dattawadkar, Pranjali Deshmukh, Ankit Gupta, Jaykant Timbadiya, Ravi Pali, Karthik Narayanan, Saksham Soni, Saransh Chhabra, Praveen Dhama, N. Sreenivasulu, Jisna Kollikunnel, Sureshbabu Kadavakollu, Vijay Deepak Sivaraj, Paolo A. Aseron, Leonid Azarenkov, Nancy Robinson, Arun Radhakrishnan, Mikhail J. Moiseev, Ganeshram Nandakumar, Akhila Madhukumar, Roman Popov, Kamakhya P. Sahu, Ramesh Peguvandla, Alberto Del Rio Ruiz, Mukesh Bhartiya, Anuradha Srinivasan, Vivek De:
A Distributed Autonomous and Collaborative Multi-Robot System Featuring a Low-Power Robot SoC in 22nm CMOS for Integrated Battery-Powered Minibots. 48-50 - Luke R. Everson, Sachin S. Sapatnekar, Chris H. Kim:
A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control. 50-52 - Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka:
A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. 52-54 - Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Naoto Okumura, Shohei Maeda, Tomonori Yanagita, Takao Koike, Yasuhisa Shimazaki, Masao Ito, Minoru Uemura, Toshihiro Hattori, Tadaaki Yamauchi, Hiroyuki Kondo:
A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D. 54-56 - Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx:
A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. 58-60 - Wenning Jiang, Yan Zhu, Minglei Zhang, Chi-Hang Chan, Rui Paulo Martins:
A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier. 60-62 - Athanasios Ramkaj, Juan Carlos Pena Ramos, Yifan Lyu, Maarten Strackx, Marcel J. M. Pelgrom, Michiel Steyaert, Marian Verhelst, Filip Tavernier:
A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS. 62-64 - Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun:
A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor. 64-66 - Minglei Zhang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins:
A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques. 66-68 - Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. 68-70 - Ahmed ElShater, Calvin Yoji Lee, Praveen Kumar Venkatachala, Jason Muhlestein, Spencer Leuenberger, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon:
A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier. 70-72 - Aoyang Zhang, Mike Shuo-Wei Chen:
A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency. 74-76 - Liang Xiong, Tong Li, Yun Yin, Hao Min, Na Yan, Hongtao Xu:
A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement. 76-78 - Zhidong Bai, Wen Yuan, Ali Azam, Jeffrey Sean Walling:
A Multiphase Interpolating Digital Power Amplifier for TX Beamforming in 65nm CMOS. 78-80 - Inchan Ju, Michael J. McPartlin, Chun-Wen Paul Huang, Clifford D. Y. Cheon, Mark Doherty, John D. Cressler:
A Highly Linear High-Power 802.11ac/ax WLAN SiGe HBT Power Amplifier Using a Compact 2nd-Harmonic-Shorting Four-Way Transformer and Integrated Thermal Sensors. 80-82 - Mohamed Hussein Eissa, Dietmar Kissinger:
A 13.5dBm Fully Integrated 200-to-255GHz Power Amplifier with a 4-Way Power Combiner in SiGe: C BiCMOS. 82-84 - Huy Thong Nguyen, Sensen Li, Hua Wang:
A mm-Wave 3-Way Linear Doherty Radiator with Multi Antenna Coupling and On-Antenna Current-Scaling Series Combiner for Deep Power Back-Off Efficiency Enhancement. 84-86 - Omar El-Aassar, Gabriel M. Rebeiz:
A Compact DC-to-108GHz Stacked-SOI Distributed PA/Driver Using Multi-Drive Inter-Stack Coupling, Achieving 1.525THz GBW, 20.8dBm Peak P1dB, and Over 100Gb/s in 64-QAM and PAM-4 Modulation. 86-88 - Fei Wang, Tso-Wei Li, Hua Wang:
A Highly Linear Super-Resolution Mixed-Signal Doherty Power Amplifier for High-Efficiency mm-Wave 5G Multi-Gb/s Communications. 88-90 - Huy Thong Nguyen, Doohwan Jung, Hua Wang:
A 60GHz CMOS Power Amplifier with Cascaded Asymmetric Distributed-Active-Transformer Achieving Watt-Level Peak Output Power with 20.8% PAE and Supporting 2Gsym/s 64-QAM Modulation. 90-92 - Chen Xu, Yaowu Mo, Guanjing Ren, Weijian Ma, Xin Wang, Wenjie Shi, Jinjian Hou, Ke Shao, Haojie Wang, Pengge Xiao, Zexu Shao, Xiao Xie, Xiaoyong Wang, Chris Yiu:
A Stacked Global-Shutter CMOS Imager with SC-Type Hybrid-GS Pixel and Self-Knee Point Calibration Single Frame HDR and On-Chip Binarization Algorithm for Smart Vision Applications. 94-96 - Kyojin David Choo, Li Xu, Yejoong Kim, Ji-Hwan Seol, Xiao Wu, Dennis Sylvester, David T. Blaauw:
Energy-Efficient Low-Noise CMOS Image Sensor with Capacitor Array-Assisted Charge-Injection SAR ADC for Motion-Triggered Low-Power IoT Applications. 96-98 - Christopher Young, Alex Omid-Zohoor, Pedram Lajevardi, Boris Murmann:
A Data-Compressive 1.5b/2.75b Log-Gradient QVGA Image Sensor with Multi-Scale Readout for Always-On Object Detection. 98-100 - Injun Park, Chanmin Park, Jimin Cheon, Youngcheol Chae:
A 76mW 500fps VGA CMOS Image Sensor with Time-Stretched Single-Slope ADCs Achieving 1.95e- Random Noise. 100-102 - Navid Sarhangnejad, Nikola Katic, Zhengfan Xia, Mian Wei, Nikita Gusev, Gairik Dutta, Rahul Gulve, Harel Haim, Manuel Moreno Garcia, David Stoppa, Kiriakos N. Kutulakos, Roman Genov:
Dual-Tap Pipelined-Code-Memory Coded-Exposure-Pixel CMOS Image Sensor for Multi-Exposure Single-Frame Computational Imaging. 102-104 - Yutaka Hirose, Shinzo Koyama, Toru Okino, Akito Inoue, Shigeru Saito, Yugo Nose, Motonori Ishii, Seiji Yamahira, Shigetaka Kasuga, Mitsuyoshi Mori, Tatsuya Kabe, Kentaro Nakanishi, Manabu Usuda, Akihiro Odagawa, Tsuyoshi Tanaka:
A 400×400-Pixel 6μm-Pitch Vertical Avalanche Photodiodes CMOS Image Sensor Based on 150ps-Fast Capacitive Relaxation Quenching in Geiger Mode for Synthesis of Arbitrary Gain Images. 104-106 - Robert K. Henderson, Nick Johnston, Sam W. Hutchings, István Gyöngy, Tarek Al Abbas, Neale A. W. Dutton, Max Tyler, Susan Chan, Jonathan Leach:
A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager. 106-108 - Sayuri Yokoyama, Masayuki Ikebe, Yuri Kanazawa, Takahiro Ikegami, Prasoon Ambalathankandy, Shota Hiramatsu, Eiichi Sano, Yuma Takida, Hiroaki Minamide:
A 32×32-Pixel 0.9THz Imager with Pixel-Parallel 12b VCO-Based ADC in 0.18μm CMOS. 108-110 - Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Martino Dazzi, Thomas Toifl:
A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET. 112-114 - Marc-Andre LaCroix, Henry Wong, Yun Hua Liu, Huong Ho, Semyon Lebedev, Petar Krotnev, Dorin Alexandru Nicolescu, Dmitry Petrov, Carlos Carvalho, Stephen Alie, Euhan Chong, Faisal Ahmed Musa, Davide Tonietto:
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss. 114-116 - Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto G. Massolini, Giovanni Cesura, Ivan Bietti:
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET. 116-118 - Tamer A. Ali, Ramy Yousry, Henry Park, Ehung Chen, Po-Shuan Weng, Yi-Chieh Huang, Chun-Cheng Liu, Chien-Hua Wu, Shih-Hao Huang, Chungshi Lin, Ke-Chung Wu, Kun-Hung Tsai, Kai-Wen Tan, Ahmed ElShater, Kuang-Ren Chen, Wei-Hao Tsai, Huan-Sheng Chen, Weiyu Leng, Mazen Soliman:
A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology. 118-120 - Chang-Feng Loi, A. Mellati, Amber Tan, A. Farhoodfar, Arun Tiruvur, Belal Helal, Bob Killips, Farshid Rafiee Rad, Jamal Riani, Jorge Pernillo, J. Sun, J. Wong, K. Abdelhalim, K. Gopalakrishnan, Kwang Young Kim, Lawrence Tse, M. Davoodi, Michael Q. Le, M. Zhang, M. Talegaonkar, P. Prabha, Ravindran Mohanavelu, S. Chong, Simon Forey, S. Netto, Sudeep Bhoja, W. Liew, Yida Duan, Y. Liao:
A 400Gb/s Transceiver for PAM-4 Optical Direct-Detect Application in 16nm FinFET. 120-122 - Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli:
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS. 122-124 - Pen-Jui Peng, Yan-Ting Chen, Sheng-Tsung Lai, Chao-Hsuan Chen, Hsiang-En Huang, Ted Shih:
A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS. 124-126 - Danny Yoo, Mohammad Bagherbeik, Wahid Rahman, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki:
A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS. 126-128 - Jinook Song, Yunkyo Cho, Jun-Seok Park, Jun-Woo Jang, Sehwan Lee, Joon-Ho Song, Jae-Gon Lee, Inyup Kang:
An 11.5TOPS/W 1024-MAC Butterfly Structure Dual-Core Sparsity-Aware Neural Processing Unit in 8nm Flagship Mobile SoC. 130-132 - Yutaka Yamada, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda, Masato Uchiyama, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Ryusuke Murakami, Takashi Yoshikawa:
A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications. 132-134 - Ziyun Li, Yu Chen, Luyao Gong, Lu Liu, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim:
An 879GOPS 243mW 80fps VGA Fully Visual CNN-SLAM Processor for Wide-Range Autonomous Exploration. 134-136 - Changhyeon Kim, Sanghoon Kang, Dongjoo Shin, Sungpill Choi, Youngwoo Kim, Hoi-Jun Yoo:
A 2.1TFLOPS/W Mobile Deep RL Accelerator with Transposable PE Array and Experience Compression. 136-138 - Jinshan Yue, Ruoyang Liu, Wenyu Sun, Zhe Yuan, Zhibo Wang, Yung-Ning Tu, Yi-Ju Chen, Ao Ren, Yanzhi Wang, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu:
A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture. 138-140 - Jeongwoo Park, Juyun Lee, Dongsuk Jeon:
A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback. 140-142 - Jinsu Lee, Juhyoung Lee, Donghyeon Han, Jinmook Lee, Gwangtae Park, Hoi-Jun Yoo:
LNPU: A 25.3TFLOPS/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8-FP16. 142-144 - Christopher Schaef, Sheldon Weng, Beomseok Choi, William J. Lambert, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A 93.8% Peak Efficiency, 5V-Input, 10A Max ILOAD Flying Capacitor Multilevel Converter in 22nm CMOS Featuring Wide Output Voltage Range and Flying Capacitor Precharging. 146-148 - Abdullah Abdulslam, Patrick P. Mercier:
A Continuous-Input-Current Passive-Stacked Third-Order Buck Converter Achieving 0.7W/mm2 Power Density and 94% Peak Efficiency. 148-150 - Casey Hardy, Hanh-Phuc Le:
A 10.9W 93.4%-Efficient (27W 97%-Efficient) Flying-Inductor Hybrid DC-DC Converter Suitable for 1-Cell (2-Cell) Battery Charging Applications. 150-152 - Nghia Tang, Bai Nguyen, Yangyang Tang, Wookpyo Hong, Zhiyuan Zhou, Deukhyoun Heo:
Fully Integrated Buck Converter with 78% Efficiency at 365mW Output Power Enabled by Switched-Inductor Capacitor Topology and Inductor Current Reduction Technique. 152-154 - Christopher Schaef, Nachiket V. Desai, Harish Krishnamurthy, Sheldon Weng, Huong Do, William J. Lambert, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation. 154-156 - Peter Renz, Maik Kaufmann, Michael Lueders, Bernhard Wicht:
A Fully Integrated 85%-Peak-Efficiency Hybrid Multi Ratio Resonant DC-DC Converter with 3.0-to-4.5V Input and 500μA -to-120mA Load Range. 156-158 - Jing Xue, Minkyu Song, Xugang Ke, Min Chen, Leonard Shtargot:
A 2MHz 4-to-60VIN Buck-Boost Converter for Automotive Use Achieving 95% Efficiency and CISPR 25 Class 5 Standard. 158-160 - Chih-Ming Hung, Alex T. C. Lin, B. C. Peng, Hua Wang, Jui-Lin Hsu, Yen-Ju Lu, Wei-Show Hsu, Jing-Hong Conan Zhan, Brian Juan, Chi-Hang Lok, Sam Lee, P. C. Hsiao, Qiang Zhou, Mark Wei, Hsiang-Yun Chu, Yu-Lun Chen, Chao-Ching Hung, Kevin Fong, Po-Chun Huang, Pierce Chen, Sheng-Yuan Su, Yan-Jiun Chen, Kehou Chen, Chun-Chao Tung, Yi-Jhan Hsieh, Tzung-Chuen Tsai, Yi-Fu Chen, Wei-Kuo Hsin, Liang Guo, Hanfei Liu, Dapeng Jin:
Toward Automotive Surround-View Radars. 162-164 - Vito Giannini, Marius Goldenberg, Aria Eshraghi, James Maligeorgos, Lysander Lim, Ryan Lobo, Dave Welland, Chung-Kai Chow, Andrew Dornbusch, Tim Dupuis, Struan Vaz, Fred Rush, Paul Bassett, Hong Kim, Monier Maher, Otto Schmid, Curtis Davis, Manju V. Hegde:
A 192-Virtual-Receiver 77/79GHz GMSK Code-Domain MIMO Radar System-on-Chip. 164-166 - Yao-Hong Liu, Sunil Sheelavant, Marco Mercuri, Paul Mateman, Johan Dijkhuis, Agossou Wilfried Zomagboguelou, Arjan Breeschoten, Stefano Traferro, Yan Zhang, Tom Torfs, Christian Bachmann, Pieter Harpe, Masoud Babaie:
A680 μW Burst-Chirp UWB Radar Transceiver for Vital Signs and Occupancy Sensing up to 15m Distance. 166-168 - Akshay Visweswaran, Kristof Vaesen, Siddhartha Sinha, Ilja Ocket, Miguel Glassee, Claude Desset, André Bourdoux, Piet Wambacq:
A 145GHz FMCW-Radar Transceiver in 28nm CMOS. 168-170 - Sangyeop Lee, Ruibing Dong, Takeshi Yoshida, Shuhei Amakawa, Shinsuke Hara, Akifumi Kasamatsu, Junji Sato, Minoru Fujishima:
An 80Gb/s 300GHz-Band Single-Chip CMOS Transceiver. 170-172 - Chintan Thakkar, Stefan Shopov, Anandaroop Chakrabarti, Shuhei Yamada, Debabani Choudhury, James E. Jaussi, Bryan Casper:
A 42.2Gb/s 4.3pJ/b 60GHz Digital Transmitter with 12b/Symbol Polarization MIMO. 172-174 - Stefano Pellerano, Steven Callender, Woorim Shin, Yanjie Wang, Somnath Kundu, Abhishek Agrawal, Peter Sagazio, Brent R. Carlton, Farhana Sheikh, Arnaud Amadjikpe, William J. Lambert, Divya Shree Vemparala, Mark Chakravorti, Satoshi Suzuki, Robert Flory, Chris Hull:
A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology. 174-176 - Jinseok Park, Seungchan Lee, Dong-Ho Lee, Songcheol Hong:
A 28GHz 20.3%-Transmitter-Efficiency 1.5°-Phase-Error Beamforming Front-End IC with Embedded Switches and Dual-Vector Variable-Gain Phase Shifters. 176-178 - Seyed Danesh, William Holland, Joe Spalding, Michael Guidry, J. E. D. Hurwitz:
An Energy Measurement Front-End with Integrated In-Situ Background Full System Accuracy Monitoring Including the Current and Voltage Sensors. 180-182 - Yuki Furubayashi, Takashi Oshima, Taizo Yamawaki, Keiki Watanabe, Keijiro Mori, Naoki Mori, Akira Matsumoto, Hideto Kazama, Yudai Kamada, Atsushi Isobe, Tomonori Sekiguchi:
A 22ng/√Hz 17mW MEMS Accelerometer with Digital Noise-Reduction Techniques. 182-184 - Sining Pan, Cagri Gurleyuk, Matheus F. Pimenta, Kofi A. A. Makinwa:
A 0.12mm2 Wien-Bridge Temperature Sensor with 0.1°C (3σ) Inaccuracy from -40°C to 180°C. 184-186 - Sining Pan, Kofi A. A. Makinwa:
A Wheatstone Bridge Temperature Sensor with a Resolution FoM of 20fJ.K2. 186-188 - Jihee Lee, Kyoung-Rog Lee, Benjamin E. Eovino, Jeong Hoan Park, Liwei Lin, Hoi-Jun Yoo, Jerald Yoo:
A 5.37mW/Channel Pitch-Matched Ultrasound ASIC with Dynamic-Bit-Shared SAR ADC and 13.2V Charge-Recycling TX in Standard CMOS for Intracardiac Echocardiography. 190-192 - Arun Manickam, Kae-Dyi You, Nicholas Wood, Lei Pei, Yang Liu, Rituraj Singh, Nader Gamini, Davood Shahrjerdi, Robert G. Kuimelis, Arjang Hassibi:
A CMOS Biosensor Array with 1024 3-Electrode Voltammetry Pixels and 93dB Dynamic Range. 192-194 - Seung-Woo Song, Jukwan Na, Moon Hyung Jang, Hyeyeon Lee, Hyesoo Lee, Yongbeom Lim, Heonjin Choi, Youngcheol Chae:
A Capacitive Biosensor for Cancer Diagnosis Using a Functionalized Microneedle and a 13.7b-Resolution Capacitance-to-Digital Converter from 1 to 100nF. 194-196 - Xiahan Zhou, Michael Sveiven, Drew A. Hall:
A Fast-Readout Mismatch-Insensitive Magnetoresistive Biosensor Front-End Achieving Sub-ppm Sensitivity. 196-198 - Changhyuk Lee, Adriaan J. Taal, Jaebin Choi, Kukjoo Kim, Kevin Tien, Laurent C. Moreaux, Michael L. Roukes, Kenneth L. Shepard:
A 512-Pixel 3kHz-Frame-Rate Dual-Shank Lensless Filterless Single-Photon-Avalanche-Diode CMOS Neural Imaging Probe. 198-200 - Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. 202-204 - Hiroki Inoue, Takeshi Aoki, Fumika Akasawa, Toshiki Hamada, Toshihiko Takeuchi, Kousei Nei, Takako Seki, Yuto Yakubo, Kei Takahashi, Shuji Fukai, Takahiko Ishizu, Munehiro Kozuma, Ryota Tajima, Takanori Matsuzaki, Takayuki Ikeda, Makoto Ikeda, Shunpei Yamazaki:
Micro Short-Circuit Detector Including S/H Circuit for 1hr Retention and 52dB Comparator Composed of C-Axis Aligned Crystalline IGZO FETs for Li-Ion Battery Protection IC. 204-206 - Florian De Roose, Jan Genoe, Auke Jisk Kronemeijer, Kris Myny, Wim Dehaene:
Memory Solutions for Flexible Thin-Film Logic: up to 8kb, >105.9kb/s LPROM and SRAM with Integrated Timing Generation Meeting the ISO NFC Standard. 206-208 - Noboru Shibata, Kazushige Kanda, Takahiro Shimizu, Jun Nakai, Osamu Nagao, Naoki Kobayashi, Makoto Miakashi, Yasushi Nagadomi, Takeshi Nakano, Takahisa Kawabe, Taira Shibuya, Mario Sako, Kosuke Yanagidaira, Toshifumi Hashimoto, Hiroki Date, Manabu Sato, Tomoki Nakagawa, H. Takamoto, Junji Musha, Takatoshi Minamoto, Mizuki Uda, Dai Nakamura, Katsuaki Sakurai, Takahiro Yamashita, Jieyun Zhou, Ryoichi Tachibana, Teruo Takagiwa, Takahiro Sugimoto, Mikio Ogawa, Yusuke Ochi, Kazuaki Kawaguchi, Masatsugu Kojima, Takeshi Ogawa, Tomoharu Hashiguchi, Ryo Fukuda, Masami Masuda, Koichi Kawakami, Tadashi Someya, Yasuyuki Kajitani, Yuuki Matsumoto, Naohito Morozumi, Jumpei Sato, Namas Raghunathan, Yee Lih Koh, Shuo Chen, Juan Lee, Hiroaki Nasu, Hiroshi Sugawara, Koji Hosono, Toshiki Hisada, T. Kaneko, Hiroshi Nakamura:
A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology. 210-212 - Pulkit Jain, Umut Arslan, Meenakshi Sekhar, Blake C. Lin, Liqiong Wei, Tanaya Sahu, Juan Alzate-vinasco, Ajay Vangapaty, Mesut Meterelliyoz, Nathan Strutt, Albert B. Chen, Patrick Hentges, Pedro A. Quintero, Chris Connor, Oleg Golonzka, Kevin Fischer, Fatih Hamzaoglu:
A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V. 212-214 - Liqiong Wei, Juan G. Alzate, Umut Arslan, Justin Brockman, Nilanjan Das, Kevin Fischer, Tahir Ghani, Oleg Golonzka, Patrick Hentges, Rawshan Jahan, Pulkit Jain, Blake C. Lin, Mesut Meterelliyoz, Jim O'Donnell, Conor Puls, Pedro A. Quintero, Tanaya Sahu, Meenakshi Sekhar, Ajay Vangapaty, Chris Wiegand, Fatih Hamzaoglu:
A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique. 214-216 - Dongku Kang, Minsu Kim, Suchang Jeon, Wontaeck Jung, Jooyong Park, Gyo Soo Choo, Dong-Kyo Shim, Anil Kavala, Seungbum Kim, Kyung-Min Kang, Jiyoung Lee, Kuihan Ko, Hyun Wook Park, ByungJun Min, Changyeon Yu, Sewon Yun, Nahyun Kim, Yeonwook Jung, Sungwhan Seo, Sunghoon Kim, Moo Kyung Lee, Joo-Yong Park, James C. Kim, Young San Cha, Kwangwon Kim, Youngmin Jo, Hyun-Jin Kim, Youngdon Choi, Jindo Byun, Ji-hyun Park, Kiwon Kim, Tae-Hong Kwon, Young-Sun Min, Chiweon Yoon, Youngcho Kim, Dong-Hun Kwak, Eungsuk Lee, Wook-Ghee Hahn, Ki-Sung Kim, Kyungmin Kim, Euisang Yoon, Wontae Kim, Inryul Lee, Seunghyun Moon, Jeong-Don Ihm, Dae-Seok Byeon, Ki-Whan Song, Sangjoon Hwang, Kyehyun Kyung:
A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface. 216-218 - Chang Hua Siau, Kwang-Ho Kim, Seungpil Lee, Katsuaki Isobe, Noboru Shibata, Kapil Verma, Takuya Ariki, Jason Li, Jong Yuh, Anirudh Amarnath, Qui Nguyen, Ohwon Kwon, Stanley Jeong, Heguang Li, Hua-Ling Hsu, Taiyuan Tseng, Steve Choi, Siddhesh Darne, Pradeep Anantula, Alex Yap, Hardwell Chibvongodze, Hitoshi Miwa, Minoru Yamashita, Mitsuyuki Watanabe, Koichiro Hayashi, Yosuke Kato, Toru Miwa, Jang Yong Kang, Masatoshi Okumura, Naoki Ookuma, Muralikrishna Balaga, Venky Ramachandra, Aki Matsuda, Swaroop Kulkarni, Raghavendra Rachineni, Pai K. Manjunath, Masahito Takehara, Anil Pai, Srinivas Rajendra, Toshiki Hisada, Ryo Fukuda, Naoya Tokiwa, Kazuaki Kawaguchi, Masashi Yamaoka, Hiromitsu Komai, Takatoshi Minamoto, Masaki Unno, Susumu Ozawa, Hiroshi Nakamura, Tomoo Hishida, Yasuyuki Kajitani, Lei Lin:
A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology. 218-220 - Ningyuan Cao, Muya Chang, Arijit Raychowdhury:
A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics. 222-224 - Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester:
A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration. 224-226 - Tony F. Wu, Binh Q. Le, Robert M. Radway, Andrew Bartolo, William Hwang, Seungbin Jeong, Haitong Li, Pulkit Tandon, Elisa Vianello, Pascal Vivet, Etienne Nowak, Mary Wootters, H.-S. Philip Wong, Mohamed M. Sabry Aly, Edith Beigné, Subhasish Mitra:
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques. 226-228 - Aseem Sayal, Shirin Fathima, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni:
All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing. 228-230 - Xun Sun, Akshat Boora, Wenbing Zhang, Venkata Rajesh Pamula, Visvesh Sathe:
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS. 230-232 - Shuo Li, Benton H. Calhoun:
A 745pA Hybrid Asynchronous Binary-Searching and Synchronous Linear-Searching Digital LDO with 3.8×105 Dynamic Load Range, 99.99% Current Efficiency, and 2mV Output Voltage Ripple. 232-234 - Xiaosen Liu, Harish K. Krishnamurthy, Taesik Na, Sheldon Weng, Khondker Z. Ahmed, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation. 234-236 - Ji-Seon Paek, Dong-Su Kim, Jun-Suk Bang, Jongbeom Baek, Jeong-Hyun Choi, Takahiro Nomiyama, Jae-Yeol Han, Young-Hwan Choo, Yong-Sik Youn, Euiyoung Park, Sung-Jun Lee, Ik-Hwan Kim, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
An 88%-Efficiency Supply Modulator Achieving 1.08μs/V Fast Transition and 100MHz Envelope-Tracking Bandwidth for 5G New Radio RF Power Amplifier. 238-240 - Ji-Seon Paek, Takahiro Nomiyama, Jae-Yeol Han, Ik-Hwan Kim, Yumi Lee, Dongsu Kim, Euiyoung Park, Sung-Jun Lee, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang:
A 90ns/V Fast-Transition Symbol-Power-Tracking Buck Converter for 5G mm-Wave Phased-Array Transceiver. 240-242 - Cheng-Yu Xie, Shang-Hsien Yang, Shen-Fu Lu, Fa-Yi Lin, Yen-An Lin, You-Zheng Ou-Yang, Ke-Horng Chen, Kuo-Chi Liu, Ying-Hsi Lin:
A 100W and 91% GaN-Based Class-E Wireless-Power-Transfer Transmitter with Differential-Impedance-Matching Control for Charging Multiple Devices. 242-244 - Yue Zhuo, Shaoyu Ma, Tianting Zhao, Wenhui Qin, Yuanyuan Zhao, Yingjie Guo, Baoxing Chen:
A 52% Peak-Efficiency >1W Isolated Power Transfer System Using Fully Integrated Magnetic-Core Transformer. 244-246 - Wenhui Qin, Xin Yang, Shaoyu Ma, Fang Liu, Yuanyuan Zhao, Tianting Zhao, Baoxing Chen:
An 800mW Fully Integrated Galvanic Isolated Power Transfer System Meeting CISPR 22 Class-B Emission Levels with 6dB Margin. 246-248 - Yingping Chen, Dongsheng Brian Ma:
A 10MHz i-Collapse Failure Self-Prognostic GaN Power Converter with TJ-Independent In-Situ Condition Monitoring and Proactive Temperature Frequency Scaling. 248-250 - Yingping Chen, Dongsheng Brian Ma:
An 8.3MHz GaN Power Converter Using Markov Continuous RSSM for 35dBμV Conducted EMI Attenuation and One-Cycle TON Rebalancing for 27.6dB VO Jittering Suppression. 250-252