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ORCIDVLSI-SoC 2011: Kowloon, Hong Kong, China
- IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011. IEEE 2011, ISBN 978-1-4577-0171-9
- Xiaojin Zhao, Amine Bermak
, Farid Boussaïd:
A low cost CMOS polarimetric ophthalmoscope scheme for cerebral malaria diagnostics. 1-4 - Hirokazu Nakazawa, Makoto Ishida, Kazuaki Sawada:
Multimodal proton and fluorescence image sensor for bio applications. 5-9 - Toshihiko Noda, Takuya Kitao, Takasuke Ito, Kiyotaka Sasagawa, Takashi Tokuda, Yasuo Terasawa, Hiroyuki Tashiro, Hiroyuki Kanda, Takashi Fujikado, Jun Ohta:
Fabrication of a flexible neural interface device with CMOS-based smart electrodes. 10-14 - Kiyotaka Sasagawa, Hiroyuki Masuda, Ayato Tagawa, Takuma Kobayashi, Toshihiko Noda, Takashi Tokuda, Jun Ohta:
Micro CMOS image sensor for multi-area imaging. 15-18 - Khawar Sarfraz:
A novel low-leakage 8T differential SRAM cell. 19-24 - Tso-Bing Juang, Hsin-Hao Peng, Chao-Tsung Kuo:
Area-efficient 3-input decimal adders using simplified carry and sum vectors. 25-30 - Jianhua Li, Chun Jason Xue, Yinlong Xu:
STT-RAM based energy-efficiency hybrid cache for CMPs. 31-36 - Weisheng Zhao, Yue Zhang, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli:
Embedded MRAM for high-speed computing. 37-42 - Shaowei Zhen, Bo Zhang, Ping Luo, Kang Yang, Xiaohui Zhu, Jiangkun Li:
A high efficiency synchronous buck converter with adaptive dead time control for dynamic voltage scaling applications. 43-48 - Xin Ming, Ze-kun Zhou, Bo Zhang:
A low-power ultra-fast capacitor-less LDO with advanced dynamic push-pull techniques. 54-59 - Jamshaid Sarwar Malik, Jameel Nawaz Malik, Ahmed Hemani, Nasirud Din Gohar:
Generating high tail accuracy Gaussian Random Numbers in hardware using central limit theorem. 60-65 - Myat Thu Linn Aung, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo:
Adaptive priority toggle asynchronous tree arbiter for AER-based image sensor. 66-71 - Jiang Ying, Xinhua Chen, Yibo Fan, Xiaoyang Zeng:
MUX-MCM based quantization VLSI architecture for H.264/AVC high profile encoder. 72-77 - Oliver Mitea, Markus Meissner, Lars Hedrich:
Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts. 78-81 - Marcel Veloso Campos, André Luís Fortunato, Carlos Alberto dos Reis Filho:
New 12-bit source-follower track-and-hold circuit suitable for high-speed applications. 82-85 - Qingyun Ma, Mohammad Rafiqul Haider, Yehia Massoud:
A low-loss rectifier unit for inductive-powering of biomedical implants. 86-89 - Yiorgos I. Bontzios, Michael G. Dimopoulos, Alkis A. Hatzopoulos:
Prospects of 3D inductors on through silicon vias processes for 3D ICs. 90-93 - Le Yu, Haigang Yang, Jia Zhang, Wei Wang:
Performance evaluation of air-gap-based coaxial RF TSV for 3D NoC. 94-97 - Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon:
Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC. 98-101 - Siwat Saibua, Liuxi Qian, Dian Zhou:
Worst case analysis for evaluating VLSI circuit performance bounds using an optimization method. 102-105 - Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi:
An easily testable routing architecture of FPGA. 106-109 - Jeong Hoon Kim, In Jung Lyu, Hyun June Lyu, Jun Rim Choi:
Minimizing redundancy-based motion estimation design for high-definition. 110-113 - Hong-Yuan Jheng, Yen-Hsiang Chen, Shanq-Jang Ruan, Ziming Qi:
FPGA implementation of high sampling rate in-car non-stationary noise cancellation based on adaptive Wiener filter. 114-117 - Pramod Kumar Meher, Yu Pan:
MCM-based implementation of block FIR filters for high-speed and low-power applications. 118-121 - Guanwen Zhong, Hongbin Zheng, ZhenHua Jin, Dihu Chen, Zhiyong Pang:
1024-point pipeline FFT processor with pointer FIFOs based on FPGA. 122-125 - Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao:
A 230mV 8-bit sub-threshold microprocessor for wireless sensor network. 126-129 - Asim Khan, Kyungsu Kang, Chong-Min Kyung:
Exploiting maximum throughput in 3D multicore architectures with stacked NUCA cache. 130-135 - Antonio Artés, José Luis Ayala, Ashoka Visweswara Sathanur, Jos Huisken, Francky Catthoor:
Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications. 136-141 - Huan Chen, João Marques-Silva:
Improvements to satisfiability-based boolean function bi-decomposition. 142-147 - Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro:
A hybrid algorithm for the optimization of area and delay in linear DSP transforms. 148-153 - Keisuke Inoue, Mineo Kaneko:
Early planning for RT-level delay insertion during clock skew-aware register binding. 154-159 - Haotian Liu, Fengrui Shi, Yuanzhe Wang, Ngai Wong:
Frequency-domain transient analysis of multitime partial differential equation systems. 160-163 - Ernesto Sánchez, Giovanni Squillero, Alberto Paolo Tonda:
Post-silicon failing-test generation through evolutionary computation. 164-167 - Franco Fummi, Davide Quaglia, Francesco Stefanni:
Communication-aware middleware-based design-space exploration for Networked Embedded Systems. 168-171 - Naifeng Jing, Weifeng He, Zhigang Mao:
A general statistical estimation for application mapping in Network-on-Chip. 172-175 - Jing Xie, Huimin Xing, Zhigang Mao:
On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system. 176-179 - Nizar Dahir, Terrence S. T. Mak, Alex Yakovlev:
Communication centric on-chip power grid models for networks-on-chip. 180-183 - Jian-Fei Jiang, Xu Wang, Wei-Guang Sheng, Wei-Feng He, Zhi-Gang Mao:
A clock-less transceiver for global interconnect. 184-187 - Jizeng Wei, Yisong Chang, Wei Guo, Jizhou Sun:
An optimized TTA-like vertex shader datapath for embedded 3D graphics processing unit. 188-191 - Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui:
A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources. 192-195 - Surya Narayanan, Ludovic Devaux, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis:
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources. 196-199 - Anupam Chattopadhyay, Zoltan Endre Rakosi:
Combinational logic synthesis for material implication. 200-203 - Seokjoong Kim, Matthew R. Guthaus:
SNM-aware power reduction and reliability improvement in 45nm SRAMs. 204-207 - Toshiyuki Tsuchiya, Hiroyuki Tokusaki, Yoshikazu Hirai, Koji Sugano, Osamu Tabata:
Self-dependent equivalent circuit modeling of electrostatic comb transducers for integrated MEMS. 208-213 - Zhijian Zhou, Man Wong, Libor Rufer:
Wide-band piezoresistive aero-acoustic microphone. 214-219 - Alex Man Ho Kwan, Sichao Song, Xing Lu, Lei Lu, Ying Khai Teh, Ying Fei Teh, Eddie Wing Cheung Chong, Yan Gao, William Hau, Fan Zeng, Man Wong, Chunmei Huang, Akira Taniyama, Yoshihide Makino, So Nishino, Toshiyuki Tsuchiya, Osamu Tabata:
Designs for improving the performance of an electro-thermal in-plane actuator. 220-225 - Yanan Sun, Volkan Kursun:
Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm P-channel MOSFETs. 226-231 - Pascal Vivet, Denis Dutoit, Yvain Thonnart, Fabien Clermidy:
3D NoC using through silicon Via: An asynchronous implementation. 232-237 - Tadahiro Kuroda:
ThruChip interface (TCI) for 3D networks on chip. 238-241 - Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu:
Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC). 242-247 - Yang Chai, Minghui Sun, Zhiyong Xiao, Yuan Li, Min Zhang, Philip C. H. Chan:
Towards future VLSI interconnects using aligned carbon nanotubes. 248-253 - Ming Zhu, Liyi Xiao, Hong Wei Luo:
New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory. 254-259 - Jia Zhang, Le Yu, Haigang Yang, Y. L. Xie, F. B. Zhou, Wei Wang:
Self-test method and recovery mechanism for high frequency TSV array. 260-265 - Charvi Dhoot, Vincent John Mooney, Shubhajit Roy Chowdhury, Lap-Pui Chau:
Fault tolerant design for low power hierarchical search motion estimation algorithms. 266-271 - Ernesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda:
On the functional test of Branch Prediction Units based on Branch History Table. 278-283 - Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Agent-based on-chip network using efficient selection method. 284-289 - Wenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu, Botao Zhang, Dongpei Liu:
Network-on-Chip multicasting with low latency path setup. 290-295 - Ying Fei Teh, Zhiliang Qian, Chi-Ying Tsui:
A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme. 296-301 - Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Lima Kastensmidt, Gianluca Palermo, Cristina Silvano:
Two-levels of adaptive buffer for virtual channel router in NoCs. 302-307 - Alberto Ghiribaldi, Daniele Ludovici, Michele Favalli, Davide Bertozzi:
System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic. 308-313 - J. Gerardo García-Sánchez, José Manuel de la Rosa Utrera:
Multirate hybrid continuous-time/discrete-time cascade 2-2 ΣΔ modulator for wideband telecom. 314-318 - Xiaohui Zhu, Ping Luo, Shaowei Zhen, Kang Yang, Jiangkun Li, Zekun Zhou:
A voltage mode power converter with the function of digitally duty cycle tuning. 319-324 - Brendan Mullane, Vincent O'Brien:
A high performance band-pass DAC architecture and design targeting a low voltage silicon process. 325-330 - Venkata Narasimha Manyam, Dhurv Chhetri, J. Jacob Wikner:
Clockless asynchronous delta modulator based ADC for smart dust applications. 331-336 - Xiaohang Wang, Maurizio Palesi, Mei Yang, Yingtao Jiang, Michael C. Huang, Peng Liu:
Low latency and energy efficient multicasting schemes for 3D NoC-based SoCs. 337-342 - Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch:
3-D integration and the limits of silicon computation. 343-348 - Alexey Lopich, Piotr Dudek:
Architecture and design of a programmable 3D-integrated cellular processor array for image processing. 349-353 - Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon:
Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network. 354-358 - Tzu-Chi Huang, Yao-Yi Yang, Yu-Huei Lee, Ming-Jhe Du, Shih-Hsien Cheng, Ke-Horng Chen:
A battery-free energy harvesting system with the switch capacitor sampler (SCS) technique for high power factor in smart meter applications. 359-362 - Joseph Sankman, Dongsheng Ma:
A subthreshold digital maximum power point tracker for micropower piezoelectric energy harvesting applications. 363-367 - Janet Meiling Wang Roveda, Susan Lysecky, Young-Jun Son, Hyungtaek Chang, Anita Annamalai, Xiao Qin:
Interface model based cyber-physical energy system design for smart grid. 368-373 - Wing-Hung Ki, Yan Lu, Feng Su, Chi-Ying Tsui:
Design and analysis of on-chip charge pumps for micro-power energy harvesting applications. 374-379 - Fabio Cenni, Serge Scotti, Emmanuel Simeu:
SystemC AMS behavioral modeling of a CMOS video sensor. 380-385 - Roman Plyaskin, Andreas Herkersdorf:
Context-aware compiled simulation of out-of-order processor behavior based on atomic traces. 386-391 - Manas Kumar Puthal, Virendra Singh, Manoj Singh Gaur, Vijay Laxmi:
C-Routing: An adaptive hierarchical NoC routing methodology. 392-397 - Jorge Fernandez Villena, L. Miguel Silveira:
Positive realization of reduced RLCM nets. 398-403 - Felipe Frantz, Lioua Labrak, Ian O'Connor:
3D-IC floorplanning: Applying meta-optimization to improve performance. 404-409 - Josef Dobes, David Cerny, Abhimanyu Yadav:
A more efficient arrangement of the sparse LU factorization for the large-scale circuit analysis. 416-421 - H. Gregor Molter, André Seffrin, Sorin A. Huss:
State space optimization within the DEVS model of computation for timing efficiency. 422-427 - Pramod Kumar Meher, Sang Yoon Park:
High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic. 428-433 - Jialiang Liu, Xinhua Chen, Yibo Fan, Xiaoyang Zeng:
A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder. 434-439 - Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao:
Robust design of sub-threshold flip-flop cells for wireless sensor network. 440-443
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