default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDVLSI-DAT 2014: Hsinchu, Taiwan
- Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, Hsinchu, Taiwan, April 28-30, 2014. IEEE 2014
- Jian Wang, Huawei Li, Xiaowei Li:
A novel abstraction-guided simulation approach using posterior probabilities for verification. 1-4 - David Prutchi:
Electroceuticals - Replacing drugs by devices enabled through advanced VLSI technologies. 1 - Joseph Sankman, Minkyu Song, Dongsheng Ma:
A 40-MHz current-mode hysteretic controlled switching converter with digital push-pull current pumping technique for high performance microprocessors. 1-4 - Der-Wei Yang, Li-Chia Chu, Chun-Wei Chen, Jia-Ming Gan, Jonas Wang, Ming-Der Shieh:
Low complexity stereo matching algorithm using adaptive sized square window. 1-4 - Shang-Yi Chuang, Jia-Ju Liao, Chia-Ching Chou, Chia-Chi Chang, Wai-Chi Fang:
An effective arterial blood pressure signal processing system based on EEMD method. 1-4 - Ching-Che Chung
, Duo Sheng, Chen-Han Chen:
An all-digital phase-locked loop compiler with liberty timing files. 1-4 - Yipin Wu, Zhigang Hao, Jingchun Han, Joy Tsai:
A novel power noise simulation methodology for chip design using Wafer Level Chip Scale Packaging. 1-4 - Kuo-Chiang Hung, Tim Chen:
Power integrity optimization on USB power distribution network for EMI reduction. 1-4 - Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh:
Output selection for test response compaction based on multiple counters. 1-4 - Sandeep Kumar Goel, Min-Jer Wang, Saman Adham, Ashok Mehta, Frank Lee:
Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs. 1-4 - Wei Zhang, Yizhi Han, Fei Chen, Bo Zhou, Xican Chen, Woogeun Rhee, Zhihua Wang:
A 3.5-4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDC. 1-4 - Chia-I Chen, Chin-Yeh Yu, Yen-Ju Lu, Chi-Feng Wu:
Apply high-level synthesis design and verification methodology on floating-point unit implementation. 1-4 - Yung-Kuei Lu, Shen-Ming Chung, Ming-Der Shieh:
Low-complexity architecture for Chase soft-decision Reed-Solomon decoding. 1-4 - Po-Han Wang, Gen-Hong Liu, Jen-Chieh Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky:
Full system simulation framework for integrated CPU/GPU architecture. 1-4 - Meng-Lieh Sheu, Te-Hsiang Liu, Lin-Jie Tsao:
A 22.4 fJ/conversion 0.7V 1.6μW 10-bit successive approximation ADC. 1-4 - Tsu-Wei Tseng, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai:
A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage. 1-4 - Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, Guan-Ying Huang:
Low power pipelined SAR ADC with loading-free architecture. 1-4 - Ronald M. Martino:
Roadway to innovation. 1 - Sung-Yao Wang, Hung-Hsien Wu, Chia-Ling Wei:
An integrated boost converter with maximum power point tracking for solar photovoltaic energy harvesting. 1-4 - Yuan-Sheng Lee, Hsien-Kai Hsin, Kun-Chih Chen, En-Jui Chang, An-Yeu Andy Wu:
Thermal-aware Dynamic Buffer Allocation for Proactive routing algorithm on 3D Network-on-Chip systems. 1-4 - Eddie Spears:
Next generation front end solutions for mobile application. 1 - Chang Hao, Huaguo Liang, Li Yang, Yiming Ouyang:
Optimized stacking order for 3D-stacked ICs considering the probability and cost of failed bonding. 1-4 - Kuo-Chiang Chang, Ching-Hao Lin, Chih-Wei Liu:
Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier. 1-4 - Atul Tambe:
Trends and directions in networking - Impact of virtualization and cloud. 1 - Hung-Chin Wang:
A frequency-domain detection and estimation scheme for single-tone interference suppression. 1-4 - Nick Cheng:
Highly integrated 4G front end modules for handset applications - A designer's perspective. 1 - Yi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang:
Two-staged parallel layer-aware partitioning for 3D designs. 1-4 - Shih-Lun Chen, Ming-Jing Ho, Yu-Ming Sun, Maung Wai Lin, Jung-Chin Lai:
An all-digital delay-locked loop for high-speed memory interface applications. 1-4 - Tong-Yu Hsieh, Kuan-Hsien Li, Yi-Han Peng:
On efficient error-tolerability evaluation and maximization for image processing applications. 1-4 - Jia-An Jheng, Wei-Sung Chang, Tai-Cheng Lee:
A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth. 1-4 - Takeshi Ikenaga, Takahiro Suzuki:
Smart feature detection device for cloud based video recognition system. 1-3 - Kai-Chen Huang, Po-Yu Chien, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A 360-degree panoramic video system design. 1-4 - Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang:
Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. 1-4 - Anthony S. Oates:
Will reliability limit Moore's law? 1 - Hau-Yung Chen, Ming Juan, Hsin-Hao Chen, Arvin Guan:
Practical electrical parameter aware methodology for analog designers with emphasis on LDE aware for devices. 1-4 - Shyue-Kung Lu, Huai-Min Li, Masaki Hashizume, Jin-Hua Hong, Zheng-Ru Tsai:
Efficient test length reduction techniques for interposer-based 2.5D ICs. 1-4 - Sriram Kalpat:
Design for reliability for low power digital circuits. 1 - Cuei-Ling Hsieh, Chang-Ming Lai, Guan-Hong Ke, Jenny Yi-Chun Liu, Po-Chiun Huang:
A mixed-signal phase-domain FSK demodulator for BLE single-path low-IF receiver. 1-4 - Mei Chang:
Precision material engineering - An equipment point of view. 1-3 - Chetan Prasad:
Advanced CMOS reliability challenges. 1-2 - Shen-Fu Hsiao, Wen-Ling Wang, Po-Sheng Wu:
VLSI implementations of stereo matching using Dynamic Programming. 1-4 - Yung-Chih Chen, Kung-Ming Ji:
SAT-based complete logic implication with application to logic optimization. 1-4 - Hsin-Yu Ting, Chih-Tsun Huang:
Design of low-cost elliptic curve cryptographic engines for ubiquitous security. 1-4 - Jae Min Cho, Kiyoung Choi:
An FPGA implementation of high-throughput key-value store using Bloom filter. 1-4 - Bumman Kim:
Bias adapted operation of CMOS PA for handset application. 1 - Subhasish Mitra, Pradip Bose, Eric Cheng, Chen-Yong Cher, Hyungmin Cho, Rajiv V. Joshi, Young Moon Kim, Charles R. Lefurgy, Yanjing Li, Kenneth P. Rodbell, Kevin Skadron, James H. Stathis, Lukasz G. Szafaryn:
The resilience wall: Cross-layer solution strategies. 1-11 - Chih-Hao Lin, Chih-Cheng Hsieh, Che-Chun Lin, Ren-Jr Chen:
A dual-mode CMOS image sensor for optical wireless communication. 1-4 - Niloofar Farnoosh, Athanasios G. Polimeridis, Thomas J. Klemas, Luca Daniel:
Accelerated domain decomposition FEM-BEM solver for magnetic resonance imaging (MRI) via discrete empirical interpolation method. 1-4 - Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou:
An ultra-low-power adaptive-body-bias control for subthreshold circuits. 1-4 - Rong-Zhou Kuo, Hao-Chiao Hong:
A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits. 1-4 - Yanbing Wang, Hong Wang, Deyong Meng, Bingqin Zhou:
Oscillation-based diagnosis by using harmonics analysis on analog filters. 1-4 - Po-Hsun Wu, Che-Wen Chen, Chi-Ruo Wu, Tsung-Yi Ho:
Triangle-based process hotspot classification with dummification in EUVL. 1-4 - Franz Dielacher, Marc Tiebout, Rudolf Lachner, Herbert Knapp, Klaus Aufinger, Willy Sansen:
SiGe BiCMOS technology and circuits for active safety systems. 1-4 - Hung-Wen Lin, Jin-Yi Lin, Min-Tai Chuang:
A low-area digitalized channel selection filter for DSRC system. 1-4 - Mostafa Said, Mohamed El-Sayed, Farhad Mehdipour, Nobuaki Miyakawa:
Keep-Out-Zone analysis for three-dimensional ICs. 1-4 - Mincent Lee, Saman Adham, Min-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen:
A novel DFT architecture for 3DIC test, diagnosis and repair. 1-4 - Hung-Yi Yang:
Highly automated and efficient simulation environment with UVM. 1-3 - Ching-Che Chung, Chi-Yu Hou:
All-digital delay-locked loop for 3D-IC die-to-die clock synchronization. 1-4 - Zebo Peng:
Thermal challenges to building reliable embedded systems. 1-2 - Yen-Kuang Chen:
Energy efficiency in the Internet of Things - Critical or nice-to-have? 1 - Janak Porwal, Sanket Diwale, Vinay B. Y. Kumar, Sachin B. Patkar:
Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems. 1-4 - Chih-Chan Tu, Tsung-Hsien Lin:
Analog front-end amplifier for ECG applications with feed-forward EOS cancellation. 1-4 - Taisuke Hayashi, Noriyuki Miura, Kumpei Yoshikawa, Makoto Nagata:
A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils. 1-4 - Chen-Yi Lee, Kelvin Yi-Tse Lai, Shu-Yu Hsu:
Event-driven read-out circuits for energy-efficient sensor-SoC's. 1-2 - Yi-Ming Wang, Mango Chia-Tso Chao, Shi-Hao Chen, Hung-Chun Li:
Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs. 1-4 - Jean-Pierre Raskin:
SOI technology: An opportunity for RF designers? 1-2 - Huiying Zhuo, Yu Li, Woogeun Rhee, Zhihua Wang:
A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS. 1-4 - Jing-Teng Lin, Jiunn-Hung Shiau, Chien-Hung Tsai:
A fast transient and under/overshoot suppression DC-DC Buck converter with ACP control. 1-4 - Kun-Chih Chen, Huai-Ting Li, An-Yeu Andy Wu:
LMS-based adaptive temperature prediction scheme for proactive thermal-aware three-dimensional Network-on-Chip systems. 1-4 - Yi-Long Yu, Fu-Chen Huang, Chorng-Kuang Wang:
A 1V 10-bit 500KS/s energy-efficient SAR ADC using Master-Slave DAC technique in 180nm CMOS. 1-4 - Yen-Lung Chen, Guan-Ming Chu, Ying-Chi Lien, Ching-Mao Lee, Chien-Nan Jimmy Liu:
Simultaneous optimization for low dropout regulator and its error amplifier with process variation. 1-4 - Yung-Chang Chang, Li-Ren Huang, Hsing-Chuang Liu, Chih-Jen Yang, Ching-Te Chiu:
Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements. 1-4 - Ryosuke Okuda, Yuki Kajiwara, Kazuaki Terashima:
A survey of technical trend of ADAS and autonomous driving. 1-4 - Li-C. Wang:
Design trends and test challenges in automotive electronics. 1 - Weiwei Shen, Yibo Fan, Leilei Huang, Jiali Li, Xiaoyang Zeng:
A hardware-friendly method for rate-distortion optimization of HEVC intra coding. 1-4 - Seok-Hee Lee:
Scaling trends and challenges of advanced memory technology. 1 - Kartikeya Bhardwaj, Pravin S. Mane:
C3Map and ARPSO based mapping algorithms for energy-efficient regular 3-D NoC architectures. 1-4 - Shih-Hsin Hsu, Wei-Zen Chen, Jui-Pin Zheng, Sean S.-Y. Liu, Po-Cheng Pan, Hung-Ming Chen:
An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming. 1-4 - Jörg Henkel:
Dark Silicon - A thermal perspective. 1 - Dipesh Patel:
Internet of Things: Connecting the physical and digital worlds. 1 - Islam A. K. M. Mahfuzul, Hidetoshi Onodera:
Characterization and compensation of performance variability using on-chip monitors. 1-4 - Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li:
Skillfully diminishing antenna effect in layer assignment stage. 1-4
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-07-05 02:35 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
