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ORCIDCICC 2008: San Jose, California, USA
- Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008. IEEE 2008, ISBN 978-1-4244-2018-6
Keynote
- Dave Bergeron:
More than Moore.
Session 2 - Statistical modeling
- Hidetoshi Onodera, Hong-Ha Vuong:
Session 2 - Statistical modeling. - Sani R. Nassif:
Process variability at the 65nm node and beyond. 1-8 - Larry T. Pileggi, Gökçe Keskin, Xin Li, Ken Mai
, Jonathan E. Proesel:
Mismatch analysis and statistical design at 65 nm and below. 9-12 - Wenping Wang, Vijay Reddy, Bo Yang, Varsha Balakrishnan, Srikanth Krishnan, Yu Cao:
Statistical prediction of circuit aging under process variations. 13-16
Session 3 - Power management
- Gordon Lee, Makoto Takamiya:
Session 3 - Power management. - Mike Wens, Michiel Steyaert:
A fully-integrated 0.18μm CMOS DC-DC step-down converter, using a bondwire spiral inductor. 17-20 - Pengfei Li, Deepak Bhatia, Lin Xue, Rizwan Bashirullah:
A 90-240MHz hysteretic controlled DC-DC buck converter with digital PLL frequency locking. 21-24 - Chia-Hsiang Lin, Hong-Wei Huang, Ke-Horng Chen:
Fast transient technique (FTT) in buck current-mode DC-DC converters for low-voltage SoC systems. 25-28 - Fumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Hiroyuki Hara, Takeshi Kitahara, Shuou Nomura, Fumiyuki Yamane, Yoshiro Tsuboi, Keiko Seki, Shuuji Matsumoto, Yoshinori Watanabe, Mototsugu Hamada:
A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design. 29-32 - Chia-Hsiang Lin, Hong-Wei Huang, Ke-Horng Chen:
Built-in resistance compensation (BRC) technique for fast charging Li-Ion battery charger. 33-36
Session 4 - High-speed test, characterization, and debug
- Mike Li, Gordon W. Roberts:
Session 4 - High-speed test, characterization, and debug. - Genichi Tanaka, Kan Takeuchi, Minoru Ito, Hiroaki Matsushita:
A voltage drop aware crosstalk measurement with multi-aggressors in 65nm process. 37-40 - Gerry Talbot, Edoardo Prete:
Measurements of the silicon die characteristics of packaged drivers for high-speed I/O. 41-48 - Steven Thijs, Mototsugu Okushima, Jonathan Borremans, Philippe Jansen, Dimitri Linten, Mirko Scholz, Piet Wambacq, Guido Groeseneken:
Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications. 49-52 - Edward I. Cole Jr.:
Non-destructive IC defect localization using optical beam-based imaging. 53-56
Session 5 - Broadband circuit techniques for emerging wireless communications
- Fa Foster Dai, Howard C. Luong:
Session 5 - Broadband circuit techniques for emerging wireless communications. - John D. Cressler:
Emerging application opportunities for SiGe technology. 57-64 - Shuzuo Lou, Howard C. Luong:
A 0.8GHz-10.6GHz SDR low-noise amplifier in 0.13-μm CMOS. 65-68 - Zahra Safarian, Hossein Hashemi:
A 1.3-6 GHz triple-mode CMOS VCO using coupled inductors. 69-72
Session 6 - Advanced SoC/SiP integration & co-design
- Rich Liu, Philippe Jansen:
Session 6 - Advanced SoC/SiP integration & co-design. - Joy Laskar, Stephane Pinel, Saikat Sarkar, Padmanava Sen, Bevin G. Perunama, Debasis Dawn, David Yeh, Francesco Barale:
A SOC/SOP co-design approach for mmW CMOS in QFN technology. 73-80 - Eric D. Perfecto, Brian Sundlof, Kamalesh Srivastava, Minhua Lu:
Chip to carrier C4 technology challenges with Pb free solders. 81-84 - Kazuhiro Takahashi, Makoto Mita, Hiroyuki Fujita, Kazuhiro Suzuki, Hideyuki Funaki, Kazuhiko Itaya, Hiroshi Toshiyoshi:
A study on process-compatibility in CMOS-first MEMS-last integration. 85-88
Session 7 - High resolution converters
- Yusuf Haque, George LaRue:
Session 7 - High resolution converters. - Moo-Yeol Choi, Sung-No Lee, Seung-Bin You, Wang-Seup Yeum, Ho-Jin Park, Jae-Whui Kim, Hae-Seung Lee:
A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control. 89-92 - Kyehyung Lee, Matthew R. Miller, Gabor C. Temes:
An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and -98 dB THD. 93-96 - Yan Wang, Kyehyung Lee, Gabor C. Temes:
A 2.5MHz BW and 78dB SNDR delta-sigma modulator using dynamically biased amplifiers. 97-100 - Nima Maghari, Sunwoo Kwon, Un-Ku Moon:
74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain. 101-104 - Boris Murmann:
A/D converter trends: Power dissipation, scaling and digitally assisted architectures. 105-112 - Tae-Hwan Oh, Ho-Young Lee, Ju-Hwa Kim, Ho-Jin Park, Kyoung-Ho Moon, Jae-Whui Kim, Hae-Seung Lee:
A 16b 10MS/s digitally self-calibrated ADC with time constant control. 113-116 - Shoji Kawahito, Kazutaka Honda, Zheng Liu, Keita Yasutomi, Shinya Itoh:
A 15b power-efficient pipeline A/D converter using non-slewing closed-loop amplifiers. 117-120
Session 8 - Characterization and test methods for device variability in nanoscale technologies
- Hamid Mahmoodi, Jeanne Trinko Mechler:
Session 8 - Characterization and test methods for device variability in nanoscale technologies. - John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim:
An array-based test circuit for fully automated gate dielectric breakdown characterization. 121-124 - Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy:
A high sensitivity process variation sensor utilizing sub-threshold operation. 125-128 - Liang-Teck Pang, Borivoje Nikolic:
Measurement and analysis of variability in 45nm strained-Si CMOS technology. 129-132 - Bishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind, V. Visvanathan:
Within-die gate delay variability measurement using re-configurable ring oscillator. 133-136 - Taro Niiyama, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai:
Expected vectorless Teacher-Student Swap (TSS) test method with dual power supply voltages for 0.3V homogeneous multi-core LSI's. 137-140
Session 9 - Broadband circuit techniques for emerging wireless communications
- Fa Foster Dai, Howard C. Luong:
Session 9 - Broadband circuit techniques for emerging wireless communications. - Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano:
MIMO techniques for high data rate radio communications. 141-148 - Swaminathan Sankaran, Kyujin Oh, Hsin-Ta Wu, Kenneth K. O:
Wireless interconnection within a hybrid engine controller board. 149-152
Session 10 - Panel discussion Sure, Moore's Law can continue, but should it
- David A. Sunderland, Kazuyuki Kawauchi, John Kent, Randy Mooney, Chuck Moore, Clark T.-C. Nguyen:
Session 10 - Panel discussion Sure, Moore's Law can continue, but should it. - Jonathan E. Proesel, Lawrence T. Pileggi:
A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS. 153-156 - Yun-Shiang Shu, Moon-Jung Kyung, Wei-Ming Lee, Bang-Sup Song, Bedabrata Pain:
A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration. 157-160 - Parastoo Nikaeen, Boris Murmann:
Digital correction of dynamic track-and-hold errors providing SFDR ≫ 83 dB up to fin = 470 MHz. 161-164 - Kang-Jin Lee, Kyoung-Jun Moon, Kwang-Sung Ma, Kyoung-Ho Moon, Jae-Whui Kim:
A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling. 165-168 - David Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon:
A continuous-time input pipeline ADC. 169-172 - Michael Trakimas, Sameer R. Sonkusale:
A 0.8 V asynchronous ADC for energy constrained sensing applications. 173-176 - Xiaochun Wu, Alireza Khaligh, Yang Xu:
Modeling, design and optimization of hybrid electromagnetic and piezoelectric MEMS energy scavengers. 177-180 - Rahul Shringarpure, Lawrence T. Clark, Sameer M. Venugopal, David R. Allee, Shrinivas G. Uppili:
Amorphous silicon logic circuits on flexible substrates. 181-184 - Frederic Nabki, Tomas A. Dusatko, Mourad N. El-Gamal:
Frequency tunable silicon carbide resonators for MEMS above IC. 185-188 - Dominique Lemoine, Paul-Vahe Cicek, Frederic Nabki, Mourad N. El-Gamal:
MEMS wafer-level vacuum packaging with transverse interconnects for CMOS integration. 189-192 - Jing Li, Haixin Liu, Sayeef S. Salahuddin, Kaushik Roy:
Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement. 193-196 - Liyang Pan, Xian Luo, Yaru Yan, Jirong Ma, Dong Wu, Jun Xu:
Pure logic CMOS based embedded Non-Volatile Random Access Memory for low power RFID application. 197-200 - H. Henry Nho, Mark Horowitz, S. Simon Wong:
A high-speed, low-power 3D-SRAM architecture. 201-204 - Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Daihyun Lim, Sangyeun Cho:
Early prediction of product performance and yield via technology benchmark. 205-208 - Poki Chen, Juan-Shan Lai, Po-Yu Chen:
A FPGA vernier digital-to-time converter with 3.56ps resolution and -0.23∼+0.2LSB inaccuracy. 209-212 - Arindam Basu, Christopher M. Twigg, Stephen Brink, Paul E. Hasler, Csaba Petre, Shubha Ramakrishnan, Scott Koziol, Craig Schlottmann:
RASP 2.8: A new generation of floating-gate based field programmable analog array. 213-216 - Piljae Park, C. Patrick Yue:
Modeling of triple-well isolation and the loading effects on circuits up to 50 GHz. 217-220 - Wei Cheng, Anne-Johan Annema, Jeroen A. Croon, Dirk B. M. Klaassen, Bram Nauta:
A general weak nonlinearity model for LNAs. 221-224 - Bodhisatwa Sadhu, Umaikhe E. Omole, Ramesh Harjani:
Modeling and synthesis of wide-band switched-resonators for VCOs. 225-228 - Ben Gu, Kiran K. Gullapalli, Yun Zhang, Savithri Sundareswaran:
Faster statistical cell characterization using adjoint sensitivity analysis. 229-232 - Yuan-Wen Hsiao, Ming-Dou Ker:
An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process. 233-236 - Jongshin Shin, Jaehyun Park, Bongjin Kim, Jongjae Ryu, Chiwon Kim, Jiyoung Kim, Seung-Hee Yang, Hyungoo Kim, Jaewhui Kim:
A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer. 237-240 - Hungwen Lu, Chauchin Su, Chien-Nan Liu:
A scalable digitalized buffer for gigabit I/O. 241-244 - Ji-Chen Huang, Yu-Sheng Lai, K. Hsu:
Broadband transimpedance amplifier in 0.35-μm SiGe BiCMOS technology for 10-Gb/s optical receiver analog front-end application. 245-248 - Yin Shi, Foster F. Dai, Jun Yan, Xueqing Hu, Hua Xu, Ming Gu, Xuelian Zhang, Qiming Xu, Bei Chen, Fangxiong Chen, Peng Yu, Heping Ma, Fang Yuan, Richard C. Jaeger:
A multifunction transceiver RFIC for 802.11a/b/g WLAN and DVB-H applications. 249-252 - Yin Shi, Fa Foster Dai, Jun Yan, Hua Xu, Xuelian Zhang, Heping Ma, Fang Yuan, Xin Guan, Richard C. Jaeger:
A fully integrated zero-IF mobile TV tuner RFIC for S-band CMMB application. 253-256
Session 11 - Compact modeling
- Gennady Gildenblat, Brian Chen:
Session 11 - Compact modeling. - Yuan Taur, Jooyoung Song, Bo Yu:
Compact modeling of multiple-gate MOSFETs. 257-264 - Jung-Suk Goo, Richard Q. Williams, Glenn O. Workman, Qiang Chen, Sungjae Lee, Edward J. Nowak:
Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges. 265-272 - Hugh J. Barnaby, Michael L. McLain, Ivan Sanchez Esqueda, Xiao J. Chen:
Modeling ionizing radiation effects in solid state materials and CMOS devices. 273-280 - Ning Lu, Bill Dewey:
Characterization, simulation, and modeling of FET source/drain diffusion resistance. 281-284 - Minki Cho, Kingsuk Maitra, Saibal Mukhopadhyay:
Analysis of the impact of interfacial oxide thickness variation on metal-gate high-K circuits. 285-288 - David G. Nairn:
Time-interleaved analog-to-digital converters. 289-296 - Hao Yu, Sing W. Chin, Bill C. Wong:
A 12b 50MSPS 34mW pipelined ADC. 297-300 - Cheongyuen W. Tsang, Yun Chiu, Johan P. Vanderhaegen, Sebastian Hoyos, Charles Chen, Robert W. Brodersen, Borivoje Nikolic:
Background ADC calibration in digital domain. 301-304 - Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik:
A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process. 305-308 - Zhiheng Cao, Shouli Yan:
A 52mW 10b 210MS/s two-step ADC for digital-IF receivers in 0.13μm CMOS. 309-312 - Jaesik Lee, Joseph Weiner, Pascal Roux, Andreas Leven, Young-Kai Chen:
A 24GS/s 5-b ADC with closed-loop THA in 0.18μm SiGe BiCMOS. 313-316
Session 13 - Biomedical, sensors and MEMS
- Makoto Nagata, Steven L. Garverick:
Session 13 - Biomedical, sensors and MEMS. - Eusebiu Matei, Edward K. Lee, John Gord, Patrick Nercessian, Phil Hess, Howard Stover, Taihu Li, James Wolfe:
A biomedical implantable FES battery-powered micro-stimulator. 317-324 - Takashi Tokuda, Shigeki Sawamura, Yasuo Terasawa, Yasuo Tano, Jun Ohta:
CMOS LSI-based multi-chip flexible retinal prosthesis device for subretinal implantation. 325-328 - Young-Jae Min, Soo-Won Kim:
A CMOS TDC-based digital magnetic Hall sensor using the self temperature compensation. 329-332 - Jeremy Holleman, Apurva Mishra, Chris Diorio, Brian P. Otis:
A micro-power neural spike detector and feature extractor in .13μm CMOS. 333-336 - Frederic Nabki, Faisal Ahmad, Karim Allidina, Mourad N. El-Gamal:
A compact and programmable high-frequency oscillator based on a MEMS resonator. 337-340
Session 14 - Advanced SoCs - techniques and applications
- Steven J. E. Wilton, Arif Rahman:
Session 14 - Advanced SoCs - techniques and applications. - Kevin J. Nowka, Sani R. Nassif, Kanak Agarwal:
Characterization and design for variability and reliability. 341-346 - JunYoung Park, Joshua Jaeyoung Kang, Sunghyun Park, Michael P. Flynn:
A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines. 347-350 - Ting-Chen Wei, Wei-Chang Liu, Chi-Yao Tseng, Syu-Siang Long, Shyh-Jye Jou, Muh-Tian Shiue:
A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization. 351-354 - Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai:
Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs. 355-358 - Tino Copani, Bert Vermeire, Anuj Jain, Habib Karaki, Kailash Chandrashekar, Sushmit Goswami, Jennifer Kitchen, Hoon Hee Chung, Ilker Deligoz, Bertan Bakkaloglu, Hugh J. Barnaby, Sayfe Kiaei:
A fully integrated pulsed-LASER time-of-flight measurement system with 12ps single-shot precision. 359-362 - Hong Chen, Chen Jia, Yi Chen, Ming Liu, Chun Zhang, Zhihua Wang:
A low-power IC design for the wireless monitoring system of the orthopedic implants. 363-366 - Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
Tessellation-enabled shader for a bandwidth-limited 3D graphics engine. 367-370
Session 15 - IC Technology - more Moore and more than Moore
- Alvin Loke, Jordan Lai:
Session 15 - IC Technology - more Moore and more than Moore. - Kurt Ronse, Philippe Jansen, Roel Gronheid, Eric Hendrickx, Mireille Maenhoudt, Mieke Goethals, Geert Vandenberghe:
Lithography options for the 32nm half pitch node and beyond. 371-378 - Chris Auth:
45nm high-k + metal gate strain-enhanced CMOS transistors. 379-386 - Patrice Garcia, Alain Chantre, Sébastien Pruvost, Pascal Chevalier, Sean T. Nicolson, David Roy, Sorin P. Voinigescu, Christophe Garnier:
Will BiCMOS stay competitive for mmW applications ? 387-394 - John P. Kent, Jagdish Prasad:
Microelectronics for the real world: "Moore" versus "More than Moore". 395-402
Session 16 - Embedded memory
- Kenji Noda, Jean-Christophe Vial:
Session 16 - Embedded memory. - Mohammed H. Taufique, Alex Okpisz, Haseeb N. Ahmed, John R. Riley, Mohammad M. Hasan, Gianfranco Gerosa:
A 512-KB level-2 cache design in 45-nm for low power IA processor silverthorne. 403-406 - Tony Tae-Hyoung Kim, Jason Liu, Chris H. Kim:
A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode. 407-410 - Andrew Carlson, Zheng Guo, Liang-Teck Pang, Tsu-Jae King Liu, Borivoje Nikolic:
Compensation of systematic variations through optimal biasing of SRAM wordlines. 411-414 - Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai, Lawrence T. Pileggi:
Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. 415-418 - Myeong-Eun Hwang, Kaushik Roy:
A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology. 419-422 - Mingoo Seok, Scott Hanson, Jae-sun Seo, Dennis Sylvester, David T. Blaauw:
Robust ultra-low voltage ROM design. 423-426 - Nan Wang, Xiang Yao, Yu Lei, Guoyou Feng, Qiaohua Dong, Liang Xu, Lu Guo, Zi Wang, T. S. Tang:
A million cycle 0.13um 1Mb embedded SONOS Flash memory using Successive Approximated Read Calibration. 427-430
Session 17 - Clocking circuits
- Dennis Michael Fischette, Kimo Tam:
Session 17 - Clocking circuits. - Alexander V. Rylyakov, José A. Tierno, George English, Michael A. Sperling, Daniel J. Friedman:
A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI. 431-434 - Ting Wu, Xudong Shi, Kambiz Kaviani, Haechang Lee, Jung-Hoon Chun, T. J. Chin, Jie Shen, Rich Perego, Ken Chang:
Clocking circuits for a 16Gb/s memory interface. 435-438 - Sander Gierkink:
A 1V 15.6mW 1-2GHz -119dBc/Hz @ 200kHz clock multiplying DLL. 439-442 - Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu:
A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB. 443-446 - Masum Hossain, Anthony Chan Carusone:
20 GHz low power QVCO and De-skew techniques in 0.13μm digital CMOS. 447-450 - Fabio Pareschi, Gianluca Setti, Riccardo Rovatti:
A 3 GHz Spread Spectrum Clock Generator for SATA applications using chaotic PAM modulation. 451-454 - Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim, Chulwoo Kim:
A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation. 455-458 - Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei:
A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction. 459-462
Session 18 - Millimeter-wave circuit techniques
- Payam Heydari, Nobuyuki Itoh:
Session 18 - Millimeter-wave circuit techniques.