default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDHOST 2015: Washington, DC, USA
- IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2015, Washington, DC, USA, 5-7 May, 2015. IEEE Computer Society 2015, ISBN 978-1-4673-7420-0
Efficient Implementation of Secure Systems
- Aria Shahverdi, Mostafa Taha, Thomas Eisenbarth
:
Silent Simon: A threshold implementation under 100 slices. 1-6 - Mudit Bhargava, Kaship Sheikh, Ken Mai:
Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers. 7-13 - Kan Xiao, Domenic Forte, Mark Tehranipoor:
Efficient and secure split manufacturing via obfuscated built-in self-authentication. 14-19
PUF
- Georg T. Becker, Alexander Wild, Tim Güneysu:
Security analysis of index-based syndrome coding for PUF-based key generation. 20-25 - Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu:
Exploiting resistive cross-point array for compact design of physical unclonable function. 26-31 - Cheng-Wei Lin, Swaroop Ghosh:
A family of Schmitt-Trigger-based arbiter-PUFs and selective challenge-pruning for robustness and quality. 32-37
Posters
- Meng-Day (Mandel) Yu, Matthias Hiller, Srinivas Devadas:
Maximum-likelihood decoding of device-specific multi-bit symbols for reliable key generation. 38-43 - Abhishek Chakraborty, Bodhisatwa Mazumdar, Debdeep Mukhopadhyay:
A practical DPA on Grain v1 using LS-SVM. 44-47 - Gedare Bloom, Bhagirath Narahari, Rahul Simha, Ali Namazi, Renato Levy:
FPGA SoC architecture and runtime to prevent hardware Trojans from leaking secrets. 48-51 - Chongxi Bao, Yang Xie, Ankur Srivastava:
A security-aware design scheme for better hardware Trojan detection sensitivity. 52-55 - Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar:
Automatic obfuscated cell layout for trusted split-foundry design. 56-61 - Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, Laurent Sauvage:
High precision fault injections on the instruction cache of ARMv7-M architectures. 62-67 - Zachary N. Goddard, Nicholas LaJeunesse, Thomas Eisenbarth:
Power analysis of the t-private logic style for FPGAs. 68-71 - Bilgiday Yuce, Nahid Farhady Ghalaty, Patrick Schaumont:
TVVF: Estimating the vulnerability of hardware cryptosystems against timing violation attacks. 72-77 - Athanasios Papadimitriou, Marios Tampas, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle:
Validation of RTL laser fault injection model with respect to layout information. 78-81 - Xuan Thuy Ngo, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm:
Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses. 82-87 - Shamit Ghosh, Dipanwita Roy Chowdhury:
Preventing fault attack on stream cipher using randomization. 88-91 - Sushmita Kadiyala Rao, Deepak Krishnankutty, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel:
Post-layout estimation of side-channel power supply signatures. 92-95 - Qian Wang, An Wang, Liji Wu, Gang Qu, Guoshuang Zhang:
Template attack on masking AES based on fault sensitivity analysis. 96-99
Side Channel and Fault Attacks Analysis
- Dhiman Saha, Dipanwita Roy Chowdhury:
Diagonal fault analysis of Gr⊘stl in dedicated MAC mode. 100-105 - Richard Gilmore, Neil Hanley, Máire O'Neill:
Neural network based attack on a masked implementation of AES. 106-111 - Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken Mai:
A DPA-resistant self-timed three-phase dual-rail pre-charge logic family. 112-117 - Liwei Zhang, A. Adam Ding, Yunsi Fei, Pei Luo:
Efficient 2nd-order power analysis on masked devices utilizing multiple leakage. 118-123 - Xiaofei Guo, Naghmeh Karimi, Francesco Regazzoni, Chenglu Jin, Ramesh Karri:
Simulation and analysis of negative-bias temperature instability aging on power analysis attacks. 124-129 - Pascal Sasdrich, Amir Moradi, Oliver Mischke, Tim Güneysu:
Achieving side-channel protection with dynamic logic reconfiguration on modern FPGAs. 130-136
Hardware Trojan Horses, Security Analysis, Evaluations, and Metrics
- Pramod Subramanyan, Sayak Ray, Sharad Malik:
Evaluating the security of logic encryption algorithms. 137-143 - Ian Wilcox, Fareena Saqib, James F. Plusquellic:
GDS-II Trojan detection using multiple supply pad VDD and GND IDDQs in ASIC functional units. 144-150 - Ingrid Exurville, Loïc Zussa, Jean-Baptiste Rigaud, Bruno Robisson:
Resilient hardware Trojans detection based on path delay measurements. 151-156
Secure and Trusted Synthesis and Design
- Roarke Horstmeyer, Sid Assawaworrarit, Ulrich Rührmair, Changhuei Yang:
Physically secure and fully reconfigurable data storage using optical scattering. 157-162 - Mohammad-Mahdi Bidmeshki, Yiorgos Makris:
Toward automatic proof generation for information flow policies in third-party hardware IP. 163-168
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-05 22:34 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
