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IEEE Journal of Solid-State Circuits, Volume 31
Volume 31, Number 1, January 1996
- Kirk B. Ashby, Ico A. Koullias, William C. Finley, John J. Bastek, Shahriar Moinian:
High Q inductors for wireless applications in a complementary silicon bipolar process. 4-9 - Farhood Moraveji:
A wide-band, low-power, high slew rate voltage-feedback operational amplifier. 10-16 - Norihisa Yamamoto, Osamu Nakagawa, Kenji Takebuchi, Yukinori Kitamura:
An adjustment-free single-chip video signal processing LSI for VHS VCR's. 17-23 - Michael Neuhäuser, Hans-Martin Rein, Horst Wernz:
Low-noise, high-gain Si-bipolar preamplifiers for 10 Gb/s optical-fiber links-design and realization. 24-29 - Shoji Otaka, Takafumi Yamaji, Ryuichi Fujimoto, Chikau Takahashi, Hiroshi Tanimoto:
A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment. 30-37 - Norman P. Jouppi, Stefanos Sidiropoulos, Suresh Menon:
A speed, power, and supply noise evaluation of ECL driver circuits. 38-45 - Kimio Ueda, Nagisa Sasaki, Hisayasu Sato, Koichiro Mashiko:
A fully compensated active pull-down ECL circuit with self-adjusting driving capability. 46-53 - Zhihao Lao, Ulrich Langmann, Jens N. Albers, Erwin Schlag, Detlef Clawin:
Si bipolar 14 Gb/s 1: 4-demultiplexer IC for system applications. 54-60 - Thomas Linder, Herbert Zojer, Berthold Seger:
Fully analogue LMS adaptive notch filter in BICMOS technology. 61-69 - Douglas A. Mercer:
A 14-b 2.5 MSPS pipelined ADC with on-chip EPROM. 70-76 - Vojin G. Oklobdzija:
An ECL gate with improved speed and low power in a BiCMOS process. 77-83 - Hitoshi Okamura, Takao Atsumo, Koichi Takeda, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Tom Yamazaki:
A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump. 84-90 - Lawrence T. Clark, Gregory F. Taylor:
High fan-in circuit design. 91-96 - Hsin-hua Li, Nasser H. Kutkut, Deepakraj Divan, Krishna Shenai:
Design considerations of IGBT's in resonant converter applications. 97-105 - John S. Hamel:
Compact modeling of the influence of emitter stored charge on the high frequency small signal AC response of bipolar transistors using quasi-static parameters. 106-113 - Leo C. N. de Vreede, Henk C. de Graaff, Koen Mouthaan
, Marinus de Kok, Joseph L. Tauritz, Roel G. F. Baets:
Advanced modeling of distortion effects in bipolar transistors using the Mextram model. 114-121 - Eric Koenig, Jürgen Schneider, Ulrich Seiler, Uwe Erben, Hermann Schumacher:
Current-temperature feedback effects in III-V heterojunction bipolar transistors. 122-127 - Zhihao Lao, Ulrich Langmann:
Design of a low-power 10 Gb/s Si bipolar 1: 16-demultiplexer IC. 128-131 - Emmanuel Dubois, Paul-Henri Bricout, Etienne Robilliart:
Extraction method of the base series resistances in bipolar transistor in presence of current crowding. 132-135 - Colin C. McAndrew, Laurence W. Nagel:
Early effect modeling in SPICE. 136-138
Volume 31, Number 2, February 1996
- Satoshi Sakurai, Mohammed Ismail:
Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage. 146-156 - Rajesh H. Zele, David J. Allstot:
Low-power CMOS continuous-time filters. 157-168 - Michael K. Mayes, Sing W. Chin, Lee L. Stoian:
A low-power 1 MHz, 25 mW 12-bit time-interleaved analog-to-digital converter. 169-178 - Jean-Paul Eggennont, Denis De Ceuster, Denis Flandre
, Bernard Gentinne, Paul G. A. Jespers, Jean-Pierre Colinge:
Design of SOI CMOS operational amplifiers for applications up to 300°C. 179-186 - David H. K. Hoe, David B. Ribner:
An auto-ranging photodiode preamplifier with 114 dB dynamic range. 187-194 - Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami:
A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond. 195-201 - Khaled M. Sharaf, Mohamed I. Elmasry:
Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits. 202-211 - Yasuo Arai, Masahiro Ikeno:
A time digitizer CMOS gate-array with a 250 ps time resolution. 212-220 - Richard X. Gu, Mohamed I. Elmasry:
All-N-logic high-speed true-single-phase dynamic CMOS logic. 221-229 - Per Larsson-Edefors:
A 965-Mb/s 1.0-μm standard CMOS twin-pipe serial/parallel multiplier. 230-239 - Tadashi Maeda, Keiichi Numata, Masatoshi Tokushima
, Masaoki Ishikawa, Muneo Fukaishi, Hikam Hida, Yasuo Ohno:
A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's. 240-246 - M. Afghahi:
A robust single phase clocking for low power, high-speed VLSI applications. 247-254 - Trond Sæther, Chung-Chih Hung, Zheng Qi, Mohammed Ismail, Oddvar Aaserud:
High speed, high linearity CMOS buffer amplifier. 255-258 - Ming-Jer Chen, Jih-Shin Ho, Tzuen-Hsi Huang:
Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling. 259-262 - Tsuneo Tsukahara, Masayuki Ishikawa, Masahiro Muraguchi:
A 2-V 2-GHz Si-bipolar direct-conversion quadrature modulator. 263-267 - Mehmet Soyuer, Keith A. Jenkins, Joachim N. Burghartz, Herschel A. Ainspan, Frank J. Canora, Slaila Ponnapalli, John F. Ewen, William E. Pence:
A 2.4-GHz silicon bipolar oscillator with integrated resonator. 268-270 - J. D. Bruce, Harry W. Li, Michael J. Dallabetta, R. Jakob Baker:
Analog layout using ALAS! 271-274 - Kjell O. Jeppson:
Comments on the metastable behavior of mismatched CMOS latches. 275-277 - Barrie Gilbert, C. Chan, H. Ling, P. Choy:
Comments on "A one volt four-quadrant analog current mode multiplier cell" [with reply]. 278
Volume 31, Number 3, March 1996
- Ted Vinko Burmas, Kenneth C. Dyer, Paul J. Hurst, Stephen H. Lewis:
A second-order double-sampled delta-sigma modulator using additive-error switching. 284-293 - David W. Cline, Paul R. Gray:
A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS. 294-303 - Tristan Reimann, François Krummenacher, Michel J. Declercq:
An 8-b, 40 msamples/s switched-current-mode track-and-hold circuit on a BiCMOS sea-of-gates array. 304-311 - Rex T. Baird, Terri S. Fiez:
A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC. 312-320 - Fuji Yang, Christian C. Enz:
A low-distortion BiCMOS seventh-order Bessel filter operating at 2.5 V supply. 321-330 - Behzad Razavi:
A study of phase noise in CMOS oscillators. 331-343 - Ranjit Gharpurey, Robert G. Meyer:
Modeling and analysis of substrate coupling in integrated circuits. 344-353 - Nishath K. Verghese, David J. Allstot, Mark A. Wolfe:
Verification techniques for substrate coupling and their application to mixed-signal IC design. 354-365 - Bernhard E. Boser, Roger T. Howe:
Surface micromachined accelerometers. 366-375 - Mehrdad Heshami, Bruce A. Wooley:
A 250-MHz skewed-clock pipelined data buffer. 376-383 - Huan-Chang Liu, Jonathan S. Min, Henry Samueli:
A low-power baseband receiver IC for frequency-hopped spread spectrum communications. 384-394 - Jeffrey T. Ludwig, S. Hamid Nawab, Anantha P. Chandrakasan:
Low-power digital filtering using approximate processing. 395-400 - Robert Rogenmoser, Qiuting Huang:
An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops. 401-409 - Jorg-Michael Green, Heinrich Klar:
A CMOS gate array architecture for digital signal processing applications. 410-418 - Chris J. Nicol, Alex G. Dickinson:
A scalable pipelined architecture for fast buffer SRAMs. 419-429 - James D. Gallia, Robert J. Landers, Ching-Hao Shaw, Terence G. W. Blake, Wally Banzha:
A flexible gate array architecture for high-speed and high-density applications. 430-436 - John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimal wire sizing and buffer insertion for low power and a generalized delay model. 437-447 - Robert R. Neff, Paul R. Gray, Alberto L. Sangiovanni-Vincentelli
:
A module generator for high-speed CMOS current output digital/analog converters. 448-451 - Kumar Venkat, Liang Chen, Ichiang Lin, Piyush Mistry, Pravin Madhani:
Timing verification of dynamic circuits. 452-455 - Qiuting Huang, Robert Rogenmoser:
Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks. 456-465
Volume 31, Number 4, April 1996
- Behzad Razavi:
A 2.5-Gb/s 15-mW clock recovery circuit. 472-480 - Alfred Felder, Michael Möller, Josef Popp, Josef Böck, Hans-Martin Rein:
46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz static frequency divider in silicon bipolar technology. 481-486 - Satoru Tanoi, Tetsuya Tanabe, Kazuhiko Takahashi, Sanpei Miyamoto, Masaru Uesugi:
A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture. 487-493 - Hideyuki Kabuo, Minoru Okamoto, Isao Tanaka, Hiroyuki Yasoshima, Shinichi Marui, Masayuki Yamasaki, Toshio Sugimura, Katsuhiko Ueda, Toshihlro Ishikawa, Hidetoshi Suzuki, Ryuichi Asahi:
An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor. 494-503 - Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
A 286 MHz 64-b floating point multiplier with enhanced CG operation. 504-513 - Yong Moon, Deog-Kyoon Jeong:
An efficient charge recovery logic circuit. 514-522 - Tadaaki Yamauchi, Yoshikazu Morooka, Hideyuki Ozaki:
A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory. 523-530 - Tomofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, Masakazu Yamashina:
Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI. 531-536 - Katsumi Dosaka, Akira Yamazaki, Naoya Watanabe, Hideaki Abe, Jun Ohtani, Toshiyuki Ogawa, Kazunori Ishihara, Masaki Kumanoya:
A 90-MHz 16-Mb system integrated memory with direct interface to CPU. 537-545 - Masanori Izumikawa, Masakazu Yamashina:
A current direction sense technique for multiport SRAM's. 546-551 - Hiroyuki Mizuno
, Takahiro Nagano:
Driving source-line cell architecture for sub-1-V high-speed low-power applications. 552-557 - Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke
, Yoshiaki Asao:
Fault-tolerant designs for 256 Mb DRAM. 558-566 - Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii:
A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. 567-574 - Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki:
A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. 575-585 - Shigehiro Kuge, Fukashi Morishita
, Takahiro Tsuruda, Shigeki Tomishima
, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto:
SOI-DRAM circuit technologies for low power high speed multigiga scale memories. 586-591 - Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki:
Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs. 592-601 - Ken Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura:
A double-level-Vth select gate array architecture for multilevel NAND flash memories. 602-609
Volume 31, Number 5, May 1996
- Chung-Yu Wu, Heng-Shou Hsu:
The design of CMOS continuous-time VHF current and voltage-mode lowpass filters with Q-enhancement circuits. 614-624 - Eric A. M. Klumperink, Carlo T. Klein, Bas Rüggeberg, Ed J. M. van Tuijl:
AM suppression with low AM-PM conversion with the aid of a variable-gain amplifier. 625-633 - J. Francisco Duque-Carrillo
, Piero Malcovati
, Franco Maloberti, Raquel Pérez-Aloe, Alexander H. Reyes, Edgar Sánchez-Sinencio, Guido Torelli, José M. Valverde:
VERDI: an acoustically programmable and adjustable CMOS mixed-mode signal processor for hearing aid applications. 634-645 - Vladimir Friedman, Kadaba R. Lakshmikumar, David L. Price, Tuan N. Le, Jit Kumar:
A baseband processor for IS-54 cellular telephony. 646-655 - Robert A. Hawley, Bennett C. Wong, Thu-ji Lin, Joe L. Laskowski, Henry Samueli:
Design techniques for silicon compiler implementations of high-speed FIR digital filters. 656-667 - How-Rern Lin, Yu-Chin Hsu, TingTing Hwang:
Cell height driven transistor sizing in a cell based static CMOS module design. 668-676 - Steven J. E. Wilton, Norman P. Jouppi:
CACTI: an enhanced cache access and cycle time model. 677-688 - Kenneth J. Schultz, P. Glenn Gulak:
Fully parallel integrated CAM/RAM using preclassification to enable large capacities. 689-699 - Peter Nilsson, Mats Torkelson:
A monolithic digital clock-generator for on-chip clocking of custom DSP's. 700-706 - Richard X. Gu, Mohamed I. Elmasry:
Power dissipation analysis and optimization of deep submicron CMOS digital circuits. 707-713 - Kevin W. Kobayashi, Donald K. Umemoto, Thomas R. Block, Aaron K. Oki, Dwight C. Streit:
A monolithically integrated HEMT-HBT low noise high linearity variable gain amplifier. 714-718 - Ping-Hsing Lu, Chung-Yu Wu, Ming-Kai Tsai:
Design techniques for VHF/UHF high-Q tunable bandpass filters using simple CMOS inverter-based transresistance amplifiers. 719-725 - Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta:
Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits. 726-731 - Changku Hwang, Mohammed Ismail, Joanne DeGroat:
On-Chip IDDQ testability schemes for detecting multiple faults in CMOS ICs. 732-739 - Rajasekhar Pullela, Uddalak Bhattacharya, Scott T. Allen, Mark J. W. Rodwell:
Multiplexer/demultiplexer IC technology for 100 Gb/s fiber-optic transmission. 740-743 - Patrik Larsson:
High-speed architecture for a programmable frequency divider and a dual-modulus prescaler. 744-748 - Byungsoo Chang, Joonbae Park, Wonchan Kim:
A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops. 749-752 - Edward M. Cherry, Johan H. Huijsing, Rudi G. H. Eschauzier:
Comments on "A 100-MHz 100 dB operational amplifier with multipath nested Miller compensation structure" [and reply]. 753-754
Volume 31, Number 6, June 1996
- Chin-Chieh Chao, Bruce A. Wooley:
A 1.3-ns 32-word×32-bit three-port BiCMOS register file. 758-766 - Toshio Sunaga:
A full bit prefetch DRAM sensing circuit. 767-772 - Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko:
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. 773-783 - Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada:
A GHz MOS adaptive pipeline technique using MOS current-mode logic. 784-791 - Kazuo Yano, Yasuhiko Sasaki, Kunihito Rikino, Koichi Seki:
Top-down pass-transistor logic design. 792-803 - Akilesh Parameswar, Hiroyuki Hara, Takayasu Sakurai:
A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications. 804-809 - Kiniio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko:
A 64-bit carry look ahead adder using pass transistor BiCMOS gates. 810-818 - Tadahiro Kuroda, Tetsuya Fujita, Makato Noda, Yasushi Itabashi, Satohiko Kabumoto, T. S. Wong, Dave Beeson, Dave Gray:
Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability. 819-827 - Gerhard Nebel, Ulrich Kleine, Hans-Jörg Pfleiderer:
Large bandwidth BiCMOS operational amplifiers for SC video applications. 828-834 - Haruhiko Koizumi, Atsushi Noma, Tsuyoshi Tanaka, Kunihiko Kanazawa, Daisuke Ueda:
A GaAs MMIC chip-set for mobile communications using on-chip ferroelectric capacitors. 835-840 - Pius Ng, Poras T. Balsara, Don Steiss:
Performance of CMOS differential circuits. 841-846 - Tetsuro Itakura, Tetsuya Iida:
A feedforward technique with frequency-dependent current mirrors for a low-voltage wideband amplifier. 847-849 - Paul D. Walker, Michael M. Green:
A tunable pulse-shaping filter for use in a nuclear spectrometer system. 850-855 - Yong-Yoong Chai, Louis G. Johnson:
A 2×2 analog memory implemented with a special layout injector. 856-859 - Yoshikazu Kondo, Yuichi Koshiba, Yutaka Arima, Mitsuhiro Murasaki, Tuyoshi Yamada, Hiroyuki Amishiro, Hakuro Mori, Kazuo Kyuma:
A 1.2 GFLOPS neural network chip for high-speed neural network servers. 860-864 - David J. Comer:
A theoretical design basis for minimizing CMOS fixed taper buffer area. 865-868 - Kei-Yong Khoo, Alan Y. Kwentus, Alan N. Willson Jr.:
A programmable FIR digital filter using CSD coefficients. 869-874
Volume 31, Number 7, July 1996
- Ahmadreza Rofougaran, James Y.-C. Chang, Maryam Rofougaran, Asad A. Abidi:
A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver. 880-889 - Jan Craninckx
, Michiel S. J. Steyaert
:
A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS. 890-897 - John B. Hughes, Kenneth W. Moulding, Judith Richardson, John Bennett, William Redman-White, Mark Bracey, Randeep Singh Soin:
Automated design of switched-current filters. 898-907 - Michael Verbeck, Christoph Zimmermann, Horst-Lothar Fiedler:
A MOS switched-capacitor ladder filter in SIMOX technology for high temperature applications up to 300°C. 908-914 - Roberto Gariboldi, Francesco Pulvirenti:
A 70 mΩ intelligent high side switch with full diagnostics. 915-923 - Christoph Kuratli, Qiuting Huang, Alice Biber:
Implementation of high peak-current IGBT gate drive circuits in VLSI compatible BiCMOS technology. 924-932 - Anton Bakker, Johan H. Huijsing:
Micropower CMOS temperature sensor with digital output. 933-937 - Raf Roovers, Michiel S. J. Steyaert
:
A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter. 938-944 - Mark Bracey, William Redman-White, Judith Richardson, John B. Hughes:
A full Nyquist 15 MS/s 8-b differential switched-current A/D converter. 945-951 - Jorgen Christiansen:
An integrated high resolution CMOS timing generator based on an array of delay locked loops. 952-957 - Michel Combes, Karim Dioury, Alain Greiner:
A portable clock multiplier generator using digital CMOS standard cells. 958-965 - Gyudong Kim, Min-Kyu Kim, Byoung-Soo Chang, Wonchan Kim:
A low-voltage, low-power CMOS delay element. 966-971