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"A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS."
Bob Verbruggen et al. (2010)
- Bob Verbruggen, Jan Craninckx
, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits 45(10): 2080-2090 (2010)
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