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ORCIDESSCIRC 2010: Sevilla, Spain
- 36th European Solid-State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, September 13-17, 2010. IEEE 2010, ISBN 978-1-4244-6662-7
- René Penning de Vries, Hans Rijns, Maarten Vertregt:
High performance mixed signal: Business and technology. 1-8 - Peter Ramm, Armin Klumpp, Josef Weber, Nicolas Lietaer, Maaike Taklo, Walter De Raedt
, Thomas Fritzsch, Pascal Couderc:
3D Integration technology: Status and application development. 9-16 - Wentai Liu, Zhi Yang:
Engineering hope with biomimetic microelectronic systems. 17-26 - Yiannos Manoli:
Energy harvesting - from devices to systems. 27-36 - Martin Zander:
Technical and economical trends in wireless applications. 37-44 - Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen, Walter Schwarzenbach, Cécile Moulin:
FDSOI: From substrate to devices and circuit applications. 45-51 - Ullrich R. Pfeiffer, Erik Öjefors:
Terahertz imaging with CMOS/BiCMOS process technologies. 52-60 - Ian A. Young:
Analog mixed-signal circuits in advanced nano-scale CMOS technology for microprocessors and SoCs. 61-70 - David Ruffieux, Matteo Contaldo, Jérémie Chabloz, Christian C. Enz:
Ultra low power and miniaturized MEMS-based radio for BAN and WSN applications. 71-80 - Fabio Sebastiano, Lucien J. Breems, Kofi A. A. Makinwa, Salvatore Drago, Domine Leenaerts, Bram Nauta:
A 65-nm CMOS temperature-compensated mobility-based frequency reference for Wireless Sensor Networks. 102-105 - Toru Tanzawa, Tomoharu Tanaka, Satoru Tamada, Jiro Kishimoto, Sjigekazu Yamada, Koichi Kawai, Takaaki Ichikawa, P. Chiang, Frank Roohparvar:
A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories. 106-109 - Mingoo Seok, Gyouho Kim, David T. Blaauw, Dennis Sylvester:
Variability analysis of a digitally trimmable ultra-low power voltage reference. 110-113 - Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa:
A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities. 114-117 - Alexandre Huffenus, Gaël Pillonnet, Nacer Abouchi, Frédéric Goutti, Vincent Rabary, Robert Cittadini:
A high PSRR Class-D audio amplifier IC based on a self-adjusting voltage reference. 118-121 - Matteo Perenzoni, Daniel Mosconi, David Stoppa:
A 160×120-pixel uncooled IR-FPA readout integrated circuit with on-chip non-uniformity compensation. 122-125 - Fang Tang, Yuan Cao, Amine Bermak:
An ultra-low power current-mode CMOS image sensor with energy harvesting capability. 126-129 - Daniel Durini, Frank Matheis, Christian Nitta, Werner Brockherde, Bedrich J. Hosticka:
Large full-well capacity stitched CMOS image sensor for high temperature applications. 130-133 - Juan A. Leñero-Bardallo, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
A 100dB dynamic range event-driven spatial contrast sensor with 100μs response time and Time-to-First-Spike mode. 134-137 - Nicola Massari, Marco De Nicola, Massimo Gottardi:
A 30µW 100dB contrast vision sensor with sync-async readout and data compression. 138-141 - Calogero Marco Ippolito, Alessandro Italia, Giuseppe Palmisano:
A 1.7-mW dual-band CMOS frequency synthesizer for low data-rate sub-GHz applications. 142-145 - Pietro Andreani, Kirill Kozmin, Per Sandrup, Thomas Mattsson:
A transmitter CMOS VCO for WCDMA/EDGE. 146-149 - Andrea Bevilacqua, Leonardo Lorenzon, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani:
A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS. 150-153 - Shih-Hao Tarng, Jia-Hung Peng, Tzu-Chan Chueh, Ming-Ching Kuo:
An automatic frequency calibration technique for fractional-N frequency synthesizers. 154-157 - Gabriele Devita, Alan Chi Wai Wong, Nick Kasparidis, P. Corbishley, Alison J. Burdett, Paul Paddan:
A 0.9mW PLL integrated in an ultra-low-power SoC for WPAN and WBAN applications. 158-161 - Siva V. Thyagarajan, Shanthi Pavan, Prabu Sankar:
Low distortion active filters using the Gm-assisted OTA-RC technique. 162-165 - Huy-Hieu Nguyen, Hoai-Nam Nguyen, Jeong-Seon Lee, Sang-Gug Lee:
A high-linearity low-noise reconfiguration-based programmable gain amplifier. 166-169 - Qinwen Fan, Fabio Sebastiano, Johan H. Huijsing, Kofi A. A. Makinwa:
A 1.8µW 1µV-offset capacitively-coupled chopper instrumentation amplifier in 65nm CMOS. 170-173 - Armin Tajalli, Yusuf Leblebici:
Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution. 174-177 - Takamoto Watanabe, Tomohito Terasawa:
An all-digital A/D converter TAD with 4-shift-clock construction for sensor interface in 0.65-μm CMOS. 178-181 - Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. 182-185 - Nobuhiro Shiramizu, Akihiro Nakamura, Takahiro Nakamura, Toru Masuda, Katsuyoshi Washio:
Low-power fully-integrated K-band transceiver using transformer direct-stacking/connecting and balun signal-combining techniques. 186-189 - Hugo Veenstra, Marc Notten, Dixian Zhao, John R. Long:
A 45-67GHz UWB transmitter with >8dBm output power for indoor radar applications. 190-193 - Jinshu Zhao, Marcus Hellfeld, Thomas Wolf, Frank Ellinger, Le Ye:
A 17-tap 3.5 Gbps finite impulse response pulse shaping filter for 60 GHz transmitter with QPSK modulation. 194-197 - Sanu Mathew, Michael E. Kounavis, Farhana Sheikh, Steven Hsu, Amit Agarwal, Himanshu Kaul, Mark A. Anders, Frank L. Berry, Ram Krishnamurthy:
3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS. 198-201 - Luca Henzen, Wolfgang Fichtner:
FPGA parallel-pipelined AES-GCM core for 100G Ethernet applications. 202-205 - Jen-Wei Lee, Yao-Lin Chen, Chih-Yeh Tseng, Hsie-Chia Chang, Chen-Yi Lee:
A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance. 206-209 - Rajaraman Ramanarayanan, Sanu Mathew, Farhana Sheikh, Suresh Srinivasan, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Vasantha Erraguntla, Ram Krishnamurthy:
18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS. 210-213 - Pieter Harpe, Cui Zhou, Xiaoyan Wang, Guido Dolmans, Harmke de Groot:
A 12fJ/conversion-step 8bit 10MS/s asynchronous SAR ADC for low energy radios. 214-217 - Sai-Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi-Hang Chan, U. Fat Chio, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. 218-221 - Jen-Hung Chi, Shih-Hsuan Chu, Tsung-Heng Tsai:
A 1.8-V 12-bit 250-MS/s 25-mW self-calibrated DAC. 222-225 - Andrea Baschirotto, Giacomino Bollati, Vittorio Colonna, Gabriele Gandolfi:
A 94dB-SNR -76dB-THD high-efficiency hybrid audio power-DAC for loudspeaker (4Ω/8Ω) and earphone (16Ω/32Ω). 226-229 - Chun-Yu Hsieh, Chih-Yu Yang, Fu-Kuei Feng, Ke-Horng Chen:
A photovoltaic system with an analog maximum power point tracking technique for 97.3% high effectiveness. 230-233 - Hannes Reinisch, Stefan Gruber, Martin Wiessflecker, Hartwig Unterassinger, Günter Hofer, Wolfgang Pribyl, Gerald Holweg:
An electro-magnetic energy harvester with 190nW idle mode power consumption for wireless sensor nodes. 234-237 - Andres Tamez, Jeffrey A. Fredenburg, Michael P. Flynn:
An integrated 120 volt AC mains voltage interface in standard 130 nm CMOS. 238-241 - Armin Tajalli, Yusuf Leblebici:
A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems. 242-245 - Lianming Li, Patrick Reynaert, Michiel Steyaert:
A 60GHz 15.7mW static frequency divider in 90nm CMOS. 246-249 - José Luis González, Xavier Aragonès, Marc Molina, Baudouin Martineau, Didier Belot:
A comparison between grounded and floating shield inductors for mmW VCOs. 250-253 - Bertrand Parvais, Karen Scheir, Vojkan Vidojkovic, R. Vandebriel, Gerd Vandersteen, Charlotte Soens, Piet Wambacq:
A 40 nm LP CMOS PLL for high-speed mm-wave communication. 254-257 - David Murphy, Qun Jane Gu, Yi-Cheng Wu, Heng-Yu Jian, Zhiwei Xu, Adrian Tang, Frank Wang, Yu-Ling Lin, Ho-Hsian Chen, Chewnpu Jou, Mau-Chung Frank Chang:
A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX. 258-261 - Marco Zanuso, Salvatore Levantino, Alberto Puggelli, Carlo Samori, Andrea L. Lacaita:
Time-to-digital converter with 3-ps resolution and digital linearization algorithm. 262-265 - Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Time-to-digital converter based on time difference amplifier with non-linearity calibration. 266-269 - Ping-Ying Wang, Chia-Huang Fu:
All digital modulation bandwidth extension technique for narrow bandwidth analog fractional-N PLL. 270-273 - Lim Joonhyung, Lee Kwangmook, Cho Koonsik:
Ultra low power RC oscillator for system wake-up using highly precise auto-calibration technique. 274-277 - Christophe De Roover, Michiel Steyaert:
A 500 mV 650 pW random number generator in 130 nm CMOS for a UWB localization system. 278-281 - Kamran Souri, Kofi A. A. Makinwa:
A 0.12mm2 7.4μW micropower temperature sensor with an inaccuracy of ±0.2°C (3σ) from -30°C to 125°C. 282-285 - Lasse Aaltonen, Antti Kalanti, Mika Pulkkinen, Matti Paavola, Mika Kämäräinen, Kari Halonen:
A 4.3 mm2 ASIC for a 300 °/s 2-axis capacitive micro-gyroscope. 286-289 - Mohammad Reza Nabavi, Michiel A. P. Pertijs, Stoyan N. Nihtianov:
An interface for eddy current displacement sensors with 15-bit resolution and 20 MHz excitation. 290-293 - Matteo Perenzoni, Nicola Massari, David Stoppa, Lucio Pancheri, Mattia Malfatti, Lorenzo Gonzo:
A 160×120-pixels range camera with on-pixel correlated double sampling and nonuniformity correction in 29.1µm pitch. 294-297 - Milos Davidovic, Gerald Zach, Kerstin Schneider-Hornstein, Horst Zimmermann:
Range finding sensor in 90nm CMOS with bridge correlator based background light suppression. 298-301 - Ercan Kaymaksut, Patrick Reynaert:
A 2.4 GHz fully integrated Doherty power amplifier using series combining transformer. 302-305 - Hongtao Xu, Yorgos Palaskas, Ashoke Ravi, Krishnamurthy Soumyanath:
A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application. 306-309 - Jonas Fritzin, Christer Svensson, Atila Alvandpour:
A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS. 310-313 - Ying He, Lianming Li, Patrick Reynaert:
60GHz power amplifier with distributed active transformer and local feedback. 314-317 - Ben Johnson, David DeTomaso, Alyosha C. Molnar:
A low-power orthogonal current-reuse amplifier for parallel sensing applications. 318-321 - Antonio J. López-Martín, José María Algueta-Miguel, Lucía Acosta, Ramón González Carvajal, Jaime Ramírez-Angulo:
200 μW CMOS class AB unity-gain buffers with accurate quiescent current control. 322-325 - Joselyn Torres, Adrian Colli-Menchi, Miguel Angel Rojas González, Edgar Sánchez-Sinencio:
A 470μW clock-free current-controlled class D amplifier with 0.02% THD+N and 82dB PSRR. 326-329 - Andrea Bonfanti, M. Ceravolo, Guido Zambra, Riccardo Gusmeroli, Tommaso Borghi, Alessandro S. Spinelli, Andrea L. Lacaita:
A multi-channel low-power IC for neural spike recording with data compression and narrowband 400-MHz MC-FSK wireless transmission. 330-333 - Yu M. Chi, Gert Cauwenberghs:
Micropower integrated bioamplifier and auto-ranging ADC for wireless and implantable medical instrumentation. 334-337 - Xiao Liu, Andreas Demosthenous, Nick Donaldson:
A DC-isolated fine-controlled neural stimulator. 338-341 - Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa:
A 24 dB gain 51-68 GHz CMOS low noise amplifier using asymmetric-layout transistors. 342-345 - Andreas Axholt, Henrik Sjöland:
A 24-GHz 90-nm CMOS beamforming receiver front-end with analog baseband phase rotation. 346-349 - Piet Wambacq, Vito Giannini, Karen Scheir, Wim Van Thillo, Yves Rolain:
A fifth-order 880MHz/1.76GHz active lowpass filter for 60GHz communications in 40nm digital CMOS. 350-353 - Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara:
0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. 354-357 - Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene:
A 4.4pJ/access 80MHz, 2K word } 64b memory with write masking feature and variability resilient multi-sized sense amplifier redundancy for wireless sensor nodes applications. 358-361 - Brice Lhomme, Yann Carminati, Bertrand Borot, Olivier Callen, Thierry Burdeau, Sylvain Clerc:
A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter. 362-365 - Gregory K. Chen, Michael Wieckowski, David T. Blaauw, Dennis Sylvester:
Crosshairs SRAM - An adaptive memory for mitigating parametric failures. 366-369 - Timmy Sundström, Christer Svensson, Atila Alvandpour:
A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS. 370-373 - Jürg Treichler, Qiuting Huang:
A 11.1-bit ENOB 50-MS/s pipelined A/D converter in 130-nm CMOS without S/H front end. 374-377 - Justin Kyung-Ryun Kim, Boris Murmann:
A 12-bit, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration. 378-381 - Mohammad Taherzadeh-Sani, Anas A. Hamoui:
A reconfigurable 10-12b 0.4-44MS/s pipelined ADC with 0.35-0.5pJ/step in 1.2V 90nm digital CMOS. 382-385 - Oscar Alonso, Joan Canals, Lluis Freixas, Josep Samitier, Ángel Diéguez, Monica Vatteroni, Ekawahyu Susilo, Carmen Cavallotti, Pietro Valdastri:
Enabling multiple robotic functions in an endoscopic capsule for the entire gastrointestinal tract exploration. 386-389 - Alexander Frey, P. Kruppa, Ingo Kuehne, Meinrad Schienle, N. Persike, Gerhard Hartwich, Helmut Seidel:
Digital potentiostat for electrochemical bio sensor chips. 390-393 - Jens Anders, Paul SanGiorgio, Giovanni Boero:
A quadrature receiver for μNMR applications in 0.13μm CMOS. 394-397 - Nitz Saputra, John R. Long, John J. Pekarik:
A 900μW, 3-5GHz integrated FM-UWB transmitter in 90nm CMOS. 398-401 - Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Vito Giannini, Jan Craninckx:
A sub-3dB NF voltage-sampling front-end with +18dBm IIP3 and +2dBm blocker compression point. 402-405 - Xiao Wang, Wolfgang Aichholzer, Johannes Sturm:
A 0.1-4GHz resistive feedback LNA with feedforward noise and distortion cancelation. 406-409 - Florian Chouard, Michael Fulde, Doris Schmitt-Landsiedel:
Reliability assessment of voltage controlled oscillators in 32nm high-κ metal gate technology. 410-413 - Thomas Christen, Qiuting Huang:
A 0.13µm CMOS 0.1-20MHz bandwidth 86-70dB DR multi-mode DT ΔΣ ADC for IMT-Advanced. 414-417 - Alonso Morgado, Rocío del Río, José M. de la Rosa, Lynn Bos, Julien Ryckaert, Geert Van der Plas:
A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS. 418-421 - Kerry A. O'Donoghue, Paul J. Hurst, Stephen H. Lewis:
A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR. 422-425 - Jens Sauerbrey, Jacinto San Pablo Garcia, Georgi Panov, Thomas Piorek, Xianghua Shen, Markus Schimper, Rudolf Koch, Matthias Keller, Yiannos Manoli, Maurits Ortmanns:
A configurable cascaded continuous-time ΔΣ modulator with up to 15MHz bandwidth. 426-429 - Enrique Prefasi, Susana Patón, Luis Hernández, Richard Gaggl, Andreas Wiesbauer, Jörg Hauptmann:
A 0.08 mm2, 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS. 430-433 - Tom Van Breussegem, Michiel Steyaert:
A fully integrated 74% efficiency 3.6V to 1.5V 150mW capacitive point-of-load DC/DC-converter. 434-437 - Stefano Michelis, Bruno Allongue, G. Blanchot, Simone Buso, Federico Faccio, Cristian Fuentes, Alessandro Marchioro, Stefano Orlandi, Stefano Saggini, Giorgio Spiazzi, Maher Kayal:
An 8W-2MHz buck converter with adaptive dead time tolerant to radiation and high magnetic field. 438-441 - Gerhard Maderbacher, Thomas Jackum, Wolfgang Pribyl, Christoph Sandner:
A sensor concept for minimizing body diode conduction losses in DC/DC converters. 442-445 - Yu-Huei Lee, Ming-Hsin Huang, Yu-Nong Tsai, Ming-Yan Fan, Ke-Horng Chen:
A single-inductor multiple positive and negative outputs (SIMPNO) converter with a vector current control mode for electronic paper displays (EPDs). 446-449 - Se-Won Wang, Young-Jin Woo, Young-Sub Yuk, Byunghun Lee, Gyu-Hyeong Cho, Gyu-Ha Cho:
Efficiency enhanced Single-Inductor Boost-Inverting Flyback converter with Dual Hybrid Energy transfer media and a Bifurcation Free Comparator. 450-453 - Kyoohyun Lim, Sunki Min, Sanghoon Lee, Jaewoo Park, Kisub Kang, Hwahyeong Shin, Hyunchul Shim, Sechang Oh, Sungho Kim, Jong-Ryul Lee, Changsik Yoo, Kukjin Chun:
A 2×2 MIMO tri-band dual-mode CMOS transceiver for worldwide WiMAX/WLAN applications. 454-457 - Paulo Augusto Dal Fabbro, Tindaro Pittorino, Christoph Kuratli, Robert Kvacek, Martin Kucera, Frédéric Giroud, Steve Tanner, Frédéric Chastellain, Arnaud Casagrande, Arthur Descombes, Vincent Peiris, Pierre-André Farine, Maher Kayal:
A 0.8V 2.4GHz 1Mb/s GFSK RF transceiver with on-chip DC-DC converter in a standard 0.18µm CMOS technology. 458-461 - Maja Vidojkovic, Simonetta Rampu, Koji Imamura, Pieter Harpe, Guido Dolmans, Harmke de Groot:
A 500mW 5Mbps ULP super-regenerative RF front-end. 462-465 - Masahiro Hosoya, Toshiya Mitomo, Osamu Watanabe:
A 900-MHz bandwidth analog baseband circuit with 1-dB step and 30-dB gain dynamic range. 466-469 - J. C. Hsu, C. Y. Chou, S. W. Chang, Albert Tseng:
A low-cost and low-power single-chip DAB+/DAB/FM receiver. 470-473 - Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara:
0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits. 474-477 - Glen Rosendale, Sohrab Kianian, Monte Manning, Darlene Hamilton, Henry Huang, Karl Robinson, Young Weon Kim, Thomas Rueckes:
A 4 Megabit Carbon Nanotube-based nonvolatile memory (NRAM). 478-481 - Jong-Pil Son, Jin Ho Kim, Woo Song Ahn, Seung Uk Han, Byung-Sick Moon, Churoo Park, Hong-Sun Hwang, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Soo-Won Kim:
A highly reliable multi-cell antifuse scheme using DRAM cell capacitors. 482-485 - Erik Öjefors, Neda Baktash, Yan Zhao, Richard Al Hadi, Hani Sherry, Ullrich R. Pfeiffer:
Terahertz imaging detectors in a 65-nm CMOS SOI technology. 486-489 - André Augusto Mariano, Thierry Taris, Bernardo Leite, Cédric Majek, Yann Deval, Eric Kerherve, Jean-Baptiste Bégueret, Didier Belot:
Low power and high gain double-balanced mixer dedicated to 77 GHz automotive radar applications. 490-493 - Roc Berenguer, Gui Liu, Abe Akhiyat, Keya Kamtikar, Yang Xu:
A 117mW 77GHz receiver in 65nm CMOS with ladder structured tunable VCO. 494-497 - Silvia Soldà, Michele Caruso, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig, Andrea Neviani:
A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request. 498-501 - Gilles Masson, Dominique Morche, Hélène Jacquinot, Pierre Vincent, François Dehmas, Stéphane Paquelet, Alexis Bisiaux, Olivier Fourquin, Jean Gaubert, Sylvain Bourdel:
A 1 nJ/b 3.2-to-4.7 GHz UWB 50 Mpulses/s double quadrature receiver for communication and localization. 502-505 - Muhammad Anis, Maurits Ortmanns, Norbert Wehn:
RF spectrum sensing technique for cognitive UWB radio network. 506-509 - Hagen Marien, Michiel Steyaert, Soeren Steudel, Peter Vicca, Steve Smout, Gerwin H. Gelinck, Paul Heremans:
An organic integrated capacitive DC-DC up-converter. 510-513 - Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu, Chien-Cheng Chen:
A loading effect insensitive and high precision clock synchronization circuit. 514-517 - Dina Kamel, Cédric Hocquet, François-Xavier Standaert, Denis Flandre, David Bol:
Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits. 518-521 - David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat:
The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic. 522-525 - Joyce Kwong, Anantha P. Chandrakasan:
An energy-efficient biomedical signal processing platform. 526-529 - Christoph Studer, Schekeb Fateh, Dominik Seethaler:
A 757Mb/s 1.5 mm2 90nm CMOS soft-input soft-output MIMO detector for IEEE 802.11n. 530-533 - Yen-Liang Chen, Ting-Jyun Jheng, Cheng-Zhou Zhan, An-Yeu Wu:
A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system. 534-537 - Hans Jürgen Mattausch, Wataru Imafuku, Tania Ansari, Akio Kawabata, Tetsushi Koide:
Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping. 538-541 - Filip Tavernier, Michiel Steyaert:
A 5.5 Gbit/s optical receiver in 130 nm CMOS with speed-enhanced integrated photodiode. 542-545 - Yu-Chang Tsai, Kuo-Hsing Cheng, Yen-Hsueh Wu, Ying-Fu Lin:
A CMOS adaptive equalizer using low-voltage zero generators technique. 546-549 - Mahyar Kargar, Michael M. Green:
A 10 Gb/s adaptive analog decision feedback equalizer for multimode fiber dispersion compensation in 0.13 µm CMOS. 550-553 - Francisco Aznar, Santiago Celma, Belén Calvo:
A 0.18-µm CMOS 1.25-Gbps front-end receiver for low-cost short reach optical communications. 554-557
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