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ORCIDISSCC 2017: San Francisco, CA, USA
- 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017. IEEE 2017, ISBN 978-1-5090-3758-2
- Laura Chizuko Fujino:
Reflections. 4 - Boris Murmann
:
Foreword: Intelligent Chips for a Smart World. 5 - Anantha P. Chandrakasan, Boris Murmann:
Session 1 overview: Plenary Session. 6-7 - Cliff Hou:
1.1 A smart design paradigm for smart chips. 8-13 - Ahmad Bahai:
1.2 Dynamics of exponentials in circuits and systems. 14-20 - Jonathan Rothberg:
1.3 The development of high-speed DNA sequencing: Jurassic Park, Neanderthal, Moore, and you. 23 - Lieven M. K. Vandersypen, Antoni van Leeuwenhoek:
1.4 Quantum computing - the next challenge in circuit and system design. 24-29 - Kohei Onizuka, Abbas Komijani, Piet Wambacq:
Session 2 overview: Power amplifiers. 30-31 - Song Hu, Fei Wang, Hua Wang:
2.1 A 28GHz/37GHz/39GHz multiband linear Doherty power amplifier for 5G massive MIMO applications. 32-33 - Debopriyo Chowdhury, Sraavan R. Mundlapudi, Ali Afsahi:
2.2 A fully integrated reconfigurable wideband envelope-tracking SoC for high-bandwidth WLAN applications in a 28nm CMOS technology. 34-35 - Shang-Hsien Yang, Yen-Ting Lin, Yu-Sheng Ma, Hung-Wei Chen, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
2.3 A single-inductor dual-output converter with linear-amplifier-driven cross regulation for prioritized energy-distribution control of envelope-tracking supply modulator. 36-37 - Xun Liu, Heng Zhang, Min Zhao, Xuan Chen, Philip K. T. Mok, Howard C. Luong:
2.4 A 2.4V 23.9dBm 35.7%-PAE -32.1dBc-ACLR LTE-20MHz envelope-shaping-and-tracking system with a multiloop-controlled AC-coupling supply modulator and a mode-switching PA. 38-39 - Jenwei Ko, Xiaochuan Guo, Changhua Cao, Saravanan Rajapandian, Solti Peng, Jing Li, Wenchang Lee, Narayanan Baskaran, Caiyi Wang:
2.5 A high-efficiency multiband Class-F power amplifier in 0.153µm bulk CMOS for WCDMA/LTE applications. 40-41 - Junlei Zhao, Elham Rahimi, Francesco Svelto, Andrea Mazzanti:
2.6 A SiGe BiCMOS E-band power amplifier with 22% PAE at 18dBm OP1dB and 8.5% at 6dB back-off leveraging current clamping in a common-base stage. 42-43 - Sherif Shakib, Mohamed Elkholy, Jeremy Dunworth, Vladimir Aparin, Kamran Entesari:
2.7 A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS. 44-45 - Voravit Vorapipat, Cooper S. Levy, Peter M. Asbeck:
2.8 A Class-G voltage-mode Doherty power amplifier. 46-47 - Thomas Burd, James Myers, Byeong-Gyu Nam:
Session 3 overview: Digital processors. 48-49 - Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam, Juergen Pille, Donald W. Plass:
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. 50-51 - Teja Singh, Sundar Rangarajan, Deepesh John, Carson Henrion, Shane Southard, Hugh McIntyre, Amy Novak, Stephen Kosonocky, Ravi Jotwani, Alex Schaefer, Edward Chang, Joshua Bell, Michael Co:
3.2 Zen: A next-generation high-performance ×86 core. 52-53 - David Greenhill, Ron Ho, David M. Lewis, Herman Schmit, Kok Hong Chan, Andy Tong, Sean Atsatt, Dana How, Peter McElheny, Keith Duwel, Jeffrey Schulz, Darren Faulkner, Gopal Iyer, George Chen, Hee Kong Phoon, Han Wooi Lim, Wei-Yee Koay, Ty Garibay:
3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration. 54-55 - Hugh Mair, Ericbill Wang, Alice Wang, Ping Kao, Yuwen Tsai, Sumanth Gururajarao, Rolf Lagerquist, Jin Son, Gordon Gammie, Gordon Lin, Achuta Thippana, Kent Li, Manzur Rahman, Wuan Kuo, David Yen, Yi-Chang Zhuang, Ue Fu, Hung-Wei Wang, Mark Peng, Cheng-Yuh Wu, Taner Dosluoglu, Anatoly Gelman, Daniel Dia, Girishankar Gurumurthy, Tony Hsieh, W. X. Lin, Ray Tzeng, Jengding Wu, C. H. Wang, Uming Ko:
3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance. 56-57 - Hayato Kimura, Hideyuki Noda, Hisaaki Watanabe, Takashi Higuchi, Ryosaku Kobayashi, Masayuki Utsuno, Fumitake Takami, Sugako Otani, Masayuki Ito, Yasuhisa Shimazaki, Naoki Yada, Hiroyuki Kondo:
3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV. 58-59 - Hemanth Prabhu, Joachim Neves Rodrigues, Liang Liu, Ove Edfors:
3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI. 60-61 - Ziyun Li, Qing Dong, Mehdi Saligane, Benjamin P. Kempke, Shijia Yang, Zhengya Zhang, Ronald G. Dreslinski, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim:
3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation. 62-63 - Hayato Wakabayashi, Jun Deguchi, Makoto Ikeda:
Session 4 overview: Imagers. 64-65 - Bongki Son, Yunjae Suh, Sungho Kim, Heejae Jung, Jun-Seok Kim, Chang-Woo Shin, Keunju Park, Kyoobin Lee, Jin Man Park, Jooyeon Woo, Yohan Roh, Hyunku Lee, Yibing Michelle Wang, Ilia A. Ovsiannikov, Hyunsurk Ryu:
4.1 A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representation. 66-67 - Arjang Hassibi, Rituraj Singh, Arun Manickam, Ruma Sinha, Bob Kuimelis, Sara Bolouki, Pejman Naraghi-Arani, Kirsten A. Johnson, Mark W. McDermott, Nicholas Wood, Piyush Savalia, Nader Gamini:
4.2 A fully integrated CMOS fluorescence biochip for multiplex polymerase chain-reaction (PCR) processes. 68-69 - Min-Woong Seo, Yuya Shirakawa, Yuriko Masuda, Yoshimasa Kawata, Keiichiro Kagawa, Keita Yasutomi, Shoji Kawahito:
4.3 A programmable sub-nanosecond time-gated 4-tap lock-in pixel CMOS image sensor for real-time fluorescence lifetime imaging microscopy. 70-71 - Wootaek Lim, Dennis Sylvester, David T. Blaauw:
4.4 A sub-nW 80mlx-to-1.26Mlx self-referencing light-to-digital converter with AlGaAs photodiode. 72-73 - Masahiro Kobayashi, Yusuke Onuki, Kazunari Kawabata, Hiroshi Sekine, Toshiki Tsuboi, Yasushi Matsuno, Hidekazu Takahashi, Toru Koizumi, Katsuhito Sakurai, Hiroshi Yuzurihara, Shunsuke Inoue, Takeshi Ichikawa:
4.5 A 1.8erms- temporal noise over 110dB dynamic range 3.4µm pixel pitch global shutter CMOS image sensor with dual-gain amplifiers, SS-ADC and multiple-accumulation shutter. 74-75 - Tsutomu Haruta, Tsutomu Nakajima, Jun Hashizume, Taku Umebayashi, Hiroshi Takahashi, Kazuo Taniguchi, Masami Kuroda, Hiroshi Sumihiro, Koji Enoki, Takatsugu Yamasaki, Katsuya Ikezawa, Atsushi Kitahara, Masao Zen, Masafumi Oyama, Hiroki Koga, Hidenobu Tsugawa, Tomoharu Ogita, Takashi Nagano, Satoshi Takano, Tetsuo Nomoto:
4.6 A 1/2.3inch 20Mpixel 3-layer stacked CMOS Image Sensor with DRAM. 76-77 - Shin'ichi Machida, Sanshiro Shishido, Takeyoshi Tokuhara, Masaaki Yanagida, Takayoshi Yamada, Masumi Izuchi, Yoshiaki Sato, Yasuo Miyake, Manabu Nakata, Masashi Murakami, Mitsuru Harada, Yasunori Inoue:
4.7 A 2.1Mpixel organic-film stacked RGB-IR image sensor with electrically controllable IR sensitivity. 78-79 - Min-Woong Seo, Tongxi Wang, Sung-Wook Jun, Tomoyuki Akahori, Shoji Kawahito:
4.8 A 0.44e-rms read-noise 32fps 0.5Mpixel high-sensitivity RG-less-pixel CMOS image sensor using bootstrapping reset. 80-81 - Tomohiro Yamazaki, Hironobu Katayama, Shuji Uehara, Atsushi Nose, Masatsugu Kobayashi, Sayaka Shida, Masaki Odahara, Kenichi Takamiya, Yasuaki Hisamatsu, Shizunori Matsumoto, Leo Miyashita, Yoshihiro Watanabe, Takashi Izawa, Yoshinori Muramatsu, Masatoshi Ishikawa:
4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing. 82-83 - Tim Piessens, Vadim Ivanov, Axel Thomsen:
Session 5 overview: Analog techniques. 84-85 - Fred Mostert, Daniël Schinkel, Wouter Groothedde, Lucien J. Breems, Remko van Heeswijk, Marto-Jan Koerts, Eric van Iersel, Daniel Groeneveld, Gertjan van Holland, Patrick Zeelen, Derk-Jan Hissink, Martin Pos, Paul Wielage, Fre Jorritsma, Marc Klein Middelink:
5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter. 86-87 - Ji-Hun Lee, Jun-Suk Bang, Kiduk Kim, Hui-Dong Gwon, Sang-Hui Park, Yeunhee Huh, Kye-Seok Yoon, Jong-Beom Baek, Yong-Min Ju, Gibbeum Lee, Homin Park, Hyeon-Min Bae, Gyu-Hyeong Cho:
5.2 An 8Ω 10W 91%-power-efficiency 0.0023%-THD+N multi-level Class-D audio amplifier with folded PWM. 88-89 - Ming Ding, Yao-Hong Liu, Yan Zhang, Chuang Lu, Peng Zhang, Benjamin Busze, Christian Bachmann, Kathleen Philips:
5.3 A 95µW 24MHz digitally controlled crystal oscillator for IoT applications with 36nJ start-up energy and >13× start-up time reduction using a fully-autonomous dynamically-adjusted load. 90-91 - Karthik Pappu, George Pieter Reitsma, Sumant Bapat:
5.4 Frequency-locked-loop ring oscillator with 3ns peak-to-peak accumulated jitter in 1ms time window for high-resolution frequency counting. 92-93 - Jahyun Koo, Kyoung-Sik Moon, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop. 94-95 - Anand Savanth, James Myers, Alex S. Weddell, David Flynn, Bashir M. Al-Hashimi:
5.6 A 0.68nW/kHz supply-independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C stability. 96-97 - Hanqing Wang, Gerard Mora-Puchalt, Colin Lyden, Roberto Maurino, Christian Birk:
5.7 A 19nV/√Hz-noise 2µV-offset 75µA low-drift capacitive-gain amplifier with switched-capacitor ADC driving capability. 98-99 - Youngwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit. 100-101 - Ying-Chih Hsu, Chia-Liang Tai, Mei-Chen Chuang, Alan Roth, Eric G. Soenen:
5.9 An 18.75µW dynamic-distributing-bias temperature sensor with 0.87°C(3σ) untrimmed inaccuracy and 0.00946mm2 area. 102-103 - Weiwei Xu, Prasanna Upadhyaya, Xiaoyue Wang, Randy Tsang, Li Lin:
5.10 A 1A LDO regulator driven by a 0.0013mm2 Class-D controller. 104-105 - Fan Yang, Philip K. T. Mok:
5.11 A 65nm inverter-based low-dropout regulator with rail-to-rail regulation and over -20dB PSR at 0.2V lowest supply voltage. 106-107 - Simone Erba, Takayuki Shibasaki, Frank O'Mahony:
Session 6 overview: Ultra-high-speed wireline. 108-109 - Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, Jri Lee:
6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS. 110-111 - Jaeduk Han, Yue Lu, Nicholas Sutardja, Elad Alon:
6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology. 112-113 - Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang:
6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET. 114-115 - Giovanni Steffan, Emanuele Depaoli, Enrico Monaco, Nicolo Sabatino, Walter Audoglio, Augusto Andrea Rossi, Simone Erba, Matteo Bassi, Andrea Mazzanti:
6.4 A 64Gb/s PAM-4 transmitter with 4-Tap FFE and 2.26pJ/b energy efficiency in 28nm CMOS FDSOI. 116-117 - Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli:
6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS. 118-119 - Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi:
6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS. 120-121 - Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi:
6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance. 122-123 - Yuu Watanabe, Danielle Griffith, Aarno Pärssinen:
Session 7 overview: Wireless transceivers. 124-125 - Tsung-Ming Chen, Yi Lu, Pang-Ning Chen, Yu-Hsien Chang, Ming-Chung Liu, Po-Yu Chang, Chia-Jen Liang, Yi-Chu Chen, Hsi-Liang Lu, Jian-Yu Ding, Chin-Chung Wang, YuLi Hsueh, Jen-Che Tsai, Min-Shun Hsu, Yuan-Hung Chung, George Chien:
7.1 An 802.11ac dual-band reconfigurable transceiver supporting up to four VHT80 spatial streams with 116fsrms-jitter frequency synthesizer and integrated LNA/PA delivering 256QAM 19dBm per stream achieving 1.733Gb/s PHY rate. 126-127 - Bodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Daniel J. Friedman, Alberto Valdes-Garcia:
7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication. 128-129 - Chinq-Shiun Chiu, Shih-Chieh Yen, Chi-Yao Yu, Tzung-Han Wu, Chung-Yun Chou, Sheng-Che Tseng, Chih-Hsien Shen, Yu-Tsung Lu, Hsinhung Chen, Song-Yu Yang, Yen-Tso Chen, Guang-Kaai Dehng, Yangjian Chen, Christophe Beghein, Dimitris Nalbantis, Manel Collados, Bernard Tenbroek, Jonathan Strange, Caiyi Wang:
7.3 A 40nm low-power transceiver for LTE-A Carrier Aggregation. 130-131 - Li-Xuan Chuo, Yao Shi, Zhihong Luo, Nikolaos Chiotellis, Zhiyoong Foo, Gyouho Kim, Yejoong Kim, Anthony Grbic, David D. Wentzloff, Hun-Seok Kim, David T. Blaauw:
7.4 A 915MHz asymmetric radio using Q-enhanced amplifier for a fully integrated 3×3×3mm3 wireless sensor node with 20m non-line-of-sight communication. 132-133 - David Lachartre, Francois Dehmas, Carolynn Bernier, Christophe Fourtet, Laurent Ouvry, Florent Lepin, Eric Mercier, Steve Hamard, Lionel Zirphile, Sébastien Thuries, Fabrice Chaix:
7.5 A TCXO-less 100Hz-minimum-bandwidth transceiver for ultra-narrow-band sub-GHz IoT cellular networks. 134-135 - Wei Yang, De Yong Hu, Chun Kit Lam, Ji Qing Cui, Lip Kai Soh, De-Cheng Song, Xiao Wei Zhong, Hon Cheong Hor, Chee Lee Heng:
7.6 A +8dBm BLE/BT transceiver with automatically calibrated integrated RF bandpass filter and -58dBc TX HD2. 136-137 - Nikolaj Andersen, Kristian Granhaug, Jørgen Andreas Michaelsen, Sumit Bagga, Håkon A. Hjortland, Mats Risopatron Knutsen, Tor Sverre Lande, Dag T. Wisland:
7.7 A 118mW 23.3GS/s dual-band 7.3GHz and 8.7GHz impulse-based direct RF sampling radar SoC in 55nm CMOS. 138-139 - Yasuhisa Shimazaki, John Maneatis, Edith Beigné:
Session 8 overview: Digital PLLs and security circuits. 140-141 - Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator. 142-143 - Eunhwan Kim, Minah Lee, Jae-Joon Kim:
8.2 8Mb/s 28Mb/mJ robust true-random-number generator in 65nm CMOS based on differential ring oscillator with feedback resistors. 144-145 - Kaiyuan Yang, Qing Dong, David T. Blaauw, Dennis Sylvester:
8.3 A 553F2 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instability. 146-147 - Tae-Kwang Jang, Seokhyeon Jeong, Dongsuk Jeon, Kyojin David Choo, Dennis Sylvester, David T. Blaauw:
8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment. 148-149 - Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa:
8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. 150-151 - Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu:
8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. 152-153 - Hwasuk Cho, Kihwan Seong, Kwang-Hee Choi, Jin-Hyeok Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
8.7 A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz. 154-155 - Pedram Lajevardi, Masayuki Miyamoto, Makoto Ikeda:
Session 9 overview: Sensors. 156-157 - Sining Pan, Yanquan Luo, Saleh Heidary Shalmany, Kofi A. A. Makinwa:
9.1 A resistor-based temperature sensor with a 0.13pJ·K2 resolution FOM. 158-159 - Kaiyuan Yang, Qing Dong, Wanyeong Jung, Yiqun Zhang, Myungjoon Choi, David T. Blaauw, Dennis Sylvester:
9.2 A 0.6nJ -0.22/+0.19°C inaccuracy temperature sensor using exponential subthreshold oscillation dependence. 160-161 - Bahman Yousefzadeh, Kofi A. A. Makinwa:
9.3 A BJT-based temperature sensor with a packaging-robust inaccuracy of ±0.3°C (3σ) from -55°C to +125°C after heater-assisted voltage calibration. 162-163 - Maximilian Marx, Daniel DeDorigo, Sebastian Nessler, Stefan Rombach, Michael Maurer, Yiannos Manoli:
9.4 A 27µW 0.06mm2 background resonance frequency tuning circuit based on noise observation for a 1.71mW CT-ΔΣ MEMS gyroscope readout system with 0.9°/h bias instability. 164-165 - Elmar Bach, Richard Gaggl, Luca Sant, Cesare Buffa, Snezana Stojanovic, Dietmar Straeussnigg, Andreas Wiesbauer:
9.5 A 1.8V true-differential 140dB SPL full-scale standard CMOS MEMS digital microphone exhibiting 67dB SNR. 166-167 - Jae-Sung An, Sang-Hyun Han, Ju Eon Kim, Dong-Hyun Yoon, Young-Hwan Kim, Han-Hee Hong, Jae-Hun Ye, Sung-Jin Jung, Seung-Hwan Lee, Ji-Yong Jeong, Kwang-Hyun Baek, Seong-Kwan Hong, Oh-Kyong Kwon:
9.6 A 3.9kHz-frame-rate capacitive touch system with pressure/tilt angle expressions of active stylus using multiple-frequency driving method for 65″ 104×64 touch screen panel. 168-169 - Hyunseok Hwang, Hyeyeon Lee, Hongchae Kim, Youngcheol Chae:
9.7 A 6.9mW 120fps 28×50 capacitive touch sensor with 41.7dB SNR for 1mm stylus using current-driven ΔΣ ADCs. 170-171 - Hui Jiang, Kofi A. A. Makinwa, Stoyan N. Nihtianov:
9.8 An energy-efficient 3.7nV/√Hz bridge-readout IC with a stable bridge offset compensation scheme. 172-173 - Vikram Chaturvedi, Mohammad Reza Nabavi, Johan Vogel, Kofi A. A. Makinwa, Stoyan N. Nihtianov:
9.9 A 0.6nm resolution 19.8mW eddy-current displacement sensor interface with 126MHz excitation. 174-175 - Hoi Lee, Gerard Villar Pique, Axel Thomsen:
Session 10 overview: DC-DC converters. 176-177 - Nicolas Butzen, Michiel Steyaert:
10.1 A 1.1W/mm2-power-density 82%-efficiency fully integrated 3∶1 Switched-Capacitor DC-DC converter in baseline 28nm CMOS using Stage Outphasing and Multiphase Soft-Charging. 178-179 - Christopher Schaef, Eric Din, Jason T. Stauth:
10.2 A digitally controlled 94.8%-peak-efficiency hybrid switched-capacitor converter for bidirectional balancing and impedance-based diagnostics of lithium-ion battery arrays. 180-181 - Wen-Chuen Liu, Pourya Assem, Yutian Lei, Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski:
10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS. 182-183 - Yong-Min Ju, Se-un Shin, Yeunhee Huh, Sang-Hui Park, Jun-Suk Bang, Kiduk Kim, Sung-Won Choi, Ji-Hun Lee, Gyu-Hyeong Cho:
10.4 A hybrid inductor-based flying-capacitor-assisted step-up/step-down DC-DC converter with 96.56% efficiency. 184-185 - Li-Cheng Chu, Wen-Hau Yang, Xiao-Qing Zhang, Yan-Jiun Lai, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
10.5 A three-level single-inductor triple-output converter with an adjustable flying-capacitor technique for low output ripple and fast transient response. 186-187 - Lin Cheng, Wing-Hung Ki:
10.6 A 30MHz hybrid buck converter with 36mV droop and 125ns 1% settling time for a 1.25A/2ns load transient. 188-189 - Bumkil Lee, Min Kyu Song, Ashis Maity, Dongsheng Brian Ma:
10.7 A 25MHz 4-phase SAW hysteretic DC-DC converter with 1-cycle APC achieving 190ns tsettle to 4A load transient and above 80% efficiency in 96.7% of the power range. 190-191 - Arun Paidimarri, Anantha P. Chandrakasan:
10.8 A Buck converter with 240pW quiescent power, 92% peak efficiency and a 2×106 dynamic range. 192-193 - Takashi Kono, Ki-Tae Park, Leland Chang:
Session 11 overview: Nonvolatile memory solutions. 194-195 - Ryuji Yamashita, Sagar Magia, Tsutomu Higuchi, Kazuhide Yoneya, Toshio Yamamura, Hiroyuki Mizukoshi, Shingo Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang, Ying Yu, Yuko Utsunomiya, Yosuke Kato, Manabu Sakai, Masahide Matsumoto, Hardwell Chibvongodze, Naoki Ookuma, Hiroki Yabe, Subodh Taigor, Rangarao Samineni, Takuyo Kodama, Yoshihiko Kamata, Yuzuru Namai, Jonathan Huynh, Sung-En Wang, Yankang He, Trung Pham, Vivek Saraf, Akshay Petkar, Mitsuyuki Watanabe, Koichiro Hayashi, Prashant Swarnkar, Hitoshi Miwa, Aditya Pradhan, Sulagna Dey, Debasish Dwibedy, Thushara Xavier, Muralikrishna Balaga, Samiksha Agarwal, Swaroop Kulkarni, Zameer Papasaheb, Sahil Deora, Patrick Hong, Meiling Wei, Gopinath Balakrishnan, Takuya Ariki, Kapil Verma, Chang Hua Siau, Yingda Dong, Ching-Huang Lu, Toru Miwa, Farookh Moogat:
11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology. 196-197 - Qing Dong, Yejoong Kim, Inhee Lee, Myungjoon Choi, Ziyun Li, Jingcheng Wang, Kaiyuan Yang, Yen-Po Chen, Junjie Dong, Minchang Cho, Gyouho Kim, Wei-Keng Chang, Yun-Sheng Chen, Yu-Der Chih, David T. Blaauw, Dennis Sylvester:
11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes. 198-199 - Shau-Yu Chou, Yu-Shiang Chen, Jun-Hao Chang, Yu-Der Chih, Tsung-Yung Jonathan Chang:
11.3 A 10nm 32Kb low-voltage logic-compatible anti-fuse one-time-programmable memory with anti-tampering sensing scheme. 200-201 - Chulbum Kim, Ji-Ho Cho, Woopyo Jeong, Il-Han Park, Hyun Wook Park, Doo-Hyun Kim, Daewoon Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-Lo Ahn, Jiyoung Lee, Jong-Hoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jonghoon Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sangki Hong, Byunghoon Jeong, Hyun-Jin Kim, Chunan Lee, Young-Sun Min, Inryul Lee, In-Mo Kim, Sunghoon Kim, Dongkyu Yoon, Ki-Sung Kim, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, Dae-Seok Byeon, Jin-Yub Lee, Ki-Tae Park, Kyehyun Kyung:
11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory. 202-203 - Fatih Hamzaoglu, Chun Shiah, Leland Chang:
Session 12 overview: SRAM. 204-205 - Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu:
12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. 206-207 - Taejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park, Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Cho, Yongjae Choo, Jaeseung Choi:
12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. 208-209 - Michael Clinton, Hank Cheng, Hung-Jen Liao, Robin Lee, Ching-Wei Wu, Johnny Yang, Hau-Tai Hsieh, Frank Wu, Jung-Ping Yang, Atul Katoch, Arun Achyuthan, Donald Mikan, Bryan Sheffield, Jonathan Chang:
12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications. 210-211 - Igor Arsovski, Michael Fragano, Robert M. Houle, Akhilesh Patil, Van Butler, Raymond Kim, Ramon Rodriguez, Tom Maffitt, Joseph J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, Steven Burns:
12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%. 212-213 - Guang-Kaai Dehng, Kyoohyun Lim, Aarno Pärssinen:
Session 13 overview: High-performance transmitters. 214-215 - Ming-Da Tsai, Chien-Cheng Lin, Ping-Yu Chen, Tao-Yao Chang, Chien-Wei Tseng, Lai-Ching Lin, Chris Beale, Bosen Tseng, Bernard Tenbroek, Chinq-Shiun Chiu, Guang-Kaai Dehng, George Chien:
13.1 A fully integrated multimode front-end module for GSM/EDGE/TD-SCDMA/TD-LTE applications using a Class-F CMOS power amplifier. 216-217 - Michael Fulde,