default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDISOCC 2022: Gangneung-si, Republic of Korea
- 19th International SoC Design Conference, ISOCC 2022, Gangneung-si, Republic of Korea, October 19-22, 2022. IEEE 2022, ISBN 978-1-6654-5971-6
- Qibang Zang, Wang Ling Goh, Fei Li, Lu Lu, Anh Tuan Do:
Temperature Compensation on SRAM-Based Computation in Memory Array. 1-2 - Taehwan Kim, Jongsun Park:
Source-Line Shared SOT-MRAM Cell for Energy Efficient Read Operation. 3-4 - Hyeyeong Lee, Joonhyung Kim, Jongsun Park:
SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation. 5-6 - Hyunchul Park, Jongsun Park:
Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage Operations. 7-8 - Yeseul Kim, Jongsun Park:
Energy-Efficient STT-MRAM based Digital PIM supporting Vertical Computations Using Sense Amplifier. 9-10 - Tzung-Je Lee, Hung-Hsiang Chang:
Fast-Transient LDO Regulator with RC-less Low-Impedance Buffer and PVT Compensation. 11-12 - Qurat ul Ain, Muhammad Basim, Syed Adil Ali Shah, Kang-Yoon Lee:
A Design of high-efficiency Constant On-Time Control DC-DC Buck Converter for Power Management integrated circuits. 13-14 - Jeongwook Koh, Elmar Herzer:
A Fully Differential Switched Capacitor Amplifier with a Two-Stage Folded-Mesh Class AB Operational Amplifier in a 22 nm FD-SOI CMOS Process. 15-16 - Tzung-Je Lee, Kuo-Hsun Tu:
Wide Dynamic Range Temperature Sensor Using High Sensitivity PTAT Current Generator. 17-18 - Junung Choi
, Jaeik Cho, Won Joon Choi, Myungguk Lee, Byungsub Kim:
A Layout Generator of Latch, Flip-Flop, and Shift Register for High-Speed Links. 19-20 - Seung Ho Shin, Hayoung Lee, Sooryeong Lee, Younwoo Yoo, Sungho Kang:
An Improved Early Termination Methodology Using Convolutional Neural Network. 21-22 - Sooryeong Lee, Hayoung Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang:
PROG: Per-Row Output Generator for BOST. 23-24 - Sunghoon Kim, Seokjun Jang, Youngki Moon, Sungho Kang:
Pair-Grouping Scan Chain Architecture for Multiple Scan Cell Fault Diagnosis. 25-26 - Jangwon Suh, Wanyeong Jung:
FACTGen: Framework for Automated Circuit Topology Generator. 27-28 - Dongsu Kim, Jongsun Park:
Distributed Accumulation based Energy Efficient STT-MRAM based Digital PIM Architecture. 29-30 - Hayoung Lee, Sooryeong Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang:
FAME: Fault Address Memory Structure for Repair Time Reduction. 31-32 - Yoojeong Yang, Dain Chon, Woong Choi:
Hiding Precharge Operation For Improved SRAM Cycle Time. 33-34 - Minseo Kim, Jongsun Park:
High Detection Rate BCH Code with CRC Code for Memory Application. 35-36 - Dongwhee Kim, Jungrae Kim:
YOCO: Unified and Efficient Memory Protection for High Bandwidth Memory. 37-38 - Wonkyu Do, Neungin Jeon, Hoyong Jung, Young-Chan Jang:
Second-order Incremental Delta-sigma Modulator with 3-bit SAR ADC and Capacitor Sharing Scheme. 39-40 - Huaikun Ji, Zhenhao Fan, Zhaonan Lu, Zhichao Tan, Menglian Zhao:
A 10.12μW 101.98dB-SNDR Three-step Incremental Analog-to-Digital Converter. 41-42 - Phanidarapu Mounika, Deeksha Verma, Kang-Yoon Lee:
An Improved Dynamic Latch Comparator with Low Power Consumption for SAR ADC Applications. 43-44 - Yung-Chuan Su, Shi-Yu Huang:
Just-Enough Strategy for Accurate Clock Jitter Measurement Using A Cyclic Time-to-Digital Converter. 45-46 - Ko-Chi Kuo, Hsiung-Yu Chi:
A 8-bit 300MHz Domino Based Successive Approximation Register ADC. 47-48 - Jeongho Lee, Jungkeun Park, Ki-Duk Kim:
An Energy Efficient Finite State Machine Algorithm for Real-Time Asset Monitoring and Tracking System. 49-50 - Donghui Lee, Junhyuk Baik, Yongtae Kim:
An Accurate and Efficient Stochastic Computing Adder Exploiting Bit Shuffle Control Scheme. 51-52 - Jongho Park, Sangjun Lee, Inhwan Lee, Sungwhan Park, Sungho Kang:
Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST. 53-54 - Masanao Okamoto, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA. 55-56 - Hyelin Seok, Hyoju Seo, Jungwon Lee, Yongtae Kim:
A Novel Efficient Approximate Adder Design using Single Input Pair based Computation. 57-58 - Dain Chon, Yoojeong Yang, Hayoung Choi, Woong Choi:
Hardware-Efficient Barrel Shifter Design Using Customized Dynamic Logic Based MUX. 59-60 - Jeongeun Kim, Yue Ri Jeong, Kwonneung Cho, Won Sik Jeong, Seung Eun Lee:
Reconfigurable Stochastic Computing Architecture for Computationally Intensive Applications. 61-62 - Yongzhen Zhang, Yuan Zhang, Yonggang Zhang, Hui Chen:
Low-Complexity High-Performance Method for Calculating Arbitrary Logarithm Function. 63-64 - Monalisa Das, Babita Jajodia:
Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGA. 65-66 - Iksu Jang, Jaeyoung Seo, Changjae Moon, Byungsub Kim:
A Cost-efficient FPGA-based Embedded System for Biosensor Platform. 67-68 - Evelyn Q. Raguindin, Reibelle Q. Raguindin, Mark Angelo C. Purio, Ronnie O. Serfa Juan:
A Morphological Image-based Recognition of Iron Triad using a Convolutional Neural Network. 69-70 - Han Cho, Jongsun Park:
Channel-Wise Activation Map Pruning using Max-Pool for Reducing Memory Accesses. 71-72 - Seungeon Hwang, Jongsun Park:
Percentile Clipping based Low Bit-Precision Quantization for Depth Estimation Network. 73-74 - Hyeonseok Hong, Hyun Kim:
Feature Distribution-based Knowledge Distillation for Deep Neural Networks. 75-76 - Ke Ma, Shinji Kimura:
ApproxTorch: An Approximate Multiplier Evaluation Environment for CNNs based on Pytorch. 77-78 - Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Trong-Thuc Hoang, Cong-Kha Pham:
A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore. 79-80 - Monalisa Das, Babita Jajodia:
FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware Primitives. 81-82 - Da Won Kim, Dalta Imam Maulana, Wanyeong Jung:
Kyber Accelerator on FPGA Using Energy-Efficient LUT-Based Barrett Reduction. 83-84 - Yui Koyanagi, Tomoaki Ukezono:
An Extremely Light-Weight Countermeasure to Power Analysis Attack in Dedicated Circuit for AES. 85-86 - Tuan-Kiet Dang, Ronaldo Serrano, Trong-Thuc Hoang, Cong-Kha Pham:
A Novel Ring Oscillator PUF for FPGA Based on Feedforward Ring Oscillators. 87-88 - Minjoon Kim, Jaehyuk So, Taemin Hwang:
Real-time Implementation of l -key Pose Estimation for Driver Behavior Analysis. 89-90 - Hyunjeong Kwon, Youngsu Kwon, Jinho Han:
Backward Graph Construction and Lowering in DL Compiler for Model Training on AI Accelerators. 91-92 - Yuan Zhang, Lele Peng, Lianghua Quan, Shubin Zheng, Qiufeng Feng, Yonggang Zhang, Hui Chen:
2b-sigmoid and 2b-tanh: Low Hardware Complexity Activation Functions for LSTM. 93-94 - Jaemyung Kim, Jin-Ku Kang, Yongwoo Kim:
An FPGA Implementation of CNN-based Compression Artifact Reduction. 95-96 - Dongwoo Lew, Jongsun Park:
A Layer-wise Training and Pruning Method for Memory Efficient On-chip Learning Hardware. 97-98 - Jiwon Kim, Seungsik Moon, Youngjoo Lee:
Hardware Analysis of Channel Estimation Method for IRS-Aided MIMO Wireless Systems. 99-100 - Yuuki Teramura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Smart Computational Resource Distribution System with Automatic Classification Interface for CPS. 101-102 - Seongyoon Kang, Jongsun Park:
Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus. 103-104 - Thang Xuan Pham, Phap Duong-Ngoc, Hanho Lee, Tuy Tan Nguyen:
Low-Complexity Architecture of Finding First Four Minimum Values for Non-binary LDPC Decoders. 105-106 - Koki Ando, Yukinaga Shimoda, Daisuke Ito, Makoto Nakamura:
An electrical chromatic dispersion emulator using digital signal processing. 107-108 - Junho Moon, Sukwon Kang, Dongyeol Yang, Byung-Sung Kim:
A Ka band FMCW Transmitter with a High Ratio Multiplier. 109-110 - Ho Won Kim, Hun Park, Kang-Yoon Lee:
Dual Band Wide Range PLL for IoT Application. 113-114 - Youngchae Jeon, Jaehoon Jeong, Yeong Min Jang, Jinho Jeong:
D-band Power Amplifier Module with Medium Output Power Using E-plane Waveguide Transition. 115-116 - Ealwan Lee:
Tone-based Measurement of Excess Group Delay in Programmable Gain Receiver Chains for RF Ranging. 117-118 - Kyungjoon Chang, Taewhan Kim:
Analysis of Impacting Multi-stack Standard Cells on Chip Implementation. 119-120 - Hyeonchan Lim, Hyojoon Yun, Juyong Lee, Sungho Kang:
Cell-Aware Scan Diagnosis Using Partially Synchronous Set and Reset. 121-122 - Hyunjun Park, Woo-Seok Choi:
Performance Variability Modeling of Analog Circuits Using Improved Orthogonal Matching Pursuit. 123-124 - Fern Nee Tan, Li Wern Chew, Ling Li Ong:
Determining PCIe5 Jitter Margin using SIPI Co-Sim. 125-126 - Hyunwoo Kim, Seungwon Baek, Jaehong Song, Taigon Song:
A Novel Processing Unit and Architecture for Process-In Memory (PIM) in NAND Flash Memory. 127-128 - Joonhyung Kim, Jongsun Park:
The Quantitative Comparisons of Analog and Digital SRAM Compute-In-Memories for Deep Neural Network Applications. 129-130 - Jihyung Jung, Youngmin Kim:
A High-Performance, Low-Power 8-Bit Full-Adder Using 8+T Differential SRAM for Computation-inMemory. 131-132 - Jihoon Jang, Hyun Kim, Hyokeun Lee:
Performance Analysis of a Phase-Change Memory System on Various CNN Inference Workloads. 133-134 - Yingfeng Wang, Yi Sheng Chong, Wang Ling Goh, Anh Tuan Do:
Noise-Aware and Lightweight LSTM for Keyword Spotting Applications. 135-136 - Yoon Heo, Won-Young Lee:
A Wide Range Digitally Controlled Oscillator with Direct Proportional Loop Control. 137-138 - Kyungmin Baek, Kahyun Kim, Deog-Kyoon Jeong:
A 5GHz All-Digital PLL with shunt regulating Ring DCO in BOST for DDR5 ATE. 139-140 - Honggyoo Ahn, Joonghyun Song, Woo-Seok Choi:
Impact of PI Nonlinearity on High-Resolution Frequency-to-Digital Converter. 141-142 - Hyun-In Kim, Jin-Ku Kang:
A Low-Power Counter-based Digital CDR. 143-144 - Jin-Ho Kim, Jin-Ku Kang:
A Wide-range Low Power Quarter Rate Single Loop CDR. 145-146 - Yoonho Song, Eunseo Kim, Deog-Kyoon Jeong:
Design of Energy Harvesting System with Piezoelectric Device for Onetime-High-Energy Applications. 149-150 - Seongmin Park, Gilsu Jeon, Suwon Seong, Yoonyoung Chung:
2T Neuromorphic Device based on oxide semiconductor with High Linearity and Symmetry for High-Precision Training. 151-152 - Syed Muhammad Abubakar, Hanjun Jiang, Yue Yin, Jiahua Shi, Xiaofeng Yang, Wen Jia, Zhihua Wang:
A 1.92 μA Always-on ECG Monitoring Mixed-Signal SoC for Implantable Medical Application. 155-156 - Jin-Fu Li:
Design and Test of Computing-In Memories. 157-158 - Chuan-Han Cheng, Shih-Hsu Huang, Jin-Fu Li:
Design and Dataflow for Multibit SRAM-Based MAC Operations. 159-160 - Yu-Guang Chen, Chi-Hsu Wang, Ing-Chao Lin:
An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine. 161-162 - Hsin-Tzu Wu, Hsin-Yi Pai, Wei-Kai Cheng:
Layer-wise Exploration of Synaptic Array and Weight Mapping on Heterogeneous Tile-based RRAM CIM Architecture. 163-164 - Xingyuan Hu, Zhuang Shao, Chenjia Xie, Li Du, Yuan Du:
SVR: A Shard-aware Vertex Reordering Method for Efficient GNN Execution and Memory Access. 165-166 - Sourav De, Maximilian Lederer, Yannick Raffel, Franz Müller, Konrad Seidel, Thomas Kämpfe:
Roadmap for Ferroelectric Memory: Challenges and Opportunities for IMC Applications. 167-168 - Wei Lu, Pei-Yu Ge, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang:
Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM. 169-170 - Jui-I Kao, Wei Lu, Po-Tsang Huang, Hung-Ming Chen:
Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN Accelerator. 171-172 - Zhou Yu Xuan, Ching-Jui Lee, Tsung Tai Yeh:
Lego: Dynamic Tensor-Splitting Multi-Tenant DNN Models on Multi-Chip-Module Architecture. 173-174 - De-Yang Chiu, Shih-Hsu Huang:
Dataflow and Hardware Design for The Sharing of Feature Maps. 175-176 - Kai-Fen Chang, Yuan-Ho Chen:
High Accuracy Abnormal ECG Detection Chip Using a Simple Neural Network. 177-178 - Song-Nien Tang, Chu-Ming Yen:
Long-Length Accumulation Unit with Efficient Biasing for Binary Weight CNNs. 179-180 - Yu-Kuen Lai, Kai-Po Chang, Xiu-Wen Ku, Hsiang-Lun Hua:
A Machine Learning Accelerator for DDoS Attack Detection and Classification on FPGA. 181-182 - Chaolin Rao, Yueyang Zheng, Haochuan Wan:
A Multi-precision Multiply-Accumulation Array. 183-184 - Dian Sheng, Rongxuan Xu, Qinan Wang, Chun Zhao:
Spiking Neural Networks for digital hand-written number recognition. 185-186 - J. Li, C. Zhao, K. Man:
Neuromorphic Hardware Based on Artificial Synaptic Devices. 187-188 - Kangshi Wang, Jieming Ma, Jingyi Wang, Bo Xu, Yifan Tao, Ka Lok Man:
Digital Twin based Maximum Power Point Estimation for Photovoltaic Systems. 189-190 - Gianfranco Avitabile, Antonello Florio, Ka Lok Man, Chun Zhao:
A Long-Term Synchronized System for Healthcare. 191-192 - Antonello Florio, Gianfranco Avitabile, Ka Lok Man:
Estimating the Angle of Arrival from Multiple RF Sources using Phase Interferometry. 193-194 - Naoya Kaneko, Koki Iwabuchi, Kenshiro Kato, Daichi Watari, Dafang Zhao, Ittetsu Taniguchi, Hiroki Nishikawa, Takao Onoye:
An Evaluation of Electricity Demand Forecasting Models for Smart Energy Management Systems. 195-196 - Tomoyasu Shimhada, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Monocular Depth Estimation with Optical Flow Attention for Autonomous Drones. 197-198 - Savath Saypadith, Sunepha Detvongsa, Takao Onoye:
Joint Generative Network for Abnormal Event Detection in Surveillance Videos. 199-200 - Yusuke Inoue, Xiangbo Kong, Takeshi Kumaki:
Implementation of AI characteristic motion detecting for improper-photography prevention system. 201-202 - Wanyin Shi, Hiroki Matsumiya, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Fusing Infrared and Visible Images for DNN-based Nighttime Human Detection. 203-204 - Qi Li, Hengyi Li, Lin Meng:
CNN Acceleration based on Dynamic Pruning and FPGAs Implementation. 205-206 - Shibo Tang, Xingxin Wang, Yifei Gao, Wei Hu:
Accelerating SoC Security Verification and Vulnerability Detection Through Symbolic Execution. 207-208 - Xingxin Wang, Shibo Tang, Wei Hu:
Towards Automatic Property Generation for SoC Security Verification. 209-210 - Yixiao Chen, Jinfeng Song, Shuai Chen, Yuan Cao, Jing Ye, Huawei Li, Xiaowei Li, Xin Lou, Enyi Yao:
Exploring the high-throughput and low-delay hardware design of SM4 on FPGA. 211-212 - Zeyu Li, Zhao Huang, Junjie Wang, Quan Wang:
Investigate of Mitigation Solution against Hardware Trojans Attack on Evolvable Hardware Platform. 213-214 - Tian Feng, Haojie Pei, Zhou Jin, Xiao Wu:
A survey and perspective on electronic design automation tools for ensuring SoC security. 215-216 - Satwik Patnaik, Vasudev Gohil, Hao Guo, Jeyavijayan (JV) Rajendran:
Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges. 217-218 - Yota Matsui, Kisara Nakajima, Weisen Luo, Xiuqin Wei:
Design of Class-EF2 WPT System with Relay Coil. 219-220 - Yusuke Goto, Hiroyuki Asahara, Daisuke Ito, Takuji Kousaka:
Chattering phenomenon in a high-side gate driver circuit using MOSFET equivalent circuit. 221-222 - Daiki Hozumi, Shota Uchino, Takuji Kousaka, Hiroyuki Asahara:
Comparative Study of Nonlinear Dynamics in DC-DC Converter with TEM. 223-224 - Yuma Furutani, Takuji Kousaka, Shota Uchino, Hiroyuki Asahara:
A simple approach of stability analysis and MPPT control in DC-DC converter with TEM. 225-226 - Toshihiro Matsuda, Yutaro Komiyama, Wenqi Zhu, Kien Nguyen, Hiroo Sekiya:
Maximum Efficiency Tracking for Wireless Power Transfer with Multiple Receivers. 227-228 - Junghoon Lee, Chang-Ryeol Jeon, Suk-Ju Kang:
Performance Comparison of Soiling Detection Using Anomaly Detection Methodology. 229-230 - Young-Ju Oh, Hyo-Jin Park, Joo-Mi Cho, Hyeon-Ji Choi, Su-Min Park, Chan-Ho Lee, Esun Baik, Chan-Kyu Lee, Ho-Chan Ahn, Sung-Wan Hong:
A High Slew-rate Wide-range Capacitive Load Driving Buffer Amplifier with Correlated Dual Positive Feedback Loops. 231-232 - Hyoung-Jung Kim, Jae-Hyuk Lee, Jae-Geun Lim, Jun-Ho Boo, Ho-Jin Kim, Seong-Bo Park, Youngdon Choi, Jung-Hwan Choi, Gil-Cho Ahn:
A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor. 235-236 - Jaehoon Jeong, Hyungeun Kim, Jihyeon Lee, Jaehyun Park, Jongsin Shin, Jinho Jeong:
Miniaturization of bandwidth extension circuit for ESD I/O pad using bridged T-coil. 237-238 - Lujie Peng, Longke Yan, Junyu Yang, Zhiyi Chen, Jun Zhou:
A Robust and Lightweight Environmental Sound Classification Technique with Adaptation to Microphone for AIoT Sound Sensing. 239-240 - Jaehyun Lee, Jong-Hyeok Yoon:
A Neuromorphic SLAM Accelerator Supporting Multi-Agent Error Correction in Swarm Robotics. 241-242 - Bo Wang, Ke Dong, Nurul Akhira Binte Zakaria, Mohit Upadhyay, Weng-Fai Wong, Li-Shiuan Peh:
Network-on-Chip-Centric Accelerator Architectures for Edge AI Computing. 243-244 - Yuncheng Lu, Zehao Li, Xin Zhang, Tony Tae-Hyoung Kim:
A Low-Power Gesture Recognition System utilizing Hybrid Tiny Classifiers. 245-246 - Yoko Uwate, Yoshifumi Nishio:
Clustering in Globally Coupled Chaotic Circuits with Changing Weights. 247-248 - Gianluca Zoppo, Francesco Marrone, Fernando Corinto, Anil Korkmaz, Su-In Yi, Samuel Palermo, R. Stanley Williams:
A Mathematical Analysis of Wire Resistance Problem in Memristor Crossbars. 249-250 - Hwan-Ung Kim, Jin-Ku Kang:
High-speed Serial Interface using PWAM Signaling Scheme. 255-256 - Jaehyeon So, Jong Hwan Ko:
An Efficient Systolic Array with Variable Data Precision and Dimension Support. 257-258 - Phap Duong-Ngoc, Thang Xuan Pham, Hanho Lee, Tuy Tan Nguyen:
Flexible GPU-Based Implementation of Number Theoretic Transform for Homomorphic Encryption. 259-260 - Amrita Rana, Kyung Ki Kim:
Search-Efficient NAS: Neural Architecture Search for Classification. 261-262 - Hayun Bong, Kyungseon Cho, Yeongkyo Seo:
Automation Framework for Digital Circuit Design and Verification. 263-264 - Yui Kishimoto, Hiroyuki Torikai:
Pitch-Shift Effects of an Ergodic Sequential Logic Nonlinear Cochlear Model Induced by Three Tones. 265-266 - Tatsumi Makino, Yuu Miino, Haruna Matsushita, Takuji Kousaka:
Computation of homoclinic points using particle swarm optimization in 2-dimensional discrete dynamical systems. 267-268 - Takuya Nakamura, Ryosuke Shimizu, Yoko Uwate, Yoshifumi Nishio:
Time Series Analysis with Noise-Mixing Effects Using Neural Networks. 269-270 - Ryosuke Shimizu, Yoko Uwate, Yoshifumi Nishio:
Investigation of the Effect of Adding Random Noise to Noisy Biological Signals on the Classification of Neural Network. 271-272 - Masashi Tomita, Tadashi Tsubone:
Multi-point search method for system identification based on chaotic dynamics. 273-274 - Shogo Shirafuji, Hiroyuki Torikai:
A hardware-efficient sequential logic biochemical switch model toward biosystem simulator. 275 - Yuta Shiomi, Hiroyuki Torikai:
A hardware-efficient ergodic sequential logic neuron network for brain prosthetic FPGA. 276-277 - Ryuji Nagazawa, Kien Nguyen, Hiroo Sekiya, Hiroyuki Torikai:
Reduction of Processing Time for Wireless Spiking Neural Network Using Wireless Communication Devices for IoT. 278-279 - Kiichi Yamashita, Yoko Uwate, Yoshifumi Nishio:
Synchronization Phenomena of Coupled Oscillators with Node and Edge Weights in Two-Dimensional Complex Networks. 280-281 - Takahiro Hattori, Yoko Uwate, Yoshifumi Nishio:
Phase Change of Three Coupled Chaotic Circuits to Input Signals. 282-283 - Jiseong Lee, Seung Soo Kwak, Yun Chan Im, Hyunjin Lee, Yong Sin Kim:
16 x 10 Pressure Sensor CMOS Driver IC for Resistance Interfence Calibration of Cells. 284-285 - Chiang Liang Kok:
A Novel Study on a 300°C, High Performance LDO Regulator Using Silicon-On-Insulator Process for Extreme Drill Bit Application. 286-289 - Dong-Kil Yun, Jung-Hoon Chun:
STT-MRAM Read and Write Circuit for High Reliability and Power Efficiency. 290-291 - Tsung-Ying Chen, Ching-Yuan Yang, Dung-An Wang:
A 80-MHz 91.2 ppm/°C Self-Biased Frequency-Locked-Loop Timer. 292-293 - Hyun-jin Jeong, Kang-Yoon Lee:
A Design of SIDITO Buck-Boost Converter with Real Time Maximum Power Point Tracking for RF Energy Harvesting System. 294-297 - Yun Seong Lee, Yun Chan Im, Hyunjin Lee, Yong Sin Kim:
Capless Low-Dropout Regulator with a Dual Feedback Loop and Voltage Dampers. 298-299 - Junho Song, Minsu Kim, Hyung-Min Lee:
A Three-Level Boost Converter With Peak Current Mode Control for Flying Capacitor Self-Balancing. 300-301 - Min-Hyeong Son, Young-Chan Lee, Hyun-Min Baek, Hyo-Jeong Choi, Ji-Yong Um:
A Programmable Gain Amplifier with Fast Transient Response for Medical Ultrasound System. 302-303 - Yosep Cho, Jongmin Park, Jinwook Burm:
A 12.5-Gb/s Switched Capacitor Based Two Tap DFE With High BER Performance. 304-305 - Soonseong Hong, Hyouk-Kyu Cha:
A Power-Efficient Low-Noise Neural Recording Amplifier IC with High Tolerance to Stimulation Artifacts. 306-307 - Aoran Wang, Jie Fang, Yinan Xu, Yihu Xu, Yubing Wang, Yujing Wu, Jin-Gyun Chung:
Anomaly information detection and fault tolerance control method for CAN-FD bus network. 308-309 - Hyojun Yoo, Hyouk-Kyu Cha:
A Biopotential Amplifier IC with Active Common-Mode Cancellation for Closed-Loop Neural Interfaces. 310-311 - Z. Di, Aarthy Mani, Anh Tuan Do, A. Baranikov, R. M. Veetil, R. P. Domínguez, Arseniy I. Kuznetsov, Kevin T. C. Chai:
Linearity Characterization of Hybrid Driving Scheme for Spatial Light Modulator System. 312-313 - Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Time-Efficient Approximate Stochastic Computing for Medical Imaging Applications. 314-315 - Wen-Hsin Tsai, Kuei-Ann Wen:
SoC Design for Mobile Real-time Badminton Stroke Classification Design. 316-317 - Daero Kim, Jungrae Kim:
Adaptive Granularity On-die ECC. 318-319 - Taesu Shin, Kibum Lee:
The first study of 10nm-class backside defect using Co-Routine based ETL in DRAM. 320-321 - Minjoon Kim, Jaehyuk So:
Design of State of Charge and Health Estimation for Li-ion Battery Management System. 322-323 - Sumin Kim, Byungmin Ahn, Bohwan Jun, Mankeun Seo, Hongrak Son, Yong Ho Song:
Low Power Decoder Architecture of Product Code for Storage Controller. 324-325 - Sang-Ung Shin, Jin-Ku Kang, Yongwoo Kim:
A Design and Implementation of MIPI A-PHY RTS Layer. 326-327 - Mannhee Cho, Dongchan Lee, Sanghyun Lee, Youngmin Kim, Hyung-Min Lee:
Automated Reverse Engineering Tools for FPGA Bitstream Extraction and Logic Estimation. 328-329 - Dongchan Lee, Sanghyun Lee, Mannhee Cho, Hyung-Min Lee, Youngmin Kim:
Data extraction from flash memory and reverse engineering using Xilinx 7 series FPGA boards. 330-331 - Jiyoung Lee, Youngmin Kim:
Hybrid Assistive Circuit of SRAM for Improving Read and Write Noise Margin in 3nm CMOS. 336-337 - Shungo Shimohane, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing. 338-339 - Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han:
Releasing the Memory Bottleneck to Display Video Correctly. 340-341 - Mayukhmali Das, Sounak Dutta, Sayan Chatterjee:
Logic and Reduction Operation based Hardware Trojans in Digital Design. 342-343 - Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim:
A Time-Domain Parallel Counter for Deep Learning Macro. 346-347 - Sang-Bo Park, Go-Eun Woo, HyungWon Kim:
Design Optimization for Decimation Filter for High Performance Sigma-Delta ADC. 348-349 - Sungkyun Shin, Soyeon Choi, Eunchae Lee, Songyeon Lee, Hoyoung Yoo:
Implementation of Aurora Interface using SFP+ Transceiver. 350-351 - Sanghyun Lee, Youngmin Kim:
Low Power Ternary XNOR using 10T SRAM for In-Memory Computing. 352-353 - Jihun Jeon, Jin-Ku Kang, Yongwoo Kim:
Filter Pruning Method for Inference Time Acceleration Based on YOLOX in Edge Device. 354-355 - Dennis Agyemanh Nana Gookyi, Eunchong Lee, Kyungho Kim, Sung-Joon Jang, Sang-Seol Lee:
Exploring GEMM Operations on Different Configurations of the Gemmini Accelerator. 356-357 - Hyun Woo Oh, Won Sik Jeong, Seung Eun Lee:
Evaluation of Posit Arithmetic on Machine Learning based on Approximate Exponential Functions. 358-359 - Jihye Kim, Hayoung Lee, Jongho Park, Sungho Kang:
ZOS: Zero Overhead Scan for Systolic Array-based AI accelerator. 360-361 - Young Jun Lim, Do Young Kim, Joon Hyeon Park, Myung Hoon Sunwoo:
DNN-based Cancer Recurrence Predictor using FPGA. 362-363 - Jia Park, Woo-Seok Choi:
Impact of Oscillator Phase Noise on Time-Domain SNN Performance. 364-365 - Tae Hyun Kim, Hyeonchan Lim, Minho Cheong, Hyojoon Yun, Sungho Kang:
Logic Diagnosis Based on Deep Learning for Multiple Faults. 366-367 - Jisu Kwon, Daejin Park:
Lightweighted AI-based Inference using Deterministic Randomness Compensation for Microcontroller ADC Resolution Enhancement. 368-369 - Kyungchul Lee, Jongsun Park:
Clipped Quantization Aware Training for Hardware Friendly Implementation of Image Classification Networks. 370-371 - Joongho Jo, Jongsun Park:
Class Difficulty based Mixed Precision Quantization for Low Complexity CNN Training. 372-373 - Takumi Nabeshima, Daisuke Ito, Makoto Nakamura, Takefumi Koyama, Katsunori Muto:
Electromagnetic Shielding Effectiveness of Sputtered Non-woven Noise Suppression Sheet with Varied Air Gap. 374-375 - Bonghyuk Park, Hui Dong Lee, Seunghyun Jang, Sunwoo Kong, Seung-Hun Wang, Seok-Bong Hyun:
A 28GHz-band integrated GaAs Power Amplifier for 5G Mobile Communications. 376-377 - Hui Dong Lee, Seunghyun Jang, Sunwoo Kong, Bonghyuk Park, Seok-Bong Hyun:
A K-band CMOS Power Amplifier with 3-Bit Phase Shifting Characteristics. 378-379 - Yeong Min Jang, Jinho Jeong:
Modified Wilkinson Power Divider with Resonating Stubs for Physical Isolation of Output Ports. 380-381 - Jeongbae Seo, Shinbeom Choi, Jaeik Lee, Sekwang Kim, Wooseong Cheong, ByungChul Yoo, Yong Ho Song:
Enhancement of Emulation Usage for NVMe Solid State Drive. 382-383 - Dongyoung Lee, Kyungsu Kang, Jongseong Park, Byunghoon Lee, Jinbeom Kim, Jae-Woo Im:
Toward Heterogeneous Virtual Platforms For Early SW Development. 384-385 - Myeongwoo Jin, Doekkeun Oh, Juho Kim:
High-Level Synthesis Considering Layer Assignment on Timing in 3D-IC. 386-387 - Myeongwoo Jin, Doekkeun Oh, Juho Kim:
Delay Impact on Process Variation of Interconnect throughout technology scaling. 388-389 - Jeong Woo Min, Jaeha Kim:
XSNN: a System-Level Simulator for Spiking Neural Network with Neuron Circuits and Synapse Devices. 390-391 - Gyuhyun Jung, Hyeokjun Kwon, Hyunhoon Lee, Youngjoo Lee:
Fast Estimation of NTT/INTT Accelerator Costs for RNS-Based Homomorphic Encryption. 392-393 - Nayoung Kwon, Daejin Park:
Lightweighted Shallow CTS Techniques for Checking Clock Tree Synthesizable Paths in RTL Design Time. 394-395 - Hyoseok Song, Kwangmin Kim, Changyoon Han, Byungsub Kim:
A Fast Eye Size Evaluation Method for High Speed Signal. 396-397 - Joonghyun Song, Woo-Seok Choi:
A Highly Linear Digitally Controlled Delay Line with Reduced Duty Cycle Distortion. 398-399
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-09 00:26 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
