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"A Delay Test Architecture for TSV With Resistive Open Defects in 3-D ..."

Hyungsu Sung et al. (2014)

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DOI: 10.1109/TVLSI.2013.2289964

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/SungCYK14
Hyungsu Sung, Keewon Cho, Kunsang Yoon, Sungho Kang:
A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2380-2387 (2014)

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