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ORCIDNiranjan Kulkarni
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2020 – today
- 2023
[j4]Ankit Wagle, Jinghua Yang, Niranjan Kulkarni, Sarma B. K. Vrudhula
:
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4164-4176 (2023)
2010 – 2019
- 2017
- [c10]Niranjan Kulkarni, Aykut Dengi, Sarma B. K. Vrudhula:
A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits. DAC 2017: 67:1-67:6 - 2016
- [j3]Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula:
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 24(9): 2873-2886 (2016) - [c9]Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula:
Digital IP protection using threshold voltage control. ISQED 2016: 344-349 - [i3]Sachin Mungmode, R. R. Sedamkar, Niranjan Kulkarni:
An Enhanced Edge Adaptive Steganography Approach Using Threshold Value for Region Selection. CoRR abs/1601.02076 (2016) - [i2]Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula:
Digital IP Protection Using Threshold Voltage Control. CoRR abs/1603.07370 (2016) - [i1]Niranjan Kulkarni, Sarma B. K. Vrudhula:
Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks. CoRR abs/1603.07371 (2016) - 2015
- [c8]Jinghua Yang, Joseph Davis, Niranjan Kulkarni, Jae-sun Seo, Sarma B. K. Vrudhula:
Dynamic and leakage power reduction of ASICs using configurable threshold logic gates. CICC 2015: 1-4 - [c7]Sarma B. K. Vrudhula, Niranjan Kulkarni, Jinghua Yang:
Design of threshold logic gates using emerging devices. ISCAS 2015: 373-376 - [c6]Jinghua Yang, Niranjan Kulkarni, Joseph Davis, Sarma B. K. Vrudhula:
Fast and robust differential flipflops and their extension to multi-input threshold gates. ISCAS 2015: 822-825 - 2014
- [j2]Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula:
Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. J. Parallel Distributed Comput. 74(6): 2452-2460 (2014) - [c5]Niranjan Kulkarni, Jinghua Yang, Sarma B. K. Vrudhula:
A fast, energy efficient, field programmable threshold-logic array. FPT 2014: 300-305 - [c4]Jinghua Yang, Niranjan Kulkarni, Shimeng Yu, Sarma B. K. Vrudhula:
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. NANOARCH 2014: 39-44 - 2012
- [c3]Niranjan Kulkarni, Nishant Nukala, Sarma B. K. Vrudhula:
Minimizing area and power of sequential CMOS circuits using threshold decomposition. ICCAD 2012: 605-612 - [c2]Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula:
Spintronic threshold logic array (STLA) - a compact, low leakage, non-volatile gate array architecture. NANOARCH 2012: 188-195 - 2011
- [j1]Tejaswi Gowda, Sarma B. K. Vrudhula, Niranjan Kulkarni, Krzysztof S. Berezowski:
Identification of Threshold Functions and Synthesis of Threshold Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 665-677 (2011)
2000 – 2009
- 2009
- [c1]Radim Belohlávek, Niranjan Kulkarni, Vilém Vychodil:
A Novel Approach to Cell Formation. ICFCA 2009: 210-223
Coauthor Index
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