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ORCIDMartin Margala
Person information
- affiliation: University of Louisiana at Lafayette, LA, USA
- affiliation (former): University of Massachusetts Lowell, USA
- affiliation (former): University of Rochester, New York, USA
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2020 – today
- 2023
[j33]Sudheer Mangalampalli
, Sangram Keshari Swain, Tulika Chakrabarti, Prasun Chakrabarti, Ganesh Reddy Karri, Martin Margala, Bhuvan Unhelkar, Sivaneasan Bala Krishnan:
Prioritized Task-Scheduling Algorithm in Cloud Computing Using Cat Swarm Optimization. Sensors 23(13): 6155 (2023)- [c116]Mohamed El-Hadedy, Russell Hua, Kazutomo Yoshii, Wen-Mei Hwu, Martin Margala:
RECO-LFSR: Reconfigurable Low-power Cryptographic processor based on LFSR for Trusted IoT platforms. ISQED 2023: 1-7 - [c115]Manisha G, Amit Krishna Dwivedi, Uma Maheshwari V, Prasun Chakrabarti, Martin Margala:
Optimum Supply Voltage for High Gain Amplifier in Telemetry Circuitry for Ultra-Low Power Implantable Cardiac Pacemaker. NEWCAS 2023: 1-5 - 2022
- [c114]Shachi Khadilkar, Martin Margala:
Optimizing open-source FPGA CAD tools. HPEC 2022: 1-4 - [c113]Sharath Patil, Bhanu Singh, Raunak Borwankar, Martin Margala:
Novel Pulse Detection System Using Differentiation: Prototyping and Experimental Results. NEWCAS 2022: 45-49 - [c112]Sharath Patil, Bhanu Singh, Raunak Borwankar, Martin Margala:
Novel Pulse Detection System Using Differentiation: Optical Experimental Results. SOCC 2022: 1-5 - [c111]Uchechukwu Leo Udeji, Martin Margala:
FPGA Implementation of Addition-based CORDIC-SNN With Izhikevich Neurons. SOCC 2022: 1-6 - 2020
- [j32]Wim Vanderbauwhede, Sven-Bodo Scholz, Martin Margala:
FPGAs for Domain Experts. Int. J. Reconfigurable Comput. 2020: 2725809:1-2725809:2 (2020) - [c110]Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala:
Automated Hardware and Neural Network Architecture co-design of FPGA accelerators using multi-objective Neural Architecture Search. ICCE-Berlin 2020: 1-6 - [c109]Mohamed El-Hadedy, Martin Margala, Sergiu Mosanu, Danilo Gligoroski, Jinjun Xiong, Wen-Mei Hwu:
Micro - GAGE: A Low-power Compact GAGE Hash Function Processor for IoT Applications. ICECS 2020: 1-4 - [c108]Philip Colangelo, Shayan Sengupta, Martin Margala:
Sparse Persistent GEMM Accelerator using OpenCL for Intel FPGAs. ISCAS 2020: 1-6 - [c107]Sharath Patil, Bhanu Singh, Darrell Livezey, Saad Ahmad, Martin Margala:
Functional Safety of a Lidar Sensor System. MWSCAS 2020: 45-48 - [c106]Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala:
AutoML for Multilayer Perceptron and FPGA Co-design. SoCC 2020: 265-266 - [i6]Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala:
AutoML for Multilayer Perceptron and FPGA Co-design. CoRR abs/2009.06156 (2020)
2010 – 2019
- 2019
- [c105]Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala:
Artificial Neural Network and Accelerator Co-design using Evolutionary Algorithms. HPEC 2019: 1-8 - [c104]Sharath Patil, Volodymyr Seliuchenko, Darrell Livezey, Saad Ahmad, Bhanu Singh, Martin Margala:
Echo Detection Using Differentiation for Compact LIDAR Implementation. MWSCAS 2019: 85-88 - [i5]Philip Colangelo, Oren Segal, Alexander Speicher, Martin Margala:
Evolutionary Cell Aided Design for Neural Network Architectures. CoRR abs/1903.02130 (2019) - 2018
- [j31]Aydin Dirican, Cagatay Ozmen, Martin Margala:
Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators. J. Electron. Test. 34(4): 405-415 (2018) - [j30]Hieu Nguyen, Rod Comer, Phuc Pham, Martin Margala:
5-Gb/s linear re-driver in 180 nm CMOS technology. Microelectron. J. 82: 81-91 (2018) - [j29]Huan Wang, Ronald W. Knepper, Jean-François Millithaler, Martin Margala:
A Novel Terahertz Ballistic Deflection Transistor Travelling Wave Amplifier System. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1435-1439 (2018) - [c103]Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis:
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. FCCM 2018: 73-80 - [c102]Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis:
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). FPGA 2018: 294 - [c101]Aydin Dirican, Cagatay Ozmen, Martin Margala:
A droop measurement built-in self-test circuit for digital low-dropout regulators. ISQED 2018: 8-13 - [c100]Huan Wang, Jean-François Millithaler, Ronald W. Knepper, Martin Margala:
Terahertz travelling wave amplifier design using Ballistic Deflection Transistor. ISQED 2018: 201-206 - [c99]Huan Wang, Jean-François Millithaler, Martin Margala, Ronald W. Knepper:
THz Ballistic Deflection Transistor Travelling Wave Amplifier Design with THz Ring Hybrid Coupler. NEWCAS 2018: 83-86 - [i4]Philip Colangelo, Nasibeh Nasiri, Asit K. Mishra, Eriko Nurvitadhi, Martin Margala, Kevin Nealis:
Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. CoRR abs/1806.11547 (2018) - 2017
- [j28]Mohamed El-Hadedy, Xinfei Guo, Martin Margala, Mircea R. Stan, Kevin Skadron:
Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems. J. Signal Process. Syst. 88(2): 167-184 (2017) - [c98]Cagatay Ozmen, Aydin Dirican, Hieu Nguyen, Martin Margala:
Column-wise ROIC design with on-chip calibration for photoresistive image sensor. ECCTD 2017: 1-4 - [c97]Philip Colangelo, Randy Huang, Enno Lübbers, Martin Margala, Kevin Nealis:
Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA. FCCM 2017: 135 - [c96]Pilin Junsangsri, Fabrizio Lombardi, Salin Junsangsri, Martin Margala:
Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits. ACM Great Lakes Symposium on VLSI 2017: 11-16 - [c95]Philip Colangelo, Enno Lübbers, Randy Huang, Martin Margala, Kevin Nealis:
Application of convolutional neural networks on Intel® Xeon® processor with integrated FPGA. HPEC 2017: 1-7 - [c94]Poorna Marthi, Nazir Hossain, Huan Wang, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González:
A high performance Full Adder based on Ballistic Deflection Transistor technology. ISCAS 2017: 1-4 - [c93]Cagatay Ozmen, Aydin Dirican, Hieu Nguyen, Martin Margala:
Sensitivity improvement of a photoresistive image sensor with novel programmable dual element readout and calibration method. MWSCAS 2017: 883-886 - [c92]Cagatay Ozmen, Aydin Dirican, Hieu Nguyen, Martin Margala:
ROIC Design for a 10k Pixel Photoresistive Image Sensor with On-Chip Calibration. NGCAS 2017: 105-108 - 2016
- [j27]Hieu Nguyen, Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Martin Margala:
A CMOS Ripple Detector for Voltage Regulator Testing. J. Electron. Test. 32(2): 227-233 (2016) - [j26]Poorna Marthi, Nazir Hossain, Huan Wang, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González:
Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(12): 2236-2244 (2016) - [j25]Zhuo Qian, Martin Margala:
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units. IEEE Trans. Very Large Scale Integr. Syst. 24(9): 3008-3012 (2016) - [c91]Poorna Marthi, Sheikh Rufsan Reza, Nazir Hossain, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González:
Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits. ACM Great Lakes Symposium on VLSI 2016: 393-396 - [c90]Oren Segal, Martin Margala:
Exploring the performance benefits of heterogeneity and reconfigurable architectures in a commodity cloud. HPCS 2016: 132-139 - [c89]Poorna Marthi, Nazir Hossain, Jean-François Millithaler, Martin Margala:
A new level sensitive D Latch using Ballistic nanodevices. ISCAS 2016: 1882-1885 - [c88]Nasibeh Nasiri, Philip Colangelo, Oren Segal, Martin Margala, Wim Vanderbauwhede:
Document classification systems in heterogeneous computing environments. PATMOS 2016: 291-295 - [e4]Ayse K. Coskun, Martin Margala, Laleh Behjat, Jie Han:
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016. ACM 2016, ISBN 978-1-4503-4274-2 [contents] - [i3]Oren Segal, Nasibeh Nasiri, Martin Margala:
A Foray into Efficient Mapping of Algorithms to Hardware Platforms on Heterogeneous Systems. CoRR abs/1605.04582 (2016) - 2015
- [c87]Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Hieu Nguyen, Martin Margala:
A CMOS ripple detector for integrated voltage regulator testing. DFTS 2015: 147-150 - [c86]Zhuo Qian, Martin Margala:
A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only). FPGA 2015: 273 - [c85]Nasibeh Nasiri, Oren Segal, Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti:
High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only). FPGA 2015: 274 - [c84]Oren Segal, Philip Colangelo, Nasibeh Nasiri, Zhuo Qian, Martin Margala:
Aparapi-UCores: A high level programming framework for unconventional cores. HPEC 2015: 1-6 - [c83]Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Hieu Nguyen, Martin Margala:
A CMOS ripple detector for integrated voltage regulator testing. MWSCAS 2015: 1-4 - [e3]Alex K. Jones, Hai (Helen) Li, Ayse K. Coskun, Martin Margala:
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015. ACM 2015, ISBN 978-1-4503-3474-7 [contents] - [e2]Alex Orailoglu, H. Fatih Ugurdag, Luís Miguel Silveira, Martin Margala, Ricardo Reis:
VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 461, Springer 2015, ISBN 978-3-319-23798-5 [contents] - [i2]Oren Segal, Philip Colangelo, Nasibeh Nasiri, Zhuo Qian, Martin Margala:
SparkCL: A Unified Programming Framework for Accelerators on Heterogeneous Clusters. CoRR abs/1505.01120 (2015) - 2014
- [c82]Zhuo Qian, Nasibeh Nasiri, Oren Segal, Martin Margala:
FPGA implementation of low-power split-radix FFT processors. FPL 2014: 1-2 - [c81]Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright:
High level programming framework for FPGAs in the data center. FPL 2014: 1-4 - [c80]Zhuo Qian, Martin Margala:
A novel low-power and in-place split-radix FFT processor. ACM Great Lakes Symposium on VLSI 2014: 81-82 - [c79]Oren Segal, Nasibeh Nasiri, Martin Margala, Wim Vanderbauwhede:
High level programming of FPGAs for HPC and data centric applications. HPEC 2014: 1-3 - [c78]Nasibeh Nasiri, Oren Segal, Martin Margala:
Modified fused multiply-accumulate chained unit. MWSCAS 2014: 889-892 - [c77]Zhuo Qian, Martin Margala:
Low power RAM-based hierarchical CAM on FPGA. ReConFig 2014: 1-4 - [i1]Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright:
High Level Programming for Heterogeneous Architectures. CoRR abs/1408.4964 (2014) - 2013
- [j24]Wim Vanderbauwhede, Anton Frolov, Sai Rahul Chalamalasetti, Martin Margala:
A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification. SIGARCH Comput. Archit. News 41(5): 53-58 (2013) - [j23]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede:
Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1346-1350 (2013) - [j22]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede:
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1915-1927 (2013) - [c76]Wim Vanderbauwhede, Anton Frolov, Leif Azzopardi, Sai Rahul Chalamalasetti, Martin Margala:
High throughput filtering using FPGA-acceleration. CIKM 2013: 1245-1248 - [c75]Sai Rahul Chalamalasetti, Kevin T. Lim, Mitch Wright, Alvin AuYoung, Parthasarathy Ranganathan, Martin Margala:
An FPGA memcached appliance. FPGA 2013: 245-254 - [c74]Samed Maltabas, Osman Kubilay Ekekon, Kemal Kulovic, Anne Meixner, Martin Margala:
An IDDQ BIST approach to characterize phase-locked loop parameters. VTS 2013: 1-6 - [e1]Martin Margala, Ricardo Augusto da Luz Reis, Alex Orailoglu, Luigi Carro, Luís Miguel Silveira, H. Fatih Ugurdag:
21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013. IEEE 2013, ISBN 978-1-4799-0522-5 [contents] - 2012
- [j21]Kemal Kulovic, Martin Margala:
Time-Based Embedded Test Instrument with Concurrent Voltage Measurement Capability. J. Electron. Test. 28(5): 653-671 (2012) - [j20]Samed Maltabas, Kemal Kulovic, Martin Margala:
Novel Practical Built-in Current Sensors. J. Electron. Test. 28(5): 673-683 (2012) - [j19]Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Martin Margala:
Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application. Int. J. Reconfigurable Comput. 2012: 507173:1-507173:16 (2012) - [j18]Sohan Purohit, Martin Margala:
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1327-1331 (2012) - [c73]Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede, Mitch Wright, Parthasarathy Ranganathan:
Evaluating FPGA-acceleration for real-time unstructured search. ISPASS 2012: 200-209 - [c72]Kemal Kulovic, Samed Maltabas, Martin Margala:
Design-for-test methodologies for current tests in Analog/Mixed-Signal Power SOCs. MWSCAS 2012: 1056-1059 - 2011
- [c71]Osman Kubilay Ekekon, Samed Maltabas, Martin Margala:
A multi-GHz PLL Built-In jitter extraction circuit for deep submicron technologies. ECCTD 2011: 657-660 - [c70]Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala:
A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks. HPCS 2011: 461-467 - 2010
- [j17]Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede:
Radiation-Hardened Reconfigurable Array With Instruction Roll-Back. IEEE Embed. Syst. Lett. 2(4): 123-126 (2010) - [j16]Sohan Purohit, Marco Lanuzza, Martin Margala:
Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. J. Low Power Electron. 6(4): 469-481 (2010) - [c69]Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, Svein J. Knapskog:
Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform. IAS 2010: 44-47 - [c68]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala:
Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths. AHS 2010: 59-65 - [c67]Mohamed El-Hadedy, Sohan Purohit, Martin Margala, Svein J. Knapskog:
Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems. AHS 2010: 113-120 - [c66]Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit:
A C++-embedded Domain-Specific Language for programming the MORA soft processor array. ASAP 2010: 141-148 - [c65]Samed Maltabas, Osman Kubilay Ekekon, Martin Margala:
A new built-in IDDQ testing method using programmable BICS. ETS 2010: 264 - [c64]Vikas Kaushal, Ignacio Iñiguez-de-la-Torre, Martin Margala:
Topology impact on the room temperature performance of THz-range ballistic deflection transistors. ACM Great Lakes Symposium on VLSI 2010: 159-162 - [c63]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala:
Design of self correcting radiation hardened digital circuits using decoupled ground bus. ACM Great Lakes Symposium on VLSI 2010: 405-408 - [c62]Sohan Purohit, David Harrington, Martin Margala:
An area efficient design methodology for SEU tolerant digital circuits. ISCAS 2010: 981-984 - [c61]Osman Kubilay Ekekon, Samed Maltabas, Martin Margala:
Novel programmable built-in current-sensor for analog, digital and mixed-signal circuits. ISCAS 2010: 3545-3548 - [c60]Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, Svein J. Knapskog:
Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform. ReConFig 2010: 394-399 - [c59]Osman Kubilay Ekekon, Samed Maltabas, Martin Margala, Ugur Çilingiroglu:
Power minimization methodology for VCTL topologies. SoCC 2010: 330-333
2000 – 2009
- 2009
- [j15]Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. J. Low Power Electron. 5(3): 326-338 (2009) - [c58]Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede:
MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor. AHS 2009: 389-396 - [c57]Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit:
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor. ERSA 2009: 195-201 - [c56]Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala:
A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model. FPL 2009: 534-538 - [c55]Vikas Kaushal, Quentin Diduck, Martin Margala:
Study of leakage current mechanisms in ballistic deflection transistors. ACM Great Lakes Symposium on VLSI 2009: 165-168 - [c54]Samed Maltabas, Martin Margala, Ugur Çilingiroglu:
Varicap threshold logic. ACM Great Lakes Symposium on VLSI 2009: 239-244 - [c53]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala:
A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic. ACM Great Lakes Symposium on VLSI 2009: 433-436 - [c52]Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello:
New performance/power/area efficient, reliable full adder design. ACM Great Lakes Symposium on VLSI 2009: 493-498 - [c51]David Wolpert, Hiroshi Irie, Roman Sobolewski, Paul Ampadu, Quentin Diduck, Martin Margala:
Ballistic Deflection Transistors and the Emerging Nanoscale Era. ISCAS 2009: 61-64 - [c50]Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design 2009: 45-50 - 2008
- [j14]John C. Liobe, Richard Geisler, Martin Margala:
A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(9): 2491-2504 (2008) - [c49]Kevin Sliech, Martin Margala:
A Digital BIST for Phase-Locked Loops. DFT 2008: 134-142 - [c48]Michael Wieckowski, Martin Margala:
A portless SRAM Cell using stunted wordline drivers. ISCAS 2008: 584-587 - [c47]Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. PATMOS 2008: 297-306 - [c46]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello:
Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. ReConFig 2008: 217-222 - [c45]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello:
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. SoCC 2008: 375-378 - 2007
- [j13]Michael Wieckowski, Sandeep Patil, Martin Margala:
Portless SRAM - A High-Performance Alternative to the 6T Methodology. IEEE J. Solid State Circuits 42(11): 2600-2610 (2007) - [j12]John C. Liobe, Martin Margala:
Novel Process and Temperature-Stable, IDD Sensor for the BIST Design of Embedded Digital, Analog, and Mixed-Signal Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(9): 1900-1915 (2007) - [j11]Brandon J. Jasionowski, Michelle K. Lay, Martin Margala:
A Processor-In-Memory Architecture for Multimedia Compression. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 478-483 (2007) - [c44]Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. AHS 2007: 119-126 - [c43]John C. Liobe, Martin Margala:
Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal Test. IOLTS 2007: 231-236 - [c42]Sandeep Patil, Michael Wieckowski, Martin Margala:
A Self-Biased Charge-Transfer Sense Amplifier. ISCAS 2007: 3030-3033 - [c41]Richard Geisler, John C. Liobe, Martin Margala:
Process and Temperature Calibration of PLLs with BiST Capabilities. ISCAS 2007: 3864-3867 - 2006
- [j10]Dan Zhao, Shambhu J. Upadhyaya, Martin Margala:
Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1411-1418 (2006) - [c40]Martin Margala:
Adaptable Architectures for Signal Processing Applications. AHS 2006: 247-254 - [c39]Yuxin Wang, Martin Margala:
New Embedded Core Testing for System-on-Chips and System-in-Packages. CCECE 2006: 1897-1900 - [c38]