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2020 – today
- 2023
[c75]Kuo-Hsing Cheng, Chun-Yao Chang, Hong-Yi Huang, Yun-Teng Shih:
A Low Power 16 Gbps CTLE and Quarter-Rate DFE With Single Adaptive System. ICECS 2023: 1-4- [c74]Hong-Yi Huang, Yu-Ming Tsao, Angelo Nico M. Daroy, Kuo-Hsing Cheng:
A 1~50mA 20ns Settling Time Low Dropout Regulator. ICECS 2023: 1-4 - 2021
- [j28]Chih-Wei Tsai
, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng:
A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications. IEEE Trans. Very Large Scale Integr. Syst. 29(10): 1720-1729 (2021)
2010 – 2019
- 2019
- [c73]Tsung-Han Tsai, Po-Ting Chi, Kuo-Hsing Cheng:
A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded System. DDECS 2019: 1-4 - 2018
- [j27]Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Chi-Yang Chang:
Low supply voltage and multiphase all-digital crystal-less clock generator. IET Circuits Devices Syst. 12(6): 720-725 (2018) - [j26]Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, Jen-Chieh Liu:
A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2097-2108 (2018) - [c72]Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng:
A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application. ISCAS 2018: 1-4 - 2017
- [c71]Yo-Hao Tu, Kai-Wen Yao, Minghao Huang, Yu-Yun Lin, Hao-Yu Chi, Po-Min Cheng, Pei-Yun Tsai, Muh-Tian Shiue, Chien-Nan Liu, Kuo-Hsing Cheng, Jia-Shiang Fu:
A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering. VLSI-DAT 2017: 1-4 - 2016
- [j25]Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu:
A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. IEICE Electron. Express 13(2): 20150950 (2016) - [j24]Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng:
Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture. IEICE Trans. Electron. 99-C(6): 655-658 (2016) - [c70]Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang:
A chaotically injected timing technique for ring-based oscillators. DDECS 2016: 31-34 - [c69]Hong-Yi Huang, Kun-Yuan Chen, Jia-Hao Xie, Ming-Ta Lee, Hao-Chiao Hong, Kuo-Hsing Cheng:
Gm-C filter with automatic calibration scheme. DDECS 2016: 206-209 - [c68]Hong-Yi Huang, Shao-Zu Yen, Jhen-Hong Chen, Hao-Chiao Hong, Kuo-Hsing Cheng:
Low-voltage indoor energy harvesting using photovoltaic cell. DDECS 2016: 223-226 - 2015
- [c67]Yo-Hao Tu, Kuo-Hsing Cheng, Yian-An Lin, Hong-Yi Huang:
A Synchronous Mirror Delay with Duty-Cycle Tunable Technology. DDECS 2015: 79-82 - [c66]Hong-Yi Huang, Jen-Chieh Liu, Pei-Ying Lee, Kun-Yuan Chen, Jin-Sheng Chen, Kuo-Hsing Cheng, Tzuen-Hsi Huang, Ching-Hsing Luo, Jin-Chern Chiou:
PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing. DDECS 2015: 125-128 - 2014
- [j23]Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun:
A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 559-563 (2014) - [c65]Hong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, Kuo-Hsing Cheng:
A 64-MHz∼640-MHz 64-phase clock generator. DDECS 2014: 51-54 - [c64]Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, Hong-Yi Huang:
A low supply voltage synchronous mirror delay with quadrature phase output. DDECS 2014: 163-166 - 2013
- [c63]Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, Hong-Yi Huang:
A low jitter delay-locked-loop applied for DDR4. DDECS 2013: 98-101 - [c62]Hong-Yi Huang, Chinet Otic Mocorro, Julyver Pinaso, Kuo-Hsing Cheng:
Indoor energy harvesting using photovoltaic cell for battery recharging. DDECS 2013: 224-227 - [c61]Hong-Yi Huang, Cheng-Yu Chen, Kuo-Hsing Cheng:
External capacitorless low dropout linear regulator using cascode structure. DDECS 2013: 236-239 - 2012
- [j22]Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Yu-Sheng Chen, Pang-Shiu Chen, Ming-Jinn Tsai, Yu-Lung Lo:
A 50 ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit. IEICE Trans. Electron. 95-C(6): 1128-1131 (2012) - [j21]Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang:
A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 888-892 (2012) - [j20]Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Fa Hsu, Bo-Qian Jiang:
An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1818-1827 (2012) - [c60]Chih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng:
Auto-calibration techniques in built-in jitter measurement circuit. DDECS 2012: 248-249 - [c59]Bo-Qian Jiang, Cheng-Liang Hung, Bing-Hung Chen, Kuo-Hsing Cheng:
A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-µm CMOS technology. ISCAS 2012: 2597-2600 - 2011
- [j19]Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Meng-Fan Chang, Pei-Chia Chiang, Wen-Pin Lin, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Frederick T. Chen, Ming-Jinn Tsai:
Fast-Write Resistive RAM (RRAM) for Embedded Applications. IEEE Des. Test Comput. 28(1): 64-71 (2011) - [j18]Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang:
A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique. IEEE J. Solid State Circuits 46(5): 1198-1213 (2011) - [j17]Kuo-Hsing Cheng, Yu-Chang Tsai, Yu-Lung Lo, Jing-Shiuan Huang:
A 0.5-V 0.4-2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(5): 849-859 (2011) - [j16]Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang, Yu-Liang Li, Yong-Jhen Jhu:
A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler. IEEE Trans. Circuits Syst. II Express Briefs 58-II(8): 492-496 (2011) - [j15]Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, Jen-Chieh Liu:
A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1218-1228 (2011) - [j14]Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, Kai-Wei Hong:
Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1325-1335 (2011) - [c58]Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, Che-hao Fan, Chi-Yang Chang:
A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation. ESSCIRC 2011: 447-450 - [c57]Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, Ching-Hsing Luo:
All digital phase-locked loop using active inductor oscillator and novel locking algorithm. ISCAS 2011: 486-489 - [c56]Shyh-Shyuan Sheu, Meng-Fan Chang, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Peiyi Gu, Sumin Wang, Frederick T. Chen, Keng-Li Su, Chen-Hsin Lien, Kuo-Hsing Cheng, Hsin-Tun Wu, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai:
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. ISSCC 2011: 200-202 - 2010
- [j13]Kuo-Hsing Cheng, Yu-Chang Tsai, Yen-Hsueh Wu, Ying-Fu Lin:
A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications. IEEE Trans. Circuits Syst. II Express Briefs 57-II(5): 324-328 (2010) - [c55]Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang:
A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. DDECS 2010: 285-288 - [c54]Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu, Chien-Cheng Chen:
A loading effect insensitive and high precision clock synchronization circuit. ESSCIRC 2010: 514-517 - [c53]Yu-Chang Tsai, Kuo-Hsing Cheng, Yen-Hsueh Wu, Ying-Fu Lin:
A CMOS adaptive equalizer using low-voltage zero generators technique. ESSCIRC 2010: 546-549 - [c52]Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng:
A 3 GHz DLL-based clock generator with stuck locking protection. ICECS 2010: 106-109
2000 – 2009
- 2009
- [j12]Shu-Yu Jiang, Chan-Wei Huang, Yu-Lung Lo, Kuo-Hsing Cheng:
Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(2): 389-400 (2009) - [j11]Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng:
High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. IEICE Trans. Electron. 92-C(6): 890-893 (2009) - [j10]Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo:
A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application. IEICE Trans. Electron. 92-C(7): 964-972 (2009) - [j9]Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng:
Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. IEEE Trans. Circuits Syst. II Express Briefs 56-II(5): 339-343 (2009) - [j8]Shu-Yu Jiang, Kuo-Hsing Cheng, Pei-Yi Jian:
A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver. IEEE Trans. Very Large Scale Integr. Syst. 17(12): 1698-1708 (2009) - [c51]Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng:
0.5V 160-MHz 260uW all digital phase-locked loop. DDECS 2009: 186-193 - [c50]Ting-Sheng Chao, Yu-Lung Lo, Wei-Bin Yang, Kuo-Hsing Cheng:
Designing ultra-low voltage PLL Using a bulk-driven technique. ESSCIRC 2009: 388-391 - 2008
- [j7]Kuo-Hsing Cheng, Chia-Wei Su, Hsin-Hsin Ko:
Highly Accurate and Efficient Current-Mode PWM CMOS DC-DC Buck Converter with On-Chip Current-Sensing. IEICE Trans. Electron. 91-C(12): 1941-1950 (2008) - [j6]Kuo-Hsing Cheng, Chia-Wei Su, Kai-Fei Chang:
A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation. IEEE J. Solid State Circuits 43(2): 399-413 (2008) - [c49]Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw:
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. DDECS 2008: 64-67 - [c48]Kuo-Hsing Cheng, Hsin-Hao Wang, Ding-Jyun Huang:
A 1-V 10-bit 2GSample/s D/A converter based on precision current reference in 90-nm CMOS. ICECS 2008: 340-343 - [c47]Kuo-Hsing Cheng, Chia-Wei Su, Hsin-Hsin Ko:
A high-accuracy and high-efficiency on-chip current sensing for current-mode control CMOS DC-DC buck converter. ICECS 2008: 458-461 - [c46]Cihun-Siyong Alex Gong, Ci-Tong Hong, Kai-Wen Yao, Muh-Tian Shiue, Kuo-Hsing Cheng:
A compact and low-power SRAM with improved read static noise margin. ICECS 2008: 546-549 - [c45]Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, Yen-Hsueh Wu:
A low jitter self-calibration PLL for 10Gbps SoC transmission links application. ICECS 2008: 786-789 - [c44]Kuo-Hsing Cheng, Chia-Wei Su, Meng-Jhe Wu, Yu-Ling Chang:
A wide-range DLL-based clock generator with phase error calibration. ICECS 2008: 798-801 - 2007
- [j5]Kuo-Hsing Cheng, Yu-Lung Lo:
A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator. IEEE Trans. Circuits Syst. II Express Briefs 54-II(7): 561-565 (2007) - [c43]Kuo-Hsing Cheng, Pei-Kai Tseng, Yu-Lung Lo:
A Phase Interpolator For Sub-1V And High Frequency For Clock And Data Recovery. ICECS 2007: 363-366 - [c42]Kuo-Hsing Cheng, Yu-Lung Lo, Ching-Wen Lai, Wei-Bin Yang:
A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique. ICECS 2007: 1163-1166 - [c41]Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng:
All-Digital PLL Using Pulse-Based DCO. ICECS 2007: 1268-1271 - [c40]Kuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su:
A Sub-1V Low-Power High-Speed Static Frequency Divider. ISCAS 2007: 3848-3851 - 2006
- [j4]Kuo-Hsing Cheng, Shun-Wen Cheng, Wen-Shiuan Lee:
64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics. J. Circuits Syst. Comput. 15(1): 13-28 (2006) - [j3]Kuo-Hsing Cheng, Shun-Wen Cheng:
Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications. J. Inf. Sci. Eng. 22(4): 975-989 (2006) - [c39]Kuo-Hsing Cheng, Yu-Lung Lo:
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. DATE Designers' Forum 2006: 178-182 - [c38]Cihun-Siyong Alex Gong, Chen-Lung Wu, Sheng-Yang Ho, Tong-Yi Chen, Jia-Chun Huang, Chia-Wei Su, Chun-Hsien Su, Yin Chang, Kuo-Hsing Cheng, Yu-Lung Lo, Muh-Tian Shiue:
Design of Self-Sampling Based ASK Demodulator for Implantable Microsystem. ICECS 2006: 33-36 - [c37]Kai-Wei Hong, Chien-Hsien Lee, Kuo-Hsing Cheng, Chen-Lung Wu, Wei-Bin Yang:
A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay. ICECS 2006: 569-572 - [c36]Kuo-Hsing Cheng, Kai-Fei Chang, Yu-Lung Lo, Ching-Wen Lai, Yuh-Kuang Tseng:
A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process. ISCAS 2006 - [c35]Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang:
Self-sampled vernier delay line for built-in clock jitter measurement. ISCAS 2006 - 2005
- [j2]Kuo-Hsing Cheng, Shun-Wen Cheng:
64-Bit High-Performance Power-Aware Conditional Carry Adder Design. IEICE Trans. Electron. 88-C(6): 1322-1331 (2005) - [c34]Wei-Bin Yang, Shu-Chang Kuo, Yuan-Hua Chu, Kuo-Hsing Cheng:
The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. ECCTD 2005: 193-196 - [c33]Kuo-Hsing Cheng, Yu-Lung Lo:
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. ESSCIRC 2005: 189-192 - [c32]Kuo-Hsing Cheng, Chen-Lung Wu, Yu-Lung Lo, Chia-Wei Su:
A phase-detect synchronous mirror delay for clock skew-compensation circuits. ISCAS (2) 2005: 1070-1073 - [c31]Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang:
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. ISCAS (2) 2005: 1174-1177 - 2004
- [c30]Kuo-Hsing Cheng, Tsung-Shen Chen, Chia Ming Tu:
A 14-bit, 200 MS/s digital-to-analog converter without trimming. ISCAS (1) 2004: 353-358 - [c29]Kuo-Hsing Cheng, Yu-Lung Lo:
A fast-lock DLL with power-on reset circuit. ISCAS (4) 2004: 357-360 - [c28]Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang:
Static divided word matching line for low-power Content Addressable Memory design. ISCAS (2) 2004: 629-632 - [c27]Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo:
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. ISCAS (1) 2004: 777-780 - [c26]Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao:
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. ISVLSI 2004: 233-236 - [c25]Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang:
64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. IWSOC 2004: 65-68 - 2003
- [j1]Kuo-Hsing Cheng, Wei-Bin Yang, Cheng-Ming Ying:
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop. IEEE Trans. Circuits Syst. II Express Briefs 50(11): 892-896 (2003) - [c24]Kuo-Hsing Cheng, Chung-Yu Chang, Chia-Hung Wei:
A CMOS charge pump for sub-2.0 V operation. ISCAS (5) 2003: 89-92 - [c23]Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu:
A mixed-mode delay-locked loop for wide-range operation and multiphase outputs. ISCAS (2) 2003: 196-199 - [c22]Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang:
A new robust handshake for asymmetric asynchronous micro-pipelines. ISCAS (5) 2003: 209-212 - [c21]Kuo-Hsing Cheng, Yung-Hsiang Lin:
A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application. ISCAS (5) 2003: 425-428 - [c20]Kuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen:
BIST for clock jitter measurements. ISCAS (5) 2003: 577-580 - [c19]Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu:
A Robust Handshake for Asynchronous System. IWSOC 2003: 16-19 - [c18]Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu, Shu-Yin Hung:
A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation. IWSOC 2003: 90-93 - 2002
- [c17]Kuo-Hsing Cheng, Shun-Wen Cheng:
Influences of minimum cut plane properties on the mincut circuit partitioning problems. ICECS 2002: 375-379 - [c16]Kuo-Hsing Cheng, Shun-Wen Cheng:
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. ASP-DAC/VLSI Design 2002: 155-159 - 2001
- [c15]Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang, Wei-Bin Yang:
A difference detector PFD for low jitter PLL. ICECS 2001: 43-46 - [c14]Kuo-Hsing Cheng, Lin-Jiunn Tzou, Wei-Bin Yang, Shyh-Shyuan Sheu:
A CMOS low power voltage controlled oscillator with split-path controller. ICECS 2001: 421-424 - [c13]Kuo-Hsing Cheng, Chi-Che Chen, Chun-Fu Chung:
Accurate current mirror with high output impedance. ICECS 2001: 565-568 - [c12]Kuo-Hsing Cheng, Wen-Shiuan Lee, Yung-Chong Huang:
A 1.2 V 500 MHz 32-bit carry-lookahead adder. ICECS 2001: 765-768 - [c11]Kuo-Hsing Cheng, Shun-Wen Cheng:
A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning. ICECS 2001: 889-893 - [c10]Shun-Wen Cheng, Kuo-Hsing Cheng:
ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning. ISCAS (5) 2001: 167-170 - [c9]Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung:
A low-power high driving ability voltage control oscillator used in PLL. ISCAS (4) 2001: 614-617 - 2000
- [c8]Kuo-Hsing Cheng, Chih-Sheng Huang, Chun-Pin Lin:
The design and implementation of DCT/IDCT chip with novel architecture. ISCAS 2000: 741-744
1990 – 1999
- 1999
- [c7]Kuo-Hsing Cheng, Chih-Sheng Huang:
The novel efficient design of XOR/XNOR function for adder applications. ICECS 1999: 29-32 - [c6]Kuo-Hsing Cheng, Wei-Bin Yang:
The suggestion for CFS CMOS buffer. ICECS 1999: 799-802 - [r1]Kuo-Hsing Cheng:
Dynamic Random Access Memory. The VLSI Handbook 1999 - 1998
- [c5]Kuo-Hsing Cheng, Yu-Kwang Yeha, Farn-Sou Lian:
Low voltage low power high-speed BiCMOS multiplier. ICECS 1998: 49-50 - 1996
- [c4]Kuo-Hsing Cheng, Yu-Yee Liow:
A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic. ICECS 1996: 1037-1040 - 1995
- [c3]Chung-Yu Wu, Jr-Houng Lu, Kuo-Hsing Cheng:
A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications. ISCAS 1995: 25-28 - [c2]Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu:
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ISCAS 1995: 1572-1575 - 1994
- [c1]Yuh-Kuang Tseng, Kuo-Hsing Cheng, Chung-Yu Wu:
Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit. ISCAS 1994: 23-26
Coauthor Index