default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDJosé Silva-Martínez
Jose Silva-Martinez
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j98]Amr Walid
, Dadian Zhou, Jose Silva-Martinez:
Matrix-Based Digital Calibration Technique for High-Performance SAR and Pipeline ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 20-28 (2024)- [c67]Mitchell Clark, Thomas Raguso, James Alexaner, Troy Buhr, Aydin Karsilayar, Jose Silva-Martinez:
X-Band Phased-Array Transmitter Architecture with Power Transfer Optimization Algorithm for Space Solar Power System: A Case Study. MWSCAS 2024: 387-391 - [c66]Tanwei Yan, Junning Jiang, Jose Silva-Martinez:
A Fractional Spur Cancellation Technique for Fractional-N Frequency Synthesizers Enabled by Dual Loop Phase Clamping. MWSCAS 2024: 642-646 - 2023
- [j97]Troy Buhr, Aydin I. Karsilayan, Jose Silva-Martinez, Christopher T. Rodenbeck, Brian B. Tierney, Yanghyo Kim:
X-Band CMOS Rectifier With 4% Efficiency at -35 dBm for Wireless Power Transmission. IEEE Access 11: 6792-6801 (2023) - 2022
- [j96]Jian Shao, Aydin Ilker Karsilayan, Christopher T. Rodenbeck, José Silva-Martínez:
An Interference-Tolerant Synchronization Scheme for Wireless Communication Systems Based on Direct Sequence Spread Spectrum. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 415-427 (2022) - [c65]Jose Silva-Martinez, Marvin Onabajo, Ayesha Mayhugh:
A Practical and Design oriented approach to teaching circuits. ISCAS 2022: 96-100 - 2021
- [j95]José Silva-Martínez, Xiaosen Liu, Dadian Zhou:
Recent Advances on Linear Low-Dropout Regulators. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 568-573 (2021) - [c64]Thomas Janes, Seth Petrosky, Troy Buhr, Aydin I. Karsilayan, Jose Silva-Martinez, David Genzer, Vighnesh Das, Larry J. Stotts:
Thermoelectric Energy Harvesting for Implantable Medical Devices. EMBC 2021: 1547-1550 - 2020
- [j94]Dadian Zhou, Junning Jiang, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez:
A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator. IEEE J. Solid State Circuits 55(8): 2140-2150 (2020) - [j93]José Silva-Martínez, José G. Delgado-Frias:
MWSCAS Guest Editorial Special Issue Based on the 62nd International Midwest Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. 67-I(10): 3249-3250 (2020) - [j92]Chulhyun Park, Tao Chen, Kyoohyun Noh, Dadian Zhou, Suraj Prakash, Mohammadhossein Naderi Alizadeh, Aydin I. Karsilayan, Degang Chen, Randall L. Geiger, José Silva-Martínez:
A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier. IEEE Trans. Circuits Syst. 67-I(11): 3618-3629 (2020) - [j91]Jian Shao, Aydin Ilker Karsilayan, Christopher T. Rodenbeck, José Silva-Martínez:
An Efficient Sinusoid-Like Pseudo Random Sequence Modulator/Demodulator System With Reduced Adjacent Channel Leakage and High Rejection to Random and Systematic Interference. IEEE Trans. Circuits Syst. 67-I(11): 3790-3803 (2020) - [j90]Tao Chen, Chulhyun Park, Shravan K. Chaganti, José Silva-Martínez, Randall L. Geiger, Degang Chen:
An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method. IEEE Trans. Instrum. Meas. 69(3): 729-738 (2020) - [j89]Tao Chen, Chulhyun Park, Hao Meng, Dadian Zhou, José Silva-Martínez, Randall L. Geiger, Degang Chen:
A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test. IEEE Trans. Instrum. Meas. 69(6): 3516-3526 (2020) - [c63]Jusung Kim, Junning Jiang, José Silva-Martínez, Aydin Ilker Karsilayan:
A 3 to 6 GHz Highly Linear I-Channel Receiver with over +3.0 dBm In-Band P1dB and 200 MHz Baseband Bandwidth Suitable for 5G Wireless and Cognitive Radio Applications. ISCAS 2020: 1 - [c62]Juan A. Bozzo, Angel Abusleme, José Silva-Martínez:
A Blind Calibration Scheme for Switched-Capacitor Pipeline Analog-to-Digital Converters. LASCAS 2020: 1-4
2010 – 2019
- 2019
- [j88]Christopher T. Rodenbeck, Matthew Martinez, Joshua B. Beun, José Silva-Martínez, Aydin Ilker Karsilayan, Robert Liechty:
When Less Is More ... Few Bit ADCs in RF Systems. IEEE Access 7: 12035-12046 (2019) - [j87]Junning Jiang, Jusung Kim, Aydin Ilker Karsilayan, José Silva-Martínez:
A 3-6-GHz Highly Linear I-Channel Receiver With Over +3.0-dBm In-Band P1dB and 200-MHz Baseband Bandwidth Suitable for 5G Wireless and Cognitive Radio Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 3134-3147 (2019) - [j86]Mohammad H. Naderi, Chulhyun Park, Suraj Prakash, Martin Kinyua, Eric G. Soenen, José Silva-Martínez:
A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3352-3364 (2019) - [j85]Dadian Zhou, Carlos Briseno-Vidrios, Junning Jiang, Chulhyun Park, Qiyuan Liu, Eric G. Soenen, Martin Kinyua, José Silva-Martínez:
A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3373-3383 (2019) - [c61]José Silva-Martínez, Tanwei Yan, Junning Jiang, Jian Shao:
Efficient Broadband Class AB Amplifier. MWSCAS 2019: 1045-1048 - 2018
- [j84]Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, Eric G. Soenen, Martin Kinyua, José Silva-Martínez:
A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. IEEE J. Solid State Circuits 53(11): 3280-3292 (2018) - [j83]Mohammad H. Naderi, Suraj Prakash, José Silva-Martínez:
Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3769-3779 (2018) - [j82]Qiyuan Liu, Alexander Edward, Dadian Zhou, José Silva-Martínez:
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 756-767 (2018) - [j81]John S. Mincey, Eric C. Su, José Silva-Martínez, Christopher T. Rodenbeck:
A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1192-1203 (2018) - [c60]Venkatraman Natarajan, Mohammad H. Naderi, José Silva-Martínez:
Low noise RF quadrature VCO using tail-switch network-based coupling in 40 nm CMOS. CICC 2018: 1-4 - 2017
- [j80]Alexander Edward, Qiyuan Liu, Carlos Briseno-Vidrios, Martin Kinyua, Eric G. Soenen, Aydin Ilker Karsilayan, José Silva-Martínez:
A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS. IEEE J. Solid State Circuits 52(2): 448-459 (2017) - [j79]Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez:
A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage. IEEE J. Solid State Circuits 52(3): 657-668 (2017) - [j78]Qiyuan Liu, Alexander Edward, Martin Kinyua, Eric G. Soenen, José Silva-Martínez:
A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques. IEEE J. Solid State Circuits 52(6): 1591-1604 (2017) - [j77]John S. Mincey, Carlos Briseno-Vidrios, José Silva-Martínez, Christopher T. Rodenbeck:
Low-Power Gm-C Filter Employing Current-Reuse Differential Difference Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 635-639 (2017) - [j76]Jun Zhou, Amir Tofighi Zavareh, Robin Gupta, Liang Liu, Zhongfeng Wang, Brian M. Sadler, José Silva-Martínez, Sebastian Hoyos:
Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2495-2507 (2017) - [j75]Haoyu Qian, José Silva-Martínez:
Multitone ACLR and Its Applications to Linear PA Design. IEEE Trans. Circuits Syst. II Express Briefs 64-II(10): 1177-1181 (2017) - [c59]Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, José Silva-Martínez:
A 13bit 200MS/S pipeline ADC with current-mode MDACs. ISCAS 2017: 1-4 - [c58]Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Negar Rashidi, José Silva-Martínez:
High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications. MWSCAS 2017: 297-300 - [c57]Aditya Bommireddipalli, Dadian Zhou, Claudio Talarico, José Silva-Martínez, Aydin I. Karsilayan:
A 200MSPS time-interleaved 12-bit ADC system with digital calibration. MWSCAS 2017: 1184-1187 - [c56]Mohammad H. Naderi, José Silva-Martínez:
Algorithmic-pipelined ADC with a modified residue curve for better linearity. MWSCAS 2017: 1446-1449 - 2016
- [j74]Haoyu Qian, Qiyuan Liu, José Silva-Martínez, Sebastian Hoyos:
A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS. IEEE J. Solid State Circuits 51(3): 587-597 (2016) - [j73]Carlos Briseno-Vidrios, Alexander Edward, Negar Rashidi, José Silva-Martínez:
A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer. IEEE J. Solid State Circuits 51(6): 1398-1409 (2016) - [c55]Dadian Zhou, Claudio Talarico, José Silva-Martínez:
A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration. SoCC 2016: 13-17 - 2015
- [j72]Hemasundar Mohan Geddada, Chang-Joon Park, Hyung-Joon Jeon, José Silva-Martínez, Aydin Ilker Karsilayan, Douglas Garrity:
Design Techniques to Improve Blocker Tolerance of Continuous-Time ΔΣ ADCs. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 54-67 (2015) - [j71]Hyung-Joon Jeon, José Silva-Martínez, Sebastian Hoyos:
A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 198-202 (2015) - [j70]Chang-Joon Park, Marvin Onabajo, Hemasundar Mohan Geddada, Aydin Ilker Karsilayan, José Silva-Martínez:
Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma-Delta Modulators. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1920-1930 (2015) - [c54]Yung-Chung Lo, Negar Rashidi, Yin-Huan Hwang, José Silva-Martínez:
A 0.6ps jitter 2-16 GHz 130nm CMOS frequency synthesizer for broadband applications. ISCAS 2015: 3048-3051 - [c53]Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez:
A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique. VLSIC 2015: 254- - 2014
- [j69]Chang-Joon Park, Marvin Onabajo, José Silva-Martínez:
External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4-4 MHz Range. IEEE J. Solid State Circuits 49(2): 486-501 (2014) - [j68]Alexander Edward, José Silva-Martínez:
General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators. IEEE Trans. Circuits Syst. II Express Briefs 61-II(7): 506-510 (2014) - [c52]Haoyu Qian, José Silva-Martínez:
A 44.9% PAE digitally-assisted linear power amplifier in 40 nm CMOS. A-SSCC 2014: 349-352 - [c51]José Silva-Martínez, Edgar Sánchez-Sinencio, José G. Delgado-Frias, Randall L. Geiger:
Welcome to MWSCAS 2014. MWSCAS 2014: 1-2 - [c50]Chang-Joon Park, José Silva-Martínez, Marvin Onabajo:
Design techniques for external capacitor-less LDOs with high PSR over wide frequency range. MWSCAS 2014: 342-345 - [c49]Hemasundar Mohan Geddada, Chang-Joon Park, José Silva-Martínez, Aydin Ilker Karsilayan:
Blocker tolerant wideband continuous time sigma-delta modulator for wireless applications. MWSCAS 2014: 765-768 - [c48]Saiteja Damera, Aydin Ilker Karsilayan, José Silva-Martínez:
Design of minimally-invasive all-pole analog lowpass filters. MWSCAS 2014: 1025-1028 - [c47]Josep Altet, Eduardo Aldrete-Vidrio, Ferran Reverter, Didac Gómez, José Luis González, Marvin Onabajo, José Silva-Martínez, B. Martineau, X. Perpiñà, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Xavier Aragonès, Xavier Jordà, Miquel Vellvehí, Stefan Dilhaire, Salvador Mir, Diego Mateo:
Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes. MWSCAS 2014: 1081-1084 - 2013
- [j67]Hyung-Joon Jeon, Raghavendra Kulkarni, Yung-Chung Lo, Jusung Kim, José Silva-Martínez:
A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy. IEEE J. Solid State Circuits 48(6): 1398-1415 (2013) - [j66]Jusung Kim, José Silva-Martínez:
Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications. IEEE J. Solid State Circuits 48(9): 2090-2103 (2013) - [j65]Carlos Zamarreño-Ramos, Raghavendra Kulkarni, José Silva-Martínez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings. IEEE Trans. Biomed. Circuits Syst. 7(5): 722-731 (2013) - [j64]Kyu-Nam Shim, Jiang Hu, José Silva-Martínez:
Dual-Level Adaptive Supply Voltage System for Variation Resilience. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1041-1052 (2013) - [c46]Chang-Joon Park, Hemasundar Mohan Geddada, Aydin I. Karsilayan, José Silva-Martínez, Marvin Onabajo:
A current-mode flash ADC for low-power continuous-time sigma delta modulators. ISCAS 2013: 141-144 - [c45]Saikrishna Ganta, Chang-Joon Park, Daniel Gitzel, Rafael Rivera, José Silva-Martínez:
An external capacitor-less low drop-out regulator with superior PSR and fast transient response. MWSCAS 2013: 137-140 - [c44]Daniel Gitzel, Rafael Rivera, José Silva-Martínez:
Robust compensation scheme for low power capacitor-less low dropout voltage regulator. MWSCAS 2013: 481-484 - [c43]Richard Turkson, Suraj Prakash, José Silva-Martínez, Herminio Martínez-Garcia:
Envelope tracking technique with bang-bang slew-rate enhancer for linear wideband RF PAs. MWSCAS 2013: 629-632 - [c42]Andreas Larsson, José Silva-Martínez:
Efficient calibration scheme for high-resolution pipelined ADCs. MWSCAS 2013: 661-664 - 2012
- [j63]Xi Chen, Ehab Ahmed Sobhy, Zhuizhuan Yu, Sebastian Hoyos, José Silva-Martínez, Samuel Palermo, Brian M. Sadler:
A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-End. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(3): 542-551 (2012) - [j62]Ahmed A. Helmy, Hyung-Joon Jeon, Yung-Chung Lo, Andreas J. Larsson, Raghavendra Kulkarni, Jusung Kim, José Silva-Martínez, Kamran Entesari:
A Self-Sustained CMOS Microwave Chemical Sensor Using a Frequency Synthesizer. IEEE J. Solid State Circuits 47(10): 2467-2483 (2012) - [j61]Haitao Tong, Shanfeng Cheng, Yung-Chung Lo, Aydin I. Karsilayan, José Silva-Martínez:
An LC Quadrature VCO Using Capacitive Source Degeneration Coupling to Eliminate Bi-Modal Oscillation. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1871-1879 (2012) - [j60]Raghavendra Kulkarni, Jusung Kim, Hyung-Joon Jeon, Jianhong Xiao, José Silva-Martínez:
UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 197-210 (2012) - [c41]José Silva-Martínez, Aydin Ilker Karsilayan, Hemasundar Mohan Geddada:
Blocker and jitter tolerant wideband ΣΔ modulators. MWSCAS 2012: 390-393 - [c40]Kunmo Kim, José Silva-Martínez:
Low-power 3rd-order continuous-time low-pass sigma-delta analog-to-digital converter for wideband applications. MWSCAS 2012: 814-817 - 2011
- [j59]Marvin Onabajo, Didac Gómez, Eduardo Aldrete-Vidrio, Josep Altet, Diego Mateo, José Silva-Martínez:
Survey of Robustness Enhancement Techniques for Wireless Systems-on-a-Chip and Study of Temperature as Observable for Process Variations. J. Electron. Test. 27(3): 225-240 (2011) - [j58]Vijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz:
A Continuous Time Multi-Bit Delta Sigma ADC Using Time Domain Quantizer and Feedback Element. IEEE J. Solid State Circuits 46(3): 639-650 (2011) - [j57]Mohamed M. Elsayed, Vijay Dhanasekaran, Manisha Gambhir, José Silva-Martínez, Edgar Sánchez-Sinencio:
A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator. IEEE J. Solid State Circuits 46(9): 2084-2098 (2011) - [j56]Sebastian Hoyos, Srikanth Pentakota, Zhuizhuan Yu, Ehab Sobhy Abdel Ghany, Xi Chen, Ramy Saad, Samuel Palermo, José Silva-Martínez:
Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(2): 253-263 (2011) - [j55]Marvin Onabajo, Josep Altet, Eduardo Aldrete-Vidrio, Diego Mateo, José Silva-Martínez:
Electrothermal Design Procedure to Observe RF Circuit Power and Linearity Characteristics With a Homodyne Differential Temperature Sensor. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(3): 458-469 (2011) - [j54]Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, Brian M. Sadler, José Silva-Martínez:
A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(3): 507-520 (2011) - [j53]Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, Brian M. Sadler, José Silva-Martínez:
Corrections to "A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing". IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(11): 2801 (2011) - [c39]Hemasundar Mohan Geddada, José Silva-Martínez, Stewart S. Taylor:
Fully balanced low-noise transconductance amplifiers with P1dB > 0dBm in 45nm CMOS. ESSCIRC 2011: 231-234 - [c38]Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Raghavendra Kulkarni, José Silva-Martínez:
Voltage mode driver for low power transmission of high speed serial AER Links. ISCAS 2011: 2433-2436 - 2010
- [j52]Mohamed Mobarak, Marvin Onabajo, José Silva-Martínez, Edgar Sánchez-Sinencio:
Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications. IEEE J. Solid State Circuits 45(2): 351-367 (2010) - [j51]Cho-Ying Lu, Jose Fabian Silva-Rivas, Praveena Kode, José Silva-Martínez, Sebastian Hoyos:
A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth. IEEE J. Solid State Circuits 45(6): 1122-1136 (2010) - [j50]Cho-Ying Lu, Marvin Onabajo, Venkata Gadde, Yung-Chung Lo, Hsien-Pu Chen, Vijayaramalingam Periasamy, José Silva-Martínez:
A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback. IEEE J. Solid State Circuits 45(9): 1795-1808 (2010) - [c37]Raghavendra Kulkarni, Jusung Kim, Hyung-Joon Jeon, José Silva-Martínez, Jianhong Xiao:
A broadband 470-862 MHz direct conversion CMOS receiver. ISCAS 2010: 2227-2230 - [c36]Kyu-Nam Shim, Jiang Hu, José Silva-Martínez:
A dual-level adaptive supply voltage system for variation resilience. ISQED 2010: 38-43
2000 – 2009
- 2009
- [j49]Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio:
Design of Three-Stage Class-AB 16ΩHeadphone Driver Capable of Handling Wide Range of Load Capacitance. IEEE J. Solid State Circuits 44(6): 1734-1744 (2009) - [j48]Rida S. Assaad, José Silva-Martínez:
The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier. IEEE J. Solid State Circuits 44(9): 2535-2542 (2009) - [j47]Marvin Onabajo, José Silva-Martínez, Félix O. Fernandez-Rodriguez, Edgar Sánchez-Sinencio:
An On-Chip Loopback Block for RF Transceiver Built-In Test. IEEE Trans. Circuits Syst. II Express Briefs 56-II(6): 444-448 (2009) - [j46]Chinmaya Mishra, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio, José Silva-Martínez:
System and Circuit Design for an MB-OFDM UWB Frequency Synthesizer. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(7): 1467-1477 (2009) - [j45]Rida S. Assaad, José Silva-Martínez:
A Graphical Approach to Teaching Amplifier Design at the Undergraduate Level. IEEE Trans. Educ. 52(1): 39-45 (2009) - [j44]Rida S. Assaad, José Silva-Martínez:
Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers. VLSI Design 2009: 323595:1-323595:11 (2009) - [c35]Yung-Chung Lo, Hsien-Pu Chen, José Silva-Martínez, Sebastian Hoyos:
A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider. CICC 2009: 259-262 - [c34]Vijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz:
A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element. ISSCC 2009: 174-175 - [c33]Eduardo Aldrete-Vidrio, Marvin Onabajo, Josep Altet, Diego Mateo, José Silva-Martínez:
Non-invasive RF built-in testing using on-chip temperature sensors. ITC 2009: 1 - 2008
- [j43]David Hernandez-Garduno, José Silva-Martínez:
A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer. IEEE J. Solid State Circuits 43(11): 2482-2491 (2008) - [j42]Pradeep Kotte Prakasam, Mandar Kulkarni, Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, José Silva-Martínez, Edgar Sánchez-Sinencio:
Applications of Multipath Transform-Domain Charge-Sampling Wide-Band Receivers. IEEE Trans. Circuits Syst. II Express Briefs 55-II(4): 309-313 (2008) - [j41]Jinghua Li, José Silva-Martínez, Brian Brunn, Shahriar Rokhsaz, Moises E. Robinson:
A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(5): 1213-1222 (2008) - [j40]Xiaohua Fan, Marvin Onabajo, Félix O. Fernandez-Rodriguez, José Silva-Martínez, Edgar Sánchez-Sinencio:
A Current Injection Built-In Test Technique for RF Low-Noise Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 1794-1804 (2008) - [j39]Alberto Valdes-Garcia, Radhika Venkatasubramanian, José Silva-Martínez, Edgar Sánchez-Sinencio:
A Broadband CMOS Amplitude Detector for On-Chip RF Measurements. IEEE Trans. Instrum. Meas. 57(7): 1470-1477 (2008) - [c32]Manisha Gambhir, Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio:
A low power 1.3GHz dual-path current mode Gm-C filter. CICC 2008: 703-706 - [c31]Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio:
A 1.2mW 1.6Vpp-Swing Class-AB 16Ω Headphone Driver Capable of Handling Load Capacitance up to 22nF. ISSCC 2008: 434-435 - 2007
- [j38]Bharath Kumar Thandri, José Silva-Martínez:
A 63 dB SNR, 75-mW Bandpass RF ΣΔ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-µm SiGe BiCMOS Technology. IEEE J. Solid State Circuits 42(2): 269-279 (2007) - [j37]Jianhong Xiao, Iuri Mehr, José Silva-Martínez:
A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner. IEEE J. Solid State Circuits 42(2): 292-301 (2007) - [j36]Shanfeng Cheng, Haitao Tong, José Silva-Martínez, Aydin Ilker Karsilayan:
A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz. IEEE J. Solid State Circuits 42(3): 583-591 (2007) - [j35]Alberto Valdes-Garcia, Chinmaya Mishra, Faramarz Bahmani, José Silva-Martínez, Edgar Sánchez-Sinencio:
An 11-Band 3-10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication. IEEE J. Solid State Circuits 42(4): 935-948 (2007) - [j34]Vijay Dhanasekaran, Manisha Gambhir, José Silva-Martínez, Edgar Sánchez-Sinencio:
A 1.1 GHz Fifth Order Active-LC Butterworth Type Equalizing Filter. IEEE J. Solid State Circuits 42(11): 2411-2420 (2007) - [j33]Manisha Gambhir, Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio:
Low-Power Architecture and Circuit Techniques for High-Boost Wide-Band Gm-C Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(3): 458-468 (2007) - [j32]Artur J. Lewinski, José Silva-Martínez:
A 30-MHz Fifth-Order Elliptic Low-Pass CMOS Filter With 65-dB Spurious-Free Dynamic Range. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(3): 469-480 (2007) - [j31]Haitao Tong, Shanfeng Cheng, Aydin I. Karsilayan, José Silva-Martínez:
An Injection-Locked Frequency Divider With Multiple Highly Nonlinear Injection Stages and Large Division Ratios. IEEE Trans. Circuits Syst. II Express Briefs 54-II(4): 313-317 (2007) - [j30]David Hernandez-Garduno, José Silva-Martínez, José L. Ausín:
Estimation of Aliasing Effects Due to Periodical Nonuniform Individual Sampling in High-Q Switched-Capacitor Filters. IEEE Trans. Circuits Syst. II Express Briefs 54-II(5): 387-391 (2007) - [j29]