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2020 – today
- 2020
[j18]Quan Deng
, Youtao Zhang, Zhenyu Zhao, Shuzheng Zhang, Minxuan Zhang, Jun Yang:
FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2396-2409 (2020)
2010 – 2019
- 2019
- [c56]Quan Deng, Youtao Zhang, Minxuan Zhang, Jun Yang:
LAcc: Exploiting Lookup Table-based Fast and Accurate Vector Multiplication in DRAM-based CNN Accelerator. DAC 2019: 128 - 2018
- [c55]Quan Deng, Lei Jiang, Youtao Zhang, Minxuan Zhang, Jun Yang:
DrAcc: a DRAM based accelerator for accurate CNN inference. DAC 2018: 168:1-168:6 - 2017
- [c54]Quan Deng, Youtao Zhang, Minxuan Zhang, Jun Yang:
Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design. ICCAD 2017: 736-742 - [c53]Lei Shan, Canqun Yang, Weixia Xu, Minxuan Zhang:
Heterogeneous acceleration for CNN training with many integrated core. ICSPCC 2017: 1-6 - [c52]Naiyang Guan, Lei Shan, Canqun Yang, Weixia Xu, Minxuan Zhang:
Delay Compensated Asynchronous Adam Algorithm for Deep Neural Networks. ISPA/IUCC 2017: 852-859 - 2016
- [j17]Wei Guo, Minxuan Zhang, Chaoyun Yao, Peng Li, Chaochao Feng, Hongwei Zhou:
Thermal optimal task allocation algorithm for multi-core 3D IC with interlayer cooling system. IEICE Electron. Express 13(1): 20150970 (2016) - [c51]Hongguang Zhang, Minxuan Zhang, Zhenyu Zhao, Shuo Tian:
A Novel Hybrid Last Level Cache Based on Multi-retention STT-RAM Cells. ACA 2016: 28-39 - [c50]Suncheng Xiang, Minxuan Zhang, Zuocheng Xing, Cang Liu:
Hardware design of ML algorithm in MIMO-OFDM system. ICSAI 2016: 965-970 - [c49]Hongguang Zhang, Minxuan Zhang:
A Novel L1 Cache Based on Volatile STT-RAM. NCCET 2016: 32-39 - [c48]Chengyi Zhang, Jiming Wang, Minxuan Zhang, Xiangdi Wu:
A New DVFS Algorithm Design for Multi-core Processor Chip. NCCET 2016: 40-51 - [c47]Lei Shan, Minxuan Zhang, Lin Deng, Guohui Gong:
A Dynamic Multi-precision Fixed-Point Data Quantization Strategy for Convolutional Neural Network. NCCET 2016: 102-111 - [c46]Lei Shan, He Wang, Weixia Xu, Canqun Yang, Minxuan Zhang:
Accelerating Nyström Kernel Independent Component Analysis with Many Integrated Core Architecture. NCCET 2016: 168-176 - [c45]Hailiang Zhou, Xiantuo Tang, Minxuan Zhang, Yue Hao:
Sub-threshold Performance Driven Choice in Tunneling CNFETs. NCCET 2016: 200-211 - 2015
- [j16]Lu Tang, Jinli Yan, Zhigang Sun, Tao Li, Minxuan Zhang:
Towards high-performance packet processing on commodity multi-cores: current issues and future directions. Sci. China Inf. Sci. 58(12): 1-16 (2015) - [j15]Wei Guo, Minxuan Zhang, Peng Li, Chaoyun Yao:
Floorplanner for multi-core micro-processors in 3D ICs with interlayer cooling system. IEICE Electron. Express 12(16): 20150489 (2015) - [j14]Chaoyun Yao, Chaochao Feng, Minxuan Zhang, Wei Guo, Shouzhong Zhu, Shaojun Wei:
Exploring partitioning methods for multicast in 3D bufferless Network on Chip. IEICE Electron. Express 12(22): 20150802 (2015) - [j13]Peng Li, Wei Guo, Zhenyu Zhao, Minxuan Zhang, Quan Deng:
SEU hardened layout design for SRAM cells based on SEU reversal. IEICE Electron. Express 12(22): 20150804 (2015) - [c44]Chao Song, Minxuan Zhang:
Improved access pattern for ROB soft error rate mitigation based on 3D integration technology. 3DIC 2015: TS8.20.1-TS8.20.5 - [c43]Chaoyun Yao, Chaochao Feng, Minxuan Zhang, Wei Guo, Shouzhong Zhu, Shaojun Wei:
Partitioning Methods for Multicast in Bufferless 3D Network on Chip. NCCET 2015: 13-22 - [c42]Wei Guo, Minxuan Zhang, Peng Li, Chaoyun Yao, Hongwei Zhou:
Thermal-Aware Floorplanner for Multi-core 3D ICs with Interlayer Cooling. NCCET 2015: 23-30 - [c41]Chao Song, Minxuan Zhang:
Mitigating Soft Error Rate Through Selective Replication in Hybrid Architecture. NCCET 2015: 38-47 - [c40]Peng Li, Wei Guo, Zhenyu Zhao, Minxuan Zhang:
Impact of Heavy Ion Species and Energy on SEE Characteristics of Three-Dimensional Integrated Circuit. NCCET 2015: 164-172 - [c39]Quan Deng, Minxuan Zhang, Zhenyu Zhao, Peng Li:
Mitigation Techniques Against TSV-to-TSV Coupling in 3DIC. NCCET 2015: 182-190 - 2014
- [j12]Peng Li, Minxuan Zhang, Weicheng Zhang, Zhenyu Zhao, Chao Song, Hua Fan:
Effect of charge sharing on SEU sensitive area of 40-nm 6T SRAM cells. IEICE Electron. Express 11(4): 20140051 (2014) - [j11]Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei:
Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1054-1059 (2014) - [c38]Ronghui Wang, Zhiguang Chen, Nong Xiao, Minxuan Zhang, Weihua Dong:
Assimilating Cleaning Operations with Flash-Level Parallelism for NAND Flash-Based Devices. CIT 2014: 212-219 - 2013
- [j10]Jun Gao, Minxuan Zhang, Zuocheng Xing, Chaochao Feng:
Architecture and Implementation of a Reduced EPIC Processor. IEICE Trans. Inf. Syst. 96-D(1): 9-18 (2013) - [j9]Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Zuocheng Xing:
Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1053-1066 (2013) - [c37]Anwen Huang, Chao Song, Wei Guo, Peng Li, Minxuan Zhang:
An interference miss isolation mechanism based on skewed mapping for shared cache in Chip Multiprocessors. ASICON 2013: 1-4 - [c36]Yongqing Wang, Minxuan Zhang:
Wormhole Bubble in Torus Networks. NCCET 2013: 73-80 - 2012
- [j8]Yancang Chen, Zhonghai Lu, Lunguo Xie, Jinwen Li, Minxuan Zhang:
A single-cycle output buffered router with layered switching for Networks-on-Chips. Comput. Electr. Eng. 38(4): 906-916 (2012) - [j7]Yu Cheng, Anguo Ma, Minxuan Zhang:
Accurate and Simplified Prediction of L2 Cache Vulnerability for Cost-Efficient Soft Error Protection. IEICE Trans. Inf. Syst. 95-D(1): 56-66 (2012) - [j6]Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Xianju Yang:
Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip. IEICE Trans. Inf. Syst. 95-D(4): 1052-1061 (2012) - [j5]Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang:
A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip. IEICE Trans. Inf. Syst. 95-D(5): 1519-1522 (2012) - [j4]Xianju Yang, Peixiang Yan, Jiang Jiang, Minxuan Zhang:
Adaptive Capacity Sharing through Probabilistic Controlled Placement. J. Comput. 7(5): 1236-1243 (2012) - [c35]Yuan Li, Jiang Jiang, Hanqiang Cheng, Minxuan Zhang, Shaojun Wei:
An Efficient Hardware Random Number Generator Based on the MT Method. CIT 2012: 1011-1015 - [c34]Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei:
Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method. FPT 2012: 190-197 - [c33]Yongqing Wang, Minxuan Zhang, Qingchao Yu, Zhengbin Pang:
Adaptive Bubble Scheme with Minimal Buffers in Torus Networks. HPCC-ICESS 2012: 914-919 - [c32]Anwen Huang, Jun Gao, Wei Guo, Wenqiang Shi, Minxuan Zhang, Jiang Jiang:
PSA-NUCA: A Pressure Self-Adapting Dynamic Non-uniform Cache Architecture. NAS 2012: 181-188 - 2011
- [j3]Xiaomin Jia, Jiang Jiang, Yongwen Wang, Shubo Qi, Tianlei Zhao, Guitao Fu, Minxuan Zhang:
BP-NUCA: Cache Pressure-Aware Migration for High-Performance Caching in CMPs. Comput. Informatics 30(5): 1037-1060 (2011) - [c31]Chaochao Feng, Jinwen Li, Zhonghai Lu, Axel Jantsch, Minxuan Zhang:
Evaluation of deflection routing on various NoC topologies. ASICON 2011: 163-166 - [c30]Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang:
Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method. FPL 2011: 110-115 - [c29]Xun Chen, Jianwen Zhu, Minxuan Zhang:
Timing-Driven Routing of High Fanout Nets. FPL 2011: 423-428 - [c28]Tianlei Zhao, Jiang Jiang, Guitao Fu, Shubo Qi, Xiaomin Jia, Minxuan Zhang:
Accelerating the Extraction of Representative Behaviors of Programs with Dynamic Binary Translation. HPCC 2011: 312-320 - [c27]Yu Cheng, Yongwen Wang, Zuocheng Xing, Minxuan Zhang:
Characterizing Time-Varying Behavior and Predictability of Cache AVF. INCoS 2011: 720-725 - [c26]Chaochao Feng, Minxuan Zhang, Jinwen Li, Jiang Jiang, Zhonghai Lu, Axel Jantsch:
A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip. ISVLSI 2011: 19-24 - 2010
- [j2]Hailiang Zhou, Jiang Jiang, Minxuan Zhang, Liang Fang:
Opitimization of tunneling carbon nanotube-FETs based on stair-case doping strategy. Sci. China Inf. Sci. 53(12): 2696-2704 (2010) - [j1]Xiaomin Jia, Pingjing Lu, Caixia Sun, Minxuan Zhang:
Dynamic Program Behavior Identification for High Performance CMPs with Private LLCs. IEICE Trans. Inf. Syst. 93-D(12): 3211-3222 (2010) - [c25]Yu Cheng, Anguo Ma, Yuxing Tang, Minxuan Zhang:
Phase Characterization and Classification for Micro-architecture Soft Error. EUC 2010: 687-694 - [c24]Yongwen Wang, Qianbing Zheng, Qiang Dou, Minxuan Zhang:
Low Power Design for a Multi-core Multi-thread Microprocessor. GreenCom/CPSCom 2010: 351-356 - [c23]Xiaomin Jia, Jiang Jiang, Tianlei Zhao, Shubo Qi, Minxuan Zhang:
Towards Online Application Cache Behaviors Identification in CMPs. HPCC 2010: 1-8 - [c22]Shubo Qi, Minxuan Zhang, Jinwen Li, Tianlei Zhao, Chengyi Zhang, Shaoqing Li:
A high performance router with dynamic buffer allocation for on-chip interconnect networks. ICCD 2010: 462-467 - [c21]Zhou Hailiang, Minxuan Zhang, Fang Liang, Hao Yue:
Performance Optimization of Conventional MOS-Like Carbon Nanotube-FETs Based on Dual-Gate-Material. ISVLSI 2010: 277-281 - [c20]Shubo Qi, Jinwen Li, Zuocheng Xing, Xiaomin Jia, Minxuan Zhang:
A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network. ISVLSI 2010: 316-320 - [c19]Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, Minxuan Zhang:
A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip. NoCArc@MICRO 2010: 11-16 - [c18]Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, Minxuan Zhang:
FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip. SoCC 2010: 441-446
2000 – 2009
- 2009
- [c17]Peixiang Yan, Xianju Yang, Minxuan Zhang:
A Global Replacement Based on Actual Set Association. ICESS 2009: 103-108 - 2008
- [c16]Canwen Xiao, Minxuan Zhang, Yong Dou, Zhitong Zhao:
Dimensional Bubble Flow Control and Fully Adaptive Routing in the 2-D Mesh Network on Chip. EUC (1) 2008: 353-358 - 2007
- [c15]Quanbao Sun, Liquan Xiao, Minxuan Zhang:
Look-Ahead Adaptive Routing on k -Ary n -Trees. APPT 2007: 441-449 - [c14]Tian Xinhua, Minxuan Zhang:
A Unified Compressed Cache Hierarchy With Partial Cache Line Prefetching Used for SMT Processor. CDES 2007: 54-60 - [c13]Qingying Deng, Minxuan Zhang, Jiang Jiang:
A Parallel Infrastructure on Dynamic EPIC SMT. ICA3PP 2007: 165-176 - [c12]Xinhua Tian, Minxuan Zhang:
A Unified Compressed Cache Hierarchy Using Simple Frequent Pattern Compression and Partial Cache Line Prefetching. ICESS 2007: 142-153 - [c11]Quanbao Sun, Minxuan Zhang, Liquan Xiao:
Hardware-Based Multicast with Global Load Balance on k-ary n-trees. ICPP 2007: 21 - [c10]Qingying Deng, Minxuan Zhang, Jiang Jiang:
A Parallel Infrastructure on Dynamic EPIC SMT and Its Speculation Optimization. ISPA 2007: 235-244 - [c9]Qingying Deng, Minxuan Zhang, Jiang Jiang:
Register File Management and Compiler Optimization on EDSMT. ISPA Workshops 2007: 394-403 - 2006
- [c8]Caixia Sun, Hong-Wei Tang, Minxuan Zhang:
Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors. Asia-Pacific Computer Systems Architecture Conference 2006: 459-465 - [c7]Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing:
An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. Asia-Pacific Computer Systems Architecture Conference 2006: 588-594 - [c6]Caixia Sun, Hong-Wei Tang, Minxuan Zhang:
Controlling Performance of a Time-Criticial Thread in SMT Processors by Instruction Fetch Policy. PDCAT 2006: 217-222 - 2005
- [c5]Caixia Sun, Hong-Wei Tang, Minxuan Zhang:
A Fetch Policy Maximizing Throughput and Fairness for Two-Context SMT Processors. APPT 2005: 13-22 - [c4]Yimin Xia, Jun Luo, Minxuan Zhang:
Detecting Memory Access Errors with Flow-Sensitive Conditional Range Analysis. ICESS 2005: 320-331 - [c3]Minxuan Zhang, Caixia Sun:
Enhancing DCache Warn Fetch Policy for SMT Processors. ISPA 2005: 216-223 - 2004
- [c2]Caixia Sun, Minxuan Zhang:
Dual-Stack Return Address Predictor. ICESS 2004: 172-179 - 2003
- [c1]Jingfei Jiang, Xiaoqiang Ni, Minxuan Zhang:
Reconfigurable Cipher Processing Framework and Implementation. APPT 2003: 509-519
Coauthor Index
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