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@article{DBLP:journals/tvlsi/Abdel-HafeezGP13,
author = {Saleh Abdel{-}Hafeez and
Ann Gordon{-}Ross and
Behrooz Parhami},
title = {Scalable Digital {CMOS} Comparator Using a Parallel Prefix Tree},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {1989--1998},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2222453},
doi = {10.1109/TVLSI.2012.2222453},
timestamp = {Tue, 09 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Abdel-HafeezGP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AbselMK13,
author = {Kalarikkal Absel and
Lijo Manuel and
R. K. Kavitha},
title = {Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient
Embedded Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1693--1704},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2213280},
doi = {10.1109/TVLSI.2012.2213280},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AbselMK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AksoyLCFM13,
author = {Levent Aksoy and
Cristiano Lazzari and
Eduardo Costa and
Paulo F. Flores and
Jos{\'{e}} Monteiro},
title = {Design of Digit-Serial {FIR} Filters: Algorithms, Architectures, and
a {CAD} Tool},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {498--511},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2188917},
doi = {10.1109/TVLSI.2012.2188917},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AksoyLCFM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlnajiarKKMHO13,
author = {Dawood Alnajiar and
Hiroaki Konoura and
Younghun Ko and
Yukio Mitsuyama and
Masanori Hashimoto and
Takao Onoye},
title = {Implementing Flexible Reliability in a Coarse-Grained Reconfigurable
Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2165--2178},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2228015},
doi = {10.1109/TVLSI.2012.2228015},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AlnajiarKKMHO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AslanzadehPMS13,
author = {Hesam Amir Aslanzadeh and
Erik John Pankratz and
Chinmaya Mishra and
Edgar S{\'{a}}nchez{-}Sinencio},
title = {Current-Reused 2.4-GHz Direct-Modulation Transmitter With On-Chip
Automatic Tuning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {732--746},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190538},
doi = {10.1109/TVLSI.2012.2190538},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AslanzadehPMS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AtakA13,
author = {Oguzhan Atak and
Abdullah Atalar},
title = {BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1285--1298},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2207748},
doi = {10.1109/TVLSI.2012.2207748},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AtakA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BasuM13,
author = {Kanad Basu and
Prabhat Mishra},
title = {{RATS:} Restoration-Aware Trace Signal Selection for Post-Silicon
Validation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {605--613},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2192457},
doi = {10.1109/TVLSI.2012.2192457},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BasuM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhojJ13,
author = {Ajay N. Bhoj and
Niraj K. Jha},
title = {Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {1975--1988},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227850},
doi = {10.1109/TVLSI.2012.2227850},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BhojJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhojJJ13,
author = {Ajay N. Bhoj and
Rajiv V. Joshi and
Niraj K. Jha},
title = {3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate
Devices and Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2094--2105},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227848},
doi = {10.1109/TVLSI.2012.2227848},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BhojJJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CaiZ13,
author = {Fang Cai and
Xinmiao Zhang},
title = {Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check
Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2010--2023},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2226920},
doi = {10.1109/TVLSI.2012.2226920},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CaiZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Caro13,
author = {Davide De Caro},
title = {Glitch-Free NAND-Based Digitally Controlled Delay-Lines},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {55--66},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2181547},
doi = {10.1109/TVLSI.2011.2181547},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Caro13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChakrabortyR13,
author = {Koushik Chakraborty and
Sanghamitra Roy},
title = {Architecturally Homogeneous Power-Performance Heterogeneous Multicore
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {670--679},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2199142},
doi = {10.1109/TVLSI.2012.2199142},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabortyR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangC13,
author = {Meng{-}Chou Chang and
Wei{-}Hsiang Chang},
title = {Asynchronous Fine-Grain Power-Gated Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1143--1153},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2204782},
doi = {10.1109/TVLSI.2012.2204782},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangHKCW13,
author = {Hsiu{-}Ming Chang and
Jiun{-}Lang Huang and
Ding{-}Ming Kwai and
Kwang{-}Ting Cheng and
Cheng{-}Wen Wu},
title = {Low-Cost Error Tolerance Scheme for 3-D {CMOS} Imagers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {465--474},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190148},
doi = {10.1109/TVLSI.2012.2190148},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangHKCW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangHW13,
author = {Austin C.{-}C. Chang and
Ryan H.{-}M. Huang and
Charles H.{-}P. Wen},
title = {{CASSER:} {A} Closed-Form Analysis Framework for Statistical Soft
Error Rate},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1837--1848},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2220386},
doi = {10.1109/TVLSI.2012.2220386},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangHW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaoCW13,
author = {Chih{-}Hao Chao and
Kun{-}Chih Chen and
An{-}Yeu Wu},
title = {Routing-Based Traffic Migration and Buffer Allocation Schemes for
3-D Network-on-Chip Systems With Thermal Limit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2118--2131},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227852},
doi = {10.1109/TVLSI.2012.2227852},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaoCW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaoTHWF13,
author = {Pei{-}Ying Chao and
Chao{-}Wen Tzeng and
Shi{-}Yu Huang and
Chia{-}Chieh Weng and
Shan{-}Chien Fang},
title = {Process-Resilient Low-Jitter All-Digital {PLL} via Smooth Code-Jumping},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2240--2249},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2230454},
doi = {10.1109/TVLSI.2012.2230454},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaoTHWF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CharaniaOS13,
author = {Tasreen Charania and
Ajoy Opal and
Manoj Sachdev},
title = {Analysis and Design of On-Chip Decoupling Capacitors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {648--658},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2198501},
doi = {10.1109/TVLSI.2012.2198501},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CharaniaOS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaturvediAA13,
author = {Vikram Chaturvedi and
Tejasvi Anand and
Bharadwaj Amrutur},
title = {An 8-to-1 bit 1-MS/s {SAR} {ADC} With {VGA} and Integrated Data Compression
for Neural Recording},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2034--2044},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2013.2238957},
doi = {10.1109/TVLSI.2013.2238957},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaturvediAA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenH13,
author = {Jienan Chen and
Jianhao Hu},
title = {Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based
Residue Number System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1322--1332},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2205953},
doi = {10.1109/TVLSI.2012.2205953},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLC13,
author = {Shi{-}Hao Chen and
Youn{-}Long Lin and
Mango Chia{-}Tso Chao},
title = {Power-Up Sequence Control for {MTCMOS} Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {413--423},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2187689},
doi = {10.1109/TVLSI.2012.2187689},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLHJ13,
author = {Hsiao{-}Yun Chen and
Jyun{-}Nan Lin and
Hsiang{-}Sheng Hu and
Shyh{-}Jye Jou},
title = {{STBC-OFDM} Downlink Baseband Receiver for Mobile {WMAN}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {43--54},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2181965},
doi = {10.1109/TVLSI.2011.2181965},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLHJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLWH13,
author = {Jiann{-}Jong Chen and
Ming{-}Xiang Lu and
Tse{-}Hsu Wu and
Yuh{-}Shyan Hwang},
title = {Sub-1-V Fast-Response Hysteresis-Controlled {CMOS} Buck Converter
Using Adaptive Ramp Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1608--1618},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2218263},
doi = {10.1109/TVLSI.2012.2218263},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLWH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenSM13,
author = {Yupeng Chen and
Bertil Schmidt and
Douglas L. Maskell},
title = {Reconfigurable Accelerator for the Word-Matching Stage of {BLASTN}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {659--669},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2196060},
doi = {10.1109/TVLSI.2012.2196060},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenSM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenTH13,
author = {You{-}Gang Chen and
Hen{-}Wai Tsao and
Chorng{-}Sii Hwang},
title = {A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {270--280},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2182216},
doi = {10.1109/TVLSI.2011.2182216},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenTH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenTH13a,
author = {Chia{-}Min Chen and
Tung{-}Wei Tsai and
Chung{-}Chih Hung},
title = {Fast Transient Low-Dropout Voltage Regulator With Hybrid Dynamic Biasing
Technique for SoC Application},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1742--1747},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2217766},
doi = {10.1109/TVLSI.2012.2217766},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenTH13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenWW13,
author = {Ching{-}Yi Chen and
Sheng{-}Hung Wang and
Cheng{-}Wen Wu},
title = {Write Current Self-Configuration Scheme for {MRAM} Yield Improvement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1260--1270},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2207136},
doi = {10.1109/TVLSI.2012.2207136},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenWW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenYSDBL13,
author = {Dandan Chen and
Kiat Seng Yeo and
Xiaomeng Shi and
Manh Anh Do and
Chirn Chye Boon and
Wei Meng Lim},
title = {Cross-Coupled Current Conveyor Based {CMOS} Transimpedance Amplifier
for Broadband Data Transmission},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1516--1525},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2211086},
doi = {10.1109/TVLSI.2012.2211086},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenYSDBL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenZJW13,
author = {Yen{-}Liang Chen and
Cheng{-}Zhou Zhan and
Ting{-}Jyun Jheng and
An{-}Yeu Wu},
title = {Reconfigurable Adaptive Singular Value Decomposition Engine Design
for High-Throughput {MIMO-OFDM} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {747--760},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2195040},
doi = {10.1109/TVLSI.2012.2195040},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenZJW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Cheng0H013,
author = {Yuanqing Cheng and
Lei Zhang and
Yinhe Han and
Xiaowei Li},
title = {Thermal-Constrained Task Allocation for Interconnect Energy Reduction
in 3-D Homogeneous MPSoCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {239--249},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2182067},
doi = {10.1109/TVLSI.2011.2182067},
timestamp = {Tue, 23 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Cheng0H013.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChiuHLLT13,
author = {Ching{-}Te Chiu and
Wen{-}Chih Huang and
Chih{-}Hsing Lin and
Wei{-}Chih Lai and
Ying{-}Fang Tsao},
title = {Embedded Transition Inversion Coding With Low Switching Activity for
Serial Links},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1797--1810},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2219888},
doi = {10.1109/TVLSI.2012.2219888},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChiuHLLT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChiuHLWHLCKH13,
author = {Ching{-}Te Chiu and
Yu{-}Hao Hsu and
Wei{-}Chih Lai and
Jen{-}Ming Wu and
Shawn S. H. Hsu and
Yang{-}Syu Lin and
Fanta Chen and
Min{-}Sheng Kao and
Yarsun Hsu},
title = {Low Propagation Delay Load-Balanced 4 {\texttimes} 4 Switch Fabric
{IC} in 0.13-{\(\mathrm{\mu}\)}m {CMOS} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1481--1495},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2212618},
doi = {10.1109/TVLSI.2012.2212618},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChiuHLWHLCKH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoL13,
author = {Taesang Cho and
Hanho Lee},
title = {A High-Speed Low-Complexity Modified \emph{Radix}-2\({}^{\mbox{5}}\)
{FFT} Processor for High Rate {WPAN} Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {187--191},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2182068},
doi = {10.1109/TVLSI.2011.2182068},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoiYLAL13,
author = {Young{-}Geun Choi and
Sungjoo Yoo and
Sunggu Lee and
Jung Ho Ahn and
Kangmin Lee},
title = {{MAEPER:} Matching Access and Error Patterns With Error-Free Resource
for Low Vcc {L1} Cache},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1013--1026},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2202931},
doi = {10.1109/TVLSI.2012.2202931},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoiYLAL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChuangLS13,
author = {Pierce Chuang and
David Li and
Manoj Sachdev},
title = {Constant Delay Logic Style},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {554--565},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2189423},
doi = {10.1109/TVLSI.2012.2189423},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChuangLS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChungA13,
author = {Jaeyong Chung and
Jacob A. Abraham},
title = {Concurrent Path Selection Algorithm in Statistical Timing Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1715--1726},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2218136},
doi = {10.1109/TVLSI.2012.2218136},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChungA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChungPA13,
author = {Jaeyong Chung and
Joonsung Park and
Jacob A. Abraham},
title = {A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented
Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {281--291},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2182217},
doi = {10.1109/TVLSI.2011.2182217},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChungPA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Dai013,
author = {Jianwei Dai and
Lei Wang},
title = {An Energy-Efficient {L2} Cache Architecture Using Way Tag Information
Under Write-Through Policy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {102--112},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2181879},
doi = {10.1109/TVLSI.2011.2181879},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Dai013.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DaiCYHH13,
author = {Shanshan Dai and
Xiaofei Cao and
Ting Yi and
Allyn E. Hubbard and
Zhiliang Hong},
title = {1-V Low-Power Programmable Rail-to-Rail Operational Amplifier With
Improved Transconductance Feedback Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1928--1935},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2220387},
doi = {10.1109/TVLSI.2012.2220387},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DaiCYHH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DarakVL13,
author = {Sumit Jagdish Darak and
A. Prasad Vinod and
Edmund Ming{-}Kit Lai},
title = {Efficient Implementation of Reconfigurable Warped Digital Filters
With Variable Low-Pass, High-Pass, Bandpass, and Bandstop Responses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1165--1169},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2203158},
doi = {10.1109/TVLSI.2012.2203158},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DarakVL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DaveJBS13,
author = {Marshnil Vipin Dave and
Mahavir Jain and
Maryam Shojaei Baghini and
Dinesh Kumar Sharma},
title = {A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {342--353},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2185835},
doi = {10.1109/TVLSI.2012.2185835},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DaveJBS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DengC13,
author = {Guoqing Deng and
Chunhong Chen},
title = {Binary Multiplication Using Hybrid {MOS} and Multi-Gate Single-Electron
Transistors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1573--1582},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2217993},
doi = {10.1109/TVLSI.2012.2217993},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DengC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DengC13a,
author = {Guoqing Deng and
Chunhong Chen},
title = {A {SET/MOS} Hybrid Multiplier Using Frequency Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1738--1742},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2218264},
doi = {10.1109/TVLSI.2012.2218264},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DengC13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DiTomasoMKSL13,
author = {Dominic DiTomaso and
Randy Morris and
Avinash Karanth Kodi and
Ashwini Sarathy and
Ahmed Louri},
title = {Extending the Energy Efficiency and Performance With Channel Buffers,
Crossbars, and Topology Analysis for Network-on-Chips},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2141--2154},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227283},
doi = {10.1109/TVLSI.2012.2227283},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DiTomasoMKSL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DingHT13,
author = {Ruo{-}Ting Ding and
Shi{-}Yu Huang and
Chao{-}Wen Tzeng},
title = {Cell-Based Process Resilient Multiphase Clock Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2348--2352},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2230347},
doi = {10.1109/TVLSI.2012.2230347},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DingHT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DoCKY13,
author = {Anh{-}Tuan Do and
Shoushun Chen and
Zhi{-}Hui Kong and
Kiat Seng Yeo},
title = {A High Speed Low Power {CAM} With a Parity Bit and Power-Gated {ML}
Sensing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {151--156},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2178276},
doi = {10.1109/TVLSI.2011.2178276},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DoCKY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EbrahimiMAF13,
author = {Mojtaba Ebrahimi and
Seyed Ghassem Miremadi and
Hossein Asadi and
Mahdi Fazeli},
title = {Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in
{TMR} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1454--1468},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2213102},
doi = {10.1109/TVLSI.2012.2213102},
timestamp = {Fri, 14 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/EbrahimiMAF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EbrahimiN13,
author = {Emad Ebrahimi and
Sasan Naseh},
title = {A Colpitts {CMOS} Quadrature {VCO} Using Direct Connection of Substrates
for Coupling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {571--574},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2188310},
doi = {10.1109/TVLSI.2012.2188310},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EbrahimiN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EissaSAHEDNA13,
author = {Haitham Eissa and
Rami Fathy Salem and
Ahmed Arafa and
Sherif Hany and
Abdelrahman ElMously and
Mohamed Dessouky and
David Nairn and
Mohab H. Anis},
title = {Parametric {DFM} Solution for Analog Circuits: Electrical-Driven Hotspot
Detection, Analysis, and Correction Flow},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {807--820},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2201759},
doi = {10.1109/TVLSI.2012.2201759},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EissaSAHEDNA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EmreC13,
author = {Yunus Emre and
Chaitali Chakrabarti},
title = {Techniques for Compensating Memory Errors in {JPEG2000}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {159--163},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2180407},
doi = {10.1109/TVLSI.2011.2180407},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EmreC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EsmaeildoustSJSN13,
author = {Mohammad Esmaeildoust and
Dimitrios Schinianakis and
Hamid Javashi and
Thanos Stouraitis and
Keivan Navi},
title = {Efficient {RNS} Implementation of Elliptic Curve Point Multiplication
Over {\textdollar}\{{\textbackslash}rm GF\}(p){\textdollar}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1545--1549},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2210916},
doi = {10.1109/TVLSI.2012.2210916},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/EsmaeildoustSJSN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EsmaeiliA13,
author = {Seyed Ebrahim Esmaeili and
Asim J. Al{-}Khalili},
title = {Integrated Power and Clock Distribution Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1941--1945},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2219630},
doi = {10.1109/TVLSI.2012.2219630},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EsmaeiliA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FahmyM13,
author = {Suhaib A. Fahmy and
A. R. Mohan},
title = {Architecture for Real-Time Nonparametric Probability Density Function
Estimation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {910--920},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2201187},
doi = {10.1109/TVLSI.2012.2201187},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FahmyM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Feng13,
author = {Zhuo Feng},
title = {Scalable Multilevel Vectorless Power Grid Voltage Integrity Verification},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1388--1397},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2212033},
doi = {10.1109/TVLSI.2012.2212033},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Feng13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FengL13,
author = {Zhuo Feng and
Peng Li},
title = {Fast Thermal Analysis on {GPU} for 3D ICs With Integrated Microchannel
Cooling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1526--1539},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2211050},
doi = {10.1109/TVLSI.2012.2211050},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FengL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FengLJZX13,
author = {Chaochao Feng and
Zhonghai Lu and
Axel Jantsch and
Minxuan Zhang and
Zuocheng Xing},
title = {Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant
Deflection Router},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1053--1066},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2204909},
doi = {10.1109/TVLSI.2012.2204909},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FengLJZX13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FongGKPYA13,
author = {Erin G. Fong and
Nathaniel J. Guilar and
Travis Kleeburg and
Hai Pham and
Diego R. Yankelevich and
Rajeevan Amirtharajah},
title = {Integrated Energy-Harvesting Photodiodes With Diffractive Storage
Capacitance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {486--497},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2189898},
doi = {10.1109/TVLSI.2012.2189898},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FongGKPYA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FuketaHYTNSS13,
author = {Hiroshi Fuketa and
Koji Hirairi and
Tadashi Yasufuku and
Makoto Takamiya and
Masahiro Nomura and
Hirofumi Shinohara and
Takayasu Sakurai},
title = {Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V\({}_{\mbox{DDmin}}\)-Aware
Dual Supply Voltage Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1175--1179},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2203834},
doi = {10.1109/TVLSI.2012.2203834},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FuketaHYTNSS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GalanPSMCL13,
author = {Juan Antonio G{\'{o}}mez Gal{\'{a}}n and
Manuel Pedro and
Trinidad Sanchez{-}Rodriguez and
Fernando Mu{\~{n}}oz and
Ram{\'{o}}n Gonz{\'{a}}lez Carvajal and
Antonio J. L{\'{o}}pez{-}Mart{\'{\i}}n},
title = {A Very Linear Low-Pass Filter with Automatic Frequency Tuning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {182--187},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2181880},
doi = {10.1109/TVLSI.2011.2181880},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GalanPSMCL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GargM13,
author = {Siddharth Garg and
Diana Marculescu},
title = {Mitigating the Impact of Process Variation on the Performance of 3-D
Integrated Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1903--1914},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2226762},
doi = {10.1109/TVLSI.2012.2226762},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GargM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GarridoGSG13,
author = {Mario Garrido and
Jes{\'{u}}s Grajal and
Miguel A. S{\'{a}}nchez Marcos and
Oscar Gustafsson},
title = {Pipelined Radix-2\({}^{\mbox{k}}\) Feedforward {FFT} Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {23--32},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2178275},
doi = {10.1109/TVLSI.2011.2178275},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GarridoGSG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GhavamiRPP13,
author = {Behnam Ghavami and
Mohsen Raji and
Hossein Pedram and
Massoud Pedram},
title = {Statistical Functional Yield Estimation and Enhancement of CNFET-Based
{VLSI} Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {887--900},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2197765},
doi = {10.1109/TVLSI.2012.2197765},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GhavamiRPP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GhoshMC13,
author = {Santosh Ghosh and
Debdeep Mukhopadhyay and
Dipanwita Roy Chowdhury},
title = {Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig
Curves on {FPGA} Platform},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {434--442},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2188655},
doi = {10.1109/TVLSI.2012.2188655},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GhoshMC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GhoshRKCB13,
author = {Amlan Ghosh and
Rahul M. Rao and
Jae{-}Joon Kim and
Ching{-}Te Chuang and
Richard B. Brown},
title = {Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1683--1692},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2218838},
doi = {10.1109/TVLSI.2012.2218838},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GhoshRKCB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GortA13,
author = {Marcel Gort and
Jason Helge Anderson},
title = {Combined Architecture/Algorithm Approach to Fast {FPGA} Routing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1067--1079},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2202326},
doi = {10.1109/TVLSI.2012.2202326},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GortA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HanKK13,
author = {Sangwoo Han and
Byung{-}Su Kim and
Juho Kim},
title = {Variation-Aware Aging Analysis in Digital ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2214--2225},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2228886},
doi = {10.1109/TVLSI.2012.2228886},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HanKK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HanWHYZ13,
author = {Jun Han and
Shuai Wang and
Wei Huang and
Zhiyi Yu and
Xiaoyang Zeng},
title = {Parallelization of Radix-2 Montgomery Multiplication on Multicore
Platform},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2325--2330},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2228677},
doi = {10.1109/TVLSI.2012.2228677},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HanWHYZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HaoSTT13,
author = {Zhigang Hao and
Guoyong Shi and
Sheldon X.{-}D. Tan and
Esteban Tlelo{-}Cuautle},
title = {Symbolic Moment Computation for Statistical Analysis of Large Interconnect
Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {944--957},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2197835},
doi = {10.1109/TVLSI.2012.2197835},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HaoSTT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HazraGDP13,
author = {Aritra Hazra and
Sahil Goyal and
Pallab Dasgupta and
Ajit Pal},
title = {Formal Verification of Architectural Power Intent},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {78--91},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2180548},
doi = {10.1109/TVLSI.2011.2180548},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HazraGDP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeLL013,
author = {Zijian He and
Tao Lv and
Huawei Li and
Xiaowei Li},
title = {Test Path Selection for Capturing Delay Failures Under Statistical
Timing Model},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1210--1219},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2208661},
doi = {10.1109/TVLSI.2012.2208661},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HeLL013.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HoACYCLP13,
author = {S. Man Ho Ho and
Yanqing Ai and
Thomas Chun{-}Pong Chau and
Steve C. L. Yuen and
Oliver Chiu{-}sing Choy and
Philip Heng Wai Leong and
Kong{-}Pang Pun},
title = {Architecture and Design Flow for a Highly Efficient Structured {ASIC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {424--433},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190478},
doi = {10.1109/TVLSI.2012.2190478},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HoACYCLP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HoppnerEHWES13,
author = {Sebastian H{\"{o}}ppner and
Holger Eisenreich and
Stephan Henker and
Dennis Walter and
Georg Ellguth and
Ren{\'{e}} Sch{\"{u}}ffny},
title = {A Compact Clock Generator for Heterogeneous {GALS} MPSoCs in 65-nm
{CMOS} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {566--570},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2187224},
doi = {10.1109/TVLSI.2012.2187224},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HoppnerEHWES13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HsiaoKTHLW13,
author = {Shen{-}Fu Hsiao and
Hou{-}Jen Ko and
Yu{-}Ling Tseng and
Wen{-}Liang Huang and
Shin{-}Hung Lin and
Chia{-}Sheng Wen},
title = {Design of Hardware Function Evaluators Using Low-Overhead Nonuniform
Segmentation With Address Remapping},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {875--886},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2202295},
doi = {10.1109/TVLSI.2012.2202295},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HsiaoKTHLW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HsiehC13,
author = {Jui{-}Hung Hsieh and
Tian{-}Sheuan Chang},
title = {Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation
for Real-Time Mobile Video Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {33--42},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2178439},
doi = {10.1109/TVLSI.2011.2178439},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HsiehC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuDBC13,
author = {Xiang Hu and
Peng Du and
James F. Buckwalter and
Chung{-}Kuan Cheng},
title = {Modeling and Analysis of Power Distribution Networks in 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {354--366},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2183904},
doi = {10.1109/TVLSI.2012.2183904},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuDBC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuXZTS13,
author = {Jingtong Hu and
Chun Jason Xue and
Qingfeng Zhuge and
Wei{-}Che Tseng and
Edwin Hsing{-}Mean Sha},
title = {Data Allocation Optimization for Hybrid Scratch Pad Memory With {SRAM}
and Nonvolatile Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1094--1102},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2202700},
doi = {10.1109/TVLSI.2012.2202700},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuXZTS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangCK13,
author = {Yoshi Shih{-}Chieh Huang and
Kaven Chun{-}Kai Chou and
Chung{-}Ta King},
title = {Application-Driven End-to-End Traffic Predictions for Low Power NoC
Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {229--238},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2187688},
doi = {10.1109/TVLSI.2012.2187688},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangCK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangCLL13,
author = {Guan{-}Ying Huang and
Soon{-}Jyh Chang and
Chun{-}Cheng Liu and
Ying{-}Zu Lin},
title = {10-bit 30-MS/s {SAR} {ADC} Using a Switchback Switching Method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {584--588},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190117},
doi = {10.1109/TVLSI.2012.2190117},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangCLL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HungW13,
author = {Eddie Hung and
Steven J. E. Wilton},
title = {Scalable Signal Selection for Post-Silicon Debug},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1103--1115},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2202409},
doi = {10.1109/TVLSI.2012.2202409},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HungW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HwangKK13,
author = {Eun Ju Hwang and
Wook Kim and
Young Hwan Kim},
title = {Timing Yield Slack for Timing Yield-Constrained Optimization and Its
Application to Statistical Leakage Minimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1783--1796},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2220792},
doi = {10.1109/TVLSI.2012.2220792},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HwangKK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HwangKKKK13,
author = {Sewook Hwang and
Kyeong{-}Min Kim and
Jungmoon Kim and
Seon Wook Kim and
Chulwoo Kim},
title = {A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware {EISC}
Processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {575--579},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2188656},
doi = {10.1109/TVLSI.2012.2188656},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HwangKKKK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HwangL13,
author = {Seong{-}In Hwang and
Hanho Lee},
title = {Block-Circulant {RS-LDPC} Code: Code Construction and Efficient Decoder
Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1337--1341},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2210452},
doi = {10.1109/TVLSI.2012.2210452},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HwangL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HymanRBV13,
author = {Ransford Hyman Jr. and
Nagarajan Ranganathan and
Thomas Bingel and
Deanne Tran Vo},
title = {A Clock Control Strategy for Peak Power and {RMS} Current Reduction
Using Path Clustering},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {259--269},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2186989},
doi = {10.1109/TVLSI.2012.2186989},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HymanRBV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ImranLD13,
author = {Naveed Imran and
Jooheung Lee and
Ronald F. DeMara},
title = {Fault Demotion Using Reconfigurable Slack (FaDReS)},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1364--1368},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2206836},
doi = {10.1109/TVLSI.2012.2206836},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ImranLD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/InoueTM13,
author = {Hiroaki Inoue and
Takashi Takenaka and
Masato Motomura},
title = {C-Based Complex Event Processing on Reconfigurable Hardware},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {971--974},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2197230},
doi = {10.1109/TVLSI.2012.2197230},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/InoueTM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Ismail13,
author = {Yehea I. Ismail},
title = {Editorial Appointments for the 2013-2014 Term},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {393--412},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2013.2245574},
doi = {10.1109/TVLSI.2013.2245574},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Ismail13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JakushokasF13,
author = {Renatas Jakushokas and
Eby G. Friedman},
title = {Power Network Optimization Based on Link Breaking Methodology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {983--987},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2201186},
doi = {10.1109/TVLSI.2012.2201186},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JakushokasF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiaoK13,
author = {Hailong Jiao and
Volkan Kursun},
title = {Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation
in {MTCMOS} Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {533--545},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190116},
doi = {10.1109/TVLSI.2012.2190116},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JiaoK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JinHL013,
author = {Song Jin and
Yinhe Han and
Huawei Li and
Xiaowei Li},
title = {Unified Capture Scheme for Small Delay Defect Detection and Aging
Prediction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {821--833},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2197766},
doi = {10.1109/TVLSI.2012.2197766},
timestamp = {Tue, 23 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JinHL013.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KahngKKS13,
author = {Andrew B. Kahng and
Seokhyeong Kang and
Rakesh Kumar and
John Sartori},
title = {Enhancing the Efficiency of Energy-Constrained {DVFS} Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1769--1782},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2219084},
doi = {10.1109/TVLSI.2012.2219084},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KahngKKS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KaizermanFF13,
author = {Asaf Kaizerman and
Sagi Fisher and
Alexander Fish},
title = {Subthreshold Dual Mode Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {979--983},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2198678},
doi = {10.1109/TVLSI.2012.2198678},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KaizermanFF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KanYCR13,
author = {Tsang{-}Chi Kan and
Shih{-}Hsien Yang and
Ting{-}Feng Chang and
Shanq{-}Jang Ruan},
title = {Design of a Practical Nanometer-Scale Redundant Via-Aware Standard
Cell Library for Improved Redundant Via1 Insertion Rate},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {142--147},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2176968},
doi = {10.1109/TVLSI.2011.2176968},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KanYCR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KapoorG13,
author = {Ajay Kapoor and
Jos{\'{e}} Pineda de Gyvez},
title = {Architectural Analysis for Wirelessly Powered Computing Platforms},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2106--2117},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227851},
doi = {10.1109/TVLSI.2012.2227851},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KapoorG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KaraklajicSV13,
author = {Dusko Karaklajic and
J{\"{o}}rn{-}Marc Schmidt and
Ingrid Verbauwhede},
title = {Hardware Designer's Guide to Fault Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2295--2306},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2231707},
doi = {10.1109/TVLSI.2012.2231707},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KaraklajicSV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KarmakarCJ13,
author = {Supriya Karmakar and
John A. Chandy and
Faquir C. Jain},
title = {Design of Ternary Logic Combinational Circuits Based on Quantum Dot
Gate FETs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {793--806},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2198248},
doi = {10.1109/TVLSI.2012.2198248},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KarmakarCJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KiasariLJ13,
author = {Abbas Eslami Kiasari and
Zhonghai Lu and
Axel Jantsch},
title = {An Analytical Latency Model for Networks-on-Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {113--123},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2178620},
doi = {10.1109/TVLSI.2011.2178620},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KiasariLJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimAK13,
author = {Hyunhee Kim and
Jung Ho Ahn and
Jihong Kim},
title = {Exploiting Replicated Cache Blocks to Reduce {L2} Cache Leakage in
CMPs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1863--1877},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2220791},
doi = {10.1109/TVLSI.2012.2220791},
timestamp = {Thu, 13 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimAK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimAL13,
author = {Dae Hyun Kim and
Krit Athikulwongse and
Sung Kyu Lim},
title = {Study of Through-Silicon-Via Impact on the 3-D Stacked {IC} Layout},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {862--874},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2201760},
doi = {10.1109/TVLSI.2012.2201760},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimAL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimAML13,
author = {Hyo{-}Jin Kim and
Tai{-}Ji An and
Sungmeen Myung and
Seung{-}Hoon Lee},
title = {Time-Interleaved and Circuit-Shared Dual-Channel 10 b 200 MS/s 0.18
{\(\mathrm{\mu}\)}m {CMOS} Analog-to-Digital Convertor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2206--2213},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2229305},
doi = {10.1109/TVLSI.2012.2229305},
timestamp = {Thu, 15 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimAML13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimLK13,
author = {Kisoo Kim and
Hokyu Lee and
Chulwoo Kim},
title = {366-kS/s 1.09-nJ 0.0013-{\textdollar}\{{\textbackslash}rm mm\}\{2\}{\textdollar}
Frequency-to-Digital Converter Based {CMOS} Temperature Sensor Utilizing
Multiphase Clock},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1950--1954},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2220389},
doi = {10.1109/TVLSI.2012.2220389},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimLK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimWF13,
author = {HoonSeok Kim and
Chanyoun Won and
Paul D. Franzon},
title = {Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1562--1567},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2213281},
doi = {10.1109/TVLSI.2012.2213281},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimWF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KookCC13,
author = {Sehun Kook and
Hyun Woo Choi and
Abhijit Chatterjee},
title = {Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs
Using Polynomial Fitting Measurements},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {454--464},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190433},
doi = {10.1109/TVLSI.2012.2190433},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KookCC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KoseTPMF13,
author = {Sel{\c{c}}uk K{\"{o}}se and
Simon Tam and
Sally Pinzon and
Bruce McDermott and
Eby G. Friedman},
title = {Active Filter-Based Hybrid On-Chip {DC-DC} Converter for Point-of-Load
Voltage Regulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {680--691},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190539},
doi = {10.1109/TVLSI.2012.2190539},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KoseTPMF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KrihelyBF13,
author = {Natan Krihely and
Sam Ben{-}Yaakov and
Alexander Fish},
title = {Efficiency Optimization of a Step-Down Switched Capacitor Converter
for Subthreshold},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2353--2357},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2231888},
doi = {10.1109/TVLSI.2012.2231888},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KrihelyBF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KuangWCH13,
author = {Shiann{-}Rong Kuang and
Jiun{-}Ping Wang and
Kai{-}Cheng Chang and
Huan{-}Wei Hsu},
title = {Energy-Efficient High-Throughput Montgomery Modular Multipliers for
{RSA} Cryptosystems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {1999--2009},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227846},
doi = {10.1109/TVLSI.2012.2227846},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KuangWCH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KwanNS13,
author = {Hing{-}Kit Kwan and
David C. W. Ng and
Victor W. K. So},
title = {Design and Analysis of Dual-Mode Digital-Control Step-Up Switched-Capacitor
Power Converter With Pulse-Skipping and Numerically Controlled Oscillator-Based
Frequency Modulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2132--2140},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227150},
doi = {10.1109/TVLSI.2012.2227150},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KwanNS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Laflamme-MayerAVBS13,
author = {Nicolas Laflamme{-}Mayer and
Walder Andre and
Olivier Valorge and
Yves Blaqui{\`{e}}re and
Mohamad Sawan},
title = {Configurable Input-Output Power Pad for Wafer-Scale Microelectronic
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2024--2033},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2223247},
doi = {10.1109/TVLSI.2012.2223247},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Laflamme-MayerAVBS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LanYH13,
author = {Po{-}Hsiang Lan and
Tsung{-}Ju Yang and
Po{-}Chiun Huang},
title = {A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation
{(DOTM)} {DC-DC} Converter With Asynchronous Power Saving Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {67--77},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2177481},
doi = {10.1109/TVLSI.2011.2177481},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LanYH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeHB13,
author = {Chi{-}Ying Lee and
Chih{-}Cheng Hsieh and
Jenn{-}Chyou Bor},
title = {2.4-GHz 10-Mb/s {BFSK} Embedded Transmitter With a Stacked-LC {DCO}
for Wireless Testing Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1727--1737},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2217765},
doi = {10.1109/TVLSI.2012.2217765},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeHB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeHC13,
author = {Ren{-}Jie Lee and
Hsin{-}Wu Hsu and
Hung{-}Ming Chen},
title = {Board- and Chip-Aware Package Wire Planning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1377--1387},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2212288},
doi = {10.1109/TVLSI.2012.2212288},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeHC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeJ13,
author = {Chun{-}Yi Lee and
Niraj K. Jha},
title = {Variable-Pipeline-Stage Router},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1669--1682},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2217401},
doi = {10.1109/TVLSI.2012.2217401},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeKCLCKBS13,
author = {Yoonmyung Lee and
Daeyeon Kim and
Jin Cai and
Isaac Lauer and
Leland Chang and
Steven J. Koester and
David T. Blaauw and
Dennis Sylvester},
title = {Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling
Transistors (HETTs)},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1632--1643},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2213103},
doi = {10.1109/TVLSI.2012.2213103},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeKCLCKBS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeKJLY13,
author = {Jang{-}Woo Lee and
Hong{-}Jung Kim and
Chun{-}Seok Jeong and
Jae{-}Jin Lee and
Changsik Yoo},
title = {Skew Compensation Technique for Source-Synchronous Parallel {DRAM}
Interface},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2155--2159},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227853},
doi = {10.1109/TVLSI.2012.2227853},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeKJLY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeNLPLK13,
author = {Junghee Lee and
Chrysostomos Nicopoulos and
Hyung Gyu Lee and
Shreepad Panth and
Sung Kyu Lim and
Jongman Kim},
title = {IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1080--1093},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2202699},
doi = {10.1109/TVLSI.2012.2202699},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeNLPLK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeR13,
author = {Dongsoo Lee and
Kaushik Roy},
title = {Area Efficient ROM-Embedded {SRAM} Cache},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1583--1595},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2217514},
doi = {10.1109/TVLSI.2012.2217514},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeTL13,
author = {I{-}Ting Lee and
Yun{-}Ta Tsai and
Shen{-}Iuan Liu},
title = {A Wide-Range {PLL} Using Self-Healing Prescaler/VCO in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {250--258},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2186990},
doi = {10.1109/TVLSI.2012.2186990},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeTL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Leung13,
author = {Bosco Leung},
title = {Design and Analysis of Saturated Ring Oscillators Based on the Random
Mid-Point Voltage Concept},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1554--1557},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2211048},
doi = {10.1109/TVLSI.2012.2211048},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Leung13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Li13,
author = {Katherine Shu{-}Min Li},
title = {CusNoC: Fast Full-Chip Custom NoC Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {692--705},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2195688},
doi = {10.1109/TVLSI.2012.2195688},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Li13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Li13a,
author = {Katherine Shu{-}Min Li},
title = {Oscillation and Transition Tests for Synchronous Sequential Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2338--2343},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2230654},
doi = {10.1109/TVLSI.2012.2230654},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Li13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiCN13,
author = {Li Li and
Ken Choi and
Haiqing Nan},
title = {Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating
Integration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1540--1544},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2212732},
doi = {10.1109/TVLSI.2012.2212732},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiCN13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiCSWC13,
author = {Gwo{-}Long Li and
Tzu{-}Yu Chen and
Meng{-}Wei Shen and
Meng{-}Hsun Wen and
Tian{-}Sheuan Chang},
title = {135-MHz 258-K Gates {VLSI} Design for All-Intra {H.264/AVC} Scalable
Video Encoder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {636--647},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190536},
doi = {10.1109/TVLSI.2012.2190536},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiCSWC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiHHTHLMHBTWW13,
author = {Tsung{-}Yeh Li and
Shi{-}Yu Huang and
Hsuan{-}Jung Hsu and
Chao{-}Wen Tzeng and
Chih{-}Tsun Huang and
Jing{-}Jia Liou and
Hsi{-}Pin Ma and
Po{-}Chiun Huang and
Jenn{-}Chyou Bor and
Ching{-}Cheng Tien and
Chi{-}Hu Wang and
Cheng{-}Wen Wu},
title = {AC-Plus Scan Methodology for Small Delay Testing and Characterization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {329--341},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2187223},
doi = {10.1109/TVLSI.2012.2187223},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiHHTHLMHBTWW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiL13,
author = {Katherine Shu{-}Min Li and
Yi{-}Yu Liao},
title = {{IEEE} 1500 Compatible Multilevel Maximal Concurrent Interconnect
Test},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1333--1337},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2210451},
doi = {10.1109/TVLSI.2012.2210451},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiLL13,
author = {Kwan Wai Li and
Ka Nang Leung and
Lincoln Lai Kan Leung},
title = {Sub-mW {\textdollar}LC{\textdollar} Dual-Input Injection-Locked Oscillator
for Autonomous WBSNs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {546--553},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2189029},
doi = {10.1109/TVLSI.2012.2189029},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiLL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiMAH13,
author = {Liang Li and
Robert G. Maunder and
Bashir M. Al{-}Hashimi and
Lajos Hanzo},
title = {A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless
Sensor Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {14--22},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2177104},
doi = {10.1109/TVLSI.2011.2177104},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiMAH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiMW13,
author = {Cha{-}Ru Li and
Wai{-}Kei Mak and
Ting{-}Chi Wang},
title = {Fast Fixed-Outline 3-D {IC} Floorplanning With {TSV} Co-Placement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {523--532},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190537},
doi = {10.1109/TVLSI.2012.2190537},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiMW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiZLNZ13,
author = {Wei Li and
Dian Zhou and
Minghua Li and
Binh P. Nguyen and
Xuan Zeng},
title = {Near-Field Communication Transceiver System Modeling and Analysis
Using SystemC/SystemC-AMS With the Consideration of Noise Issues},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2250--2261},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2231443},
doi = {10.1109/TVLSI.2012.2231443},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiZLNZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiangZLZGL13,
author = {Feng Liang and
Luwen Zhang and
Shaochong Lei and
Guohe Zhang and
Kaile Gao and
Bin Liang},
title = {Test Patterns of Multiple {SIC} Vectors: Theory and Application in
{BIST} Schemes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {614--623},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2195689},
doi = {10.1109/TVLSI.2012.2195689},
timestamp = {Mon, 30 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiangZLZGL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiaoCLW13,
author = {Christina C.{-}H. Liao and
Allen W.{-}T. Chen and
Louis Y.{-}Z. Lin and
Charles H.{-}P. Wen},
title = {Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via
{(TSV)} Constraints},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1170--1174},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2204781},
doi = {10.1109/TVLSI.2012.2204781},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiaoCLW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiaoSH13,
author = {Te{-}Wen Liao and
Jun{-}Ren Su and
Chung{-}Chih Hung},
title = {Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected
{PFD}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {589--592},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190118},
doi = {10.1109/TVLSI.2012.2190118},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiaoSH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCJ13,
author = {Chia{-}Chun Lin and
Amlan Chakrabarti and
Niraj K. Jha},
title = {Optimized Quantum Gate Library for Various Physical Machine Descriptions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2055--2068},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227518},
doi = {10.1109/TVLSI.2012.2227518},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCL13,
author = {Yi{-}Min Lin and
Hsie{-}Chia Chang and
Chen{-}Yi Lee},
title = {Improved High Code-Rate Soft {BCH} Decoder Architectures With One
Extra Error Compensation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2160--2164},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227847},
doi = {10.1109/TVLSI.2012.2227847},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinY13,
author = {Jun Lin and
Zhiyuan Yan},
title = {Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic
{LDPC} Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1756--1761},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2218839},
doi = {10.1109/TVLSI.2012.2218839},
timestamp = {Sat, 20 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuLNO13,
author = {Liang Liu and
Johan L{\"{o}}fgren and
Peter Nilsson and
Viktor {\"{O}}wall},
title = {{VLSI} Implementation of a Soft-Output Signal Detector for Multimode
Adaptive Multiple-Input Multiple-Output Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2262--2273},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2231706},
doi = {10.1109/TVLSI.2012.2231706},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuLNO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MahdaviS13,
author = {Mojtaba Mahdavi and
Mahdi Shabany},
title = {Novel {MIMO} Detection Algorithm for High-Order Constellations in
the Complex Domain},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {834--847},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2196296},
doi = {10.1109/TVLSI.2012.2196296},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MahdaviS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MahdizadehM13,
author = {Hossein Mahdizadeh and
Massoud Masoumi},
title = {Novel Architecture for Efficient {FPGA} Implementation of Elliptic
Curve Cryptographic Processor Over {\textdollar}\{{\textbackslash}rm
GF\}(2\{163\}){\textdollar}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2330--2333},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2230410},
doi = {10.1109/TVLSI.2012.2230410},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MahdizadehM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MarrDHA13,
author = {Bo Marr and
Brian P. Degnan and
Paul E. Hasler and
David V. Anderson},
title = {Scaling Energy Per Operation via an Asynchronous Pipeline},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {147--151},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2178126},
doi = {10.1109/TVLSI.2011.2178126},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MarrDHA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MeherP13,
author = {Pramod Kumar Meher and
Sang Yoon Park},
title = {{CORDIC} Designs for Fixed Angle of Rotation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {217--228},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2187080},
doi = {10.1109/TVLSI.2012.2187080},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MeherP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MehriKMS13,
author = {Milad Mehri and
Mohammad Hossein Mazaheri Kouhani and
Nasser Masoumi and
Reza Sarvari},
title = {New Approach to {VLSI} Buffer Modeling, Considering Overshooting Effect},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1568--1572},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2211629},
doi = {10.1109/TVLSI.2012.2211629},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MehriKMS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MhambreyMC13,
author = {Siddhesh S. Mhambrey and
Satendra Kumar Maurya and
Lawrence T. Clark},
title = {Low Complexity Out-of-Order Issue Logic Using Static Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {380--384},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2184310},
doi = {10.1109/TVLSI.2012.2184310},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MhambreyMC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MiettinenHRV13,
author = {Pekka Miettinen and
Mikko Honkala and
Janne Roos and
Martti Valtonen},
title = {Sparsification of Dense Capacitive Coupling of Interconnect Models},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1955--1959},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227284},
doi = {10.1109/TVLSI.2012.2227284},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MiettinenHRV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MirsaeediTA13,
author = {Minoo Mirsaeedi and
Andres J. Torres and
Mohab H. Anis},
title = {Litho-Friendly Decomposition Method for Self-Aligned Double Patterning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1469--1480},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2212473},
doi = {10.1109/TVLSI.2012.2212473},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MirsaeediTA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MohammadHE13,
author = {Baker Mohammad and
Dirar Homouz and
Hazem Elgabra},
title = {Robust Hybrid Memristor-CMOS Memory: Modeling and Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2069--2079},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227519},
doi = {10.1109/TVLSI.2012.2227519},
timestamp = {Sat, 16 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MohammadHE13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MontonEB13,
author = {Marius Monton and
Jakob Engblom and
Mark Burton},
title = {Checkpointing for Virtual Platforms and SystemC-TLM},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {133--141},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2181881},
doi = {10.1109/TVLSI.2011.2181881},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MontonEB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MostafaAE13,
author = {Hassan Mostafa and
Mohab Anis and
Mohamed I. Elmasry},
title = {Statistical {SRAM} Read Access Yield Improvement Using Negative Capacitance
Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {92--101},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2178046},
doi = {10.1109/TVLSI.2011.2178046},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MostafaAE13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NarayananSZT13,
author = {Rajeev Narayanan and
Ibtissem Seghaier and
Mohamed H. Zaki and
Sofi{\`{e}}ne Tahar},
title = {Statistical Run-Time Verification of Analog Circuits in Presence of
Noise and Process Variation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1811--1822},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2219083},
doi = {10.1109/TVLSI.2012.2219083},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NarayananSZT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NowrozWR13,
author = {Abdullah Nazma Nowroz and
Gary L. Woods and
Sherief Reda},
title = {Power Mapping of Integrated Circuits Using AC-Based Thermography},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1398--1409},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2211111},
doi = {10.1109/TVLSI.2012.2211111},
timestamp = {Tue, 07 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NowrozWR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OgasaharaHKO13,
author = {Yasuhiro Ogasahara and
Masanori Hashimoto and
Toshiki Kanamoto and
Takao Onoye},
title = {Supply Noise Suppression by Triple-Well Structure},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {781--785},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2192458},
doi = {10.1109/TVLSI.2012.2192458},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OgasaharaHKO13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OhLY13,
author = {Jinwook Oh and
Seungjin Lee and
Hoi{-}Jun Yoo},
title = {1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for
Low-Power Real-Time Object Recognition Processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {921--933},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2198249},
doi = {10.1109/TVLSI.2012.2198249},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OhLY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OmanaRGSMMK13,
author = {Martin Oma{\~{n}}a and
Daniele Rossi and
Daniele Giaffreda and
Roberto Specchia and
Cecilia Metra and
Marcin Marzencki and
Bozena Kaminska},
title = {Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless
Sensors and Their Possible Concurrent Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2286--2294},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2230036},
doi = {10.1109/TVLSI.2012.2230036},
timestamp = {Sun, 20 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OmanaRGSMMK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PalaniappanP13,
author = {Arun Palaniappan and
Samuel Palermo},
title = {A Design Methodology for Power Efficiency Optimization of High-Speed
Equalized-Electrical {I/O} Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1421--1431},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2211628},
doi = {10.1109/TVLSI.2012.2211628},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PalaniappanP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PanD013,
author = {Yangyang Pan and
Guiqiang Dong and
Tong Zhang},
title = {Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled
Technology Nodes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1350--1354},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2210256},
doi = {10.1109/TVLSI.2012.2210256},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PanD013.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PanLSXZZ13,
author = {Yangyang Pan and
Yiran Li and
Hongbin Sun and
Wei Xu and
Nanning Zheng and
Tong Zhang},
title = {Exploring the Use of Emerging Nonvolatile Memory Technologies in Future
FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {771--775},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2195786},
doi = {10.1109/TVLSI.2012.2195786},
timestamp = {Mon, 19 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PanLSXZZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Parhi13,
author = {Keshab K. Parhi},
title = {Comments on "Low-energy {CSMT} carry generators and binary adders"},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {791},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190771},
doi = {10.1109/TVLSI.2012.2190771},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Parhi13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkJRJ13,
author = {Jung{-}Hyun Park and
Dong{-}Hoon Jung and
Kyungho Ryu and
Seong{-}Ook Jung},
title = {{ADDLL} for Clock-Deskew Buffer in High-Performance SoCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1368--1373},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2210742},
doi = {10.1109/TVLSI.2012.2210742},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkJRJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkOKWW13,
author = {Jeongha Park and
Saeroonter Oh and
Soyoung Kim and
H.{-}S. Philip Wong and
S. Simon Wong},
title = {Impact of {III-V} and Ge Devices on Circuit Performance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1189--1200},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2210450},
doi = {10.1109/TVLSI.2012.2210450},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkOKWW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkY13,
author = {Won Ho Park and
Chih{-}Kong Ken Yang},
title = {Effects of Using Advanced Cooling Systems on the Overall Power Consumption
of Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1644--1654},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2217386},
doi = {10.1109/TVLSI.2012.2217386},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PeiraviA13,
author = {Ali Peiravi and
Mohammad Asyaei},
title = {Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino
Circuit for Wide Fan-In Gates},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {934--943},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2202408},
doi = {10.1109/TVLSI.2012.2202408},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PeiraviA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PengHKZ13,
author = {Yanjie Peng and
Xinming Huang and
Andrew G. Klein and
Kai Zhang},
title = {Design and Implementation of a Low-Complexity Symbol Detector for
Sparse Channels},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1506--1515},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2211902},
doi = {10.1109/TVLSI.2012.2211902},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PengHKZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PengYCT13,
author = {Ke Peng and
Mahmut Yilmaz and
Krishnendu Chakrabarty and
Mohammad Tehranipoor},
title = {Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay
Defects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1129--1142},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2205026},
doi = {10.1109/TVLSI.2012.2205026},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PengYCT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PhamFM13,
author = {Thinh Hung Pham and
Suhaib A. Fahmy and
Ian Vince McLoughlin},
title = {Low-Power Correlation for {IEEE} 802.16 {OFDM} Synchronization on
{FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1549--1553},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2210917},
doi = {10.1109/TVLSI.2012.2210917},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PhamFM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PhamMKK13,
author = {Phi{-}Hung Pham and
Phuong Mau and
Jungmoon Kim and
Chulwoo Kim},
title = {An On-Chip Network Fabric Supporting Coarse-Grained Processor Array},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {178--182},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2181546},
doi = {10.1109/TVLSI.2011.2181546},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PhamMKK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PhamSPK13,
author = {Phi{-}Hung Pham and
Junyoung Song and
Jongsun Park and
Chulwoo Kim},
title = {Design and Implementation of an On-Chip Permutation Network for Multiprocessor
System-On-Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {173--177},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2181545},
doi = {10.1109/TVLSI.2011.2181545},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PhamSPK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PierceT13,
author = {Luke Pierce and
Spyros Tragoudas},
title = {Enhanced Secure Architecture for Joint Action Test Group Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1342--1345},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2208209},
doi = {10.1109/TVLSI.2012.2208209},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PierceT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PlosHFSC13,
author = {Thomas Plos and
Michael Hutter and
Martin Feldhofer and
Maksimiljan Stiglic and
Francesco Cavaliere},
title = {Security-Enabled Near-Field Communication Tag With Flexible Architecture
Supporting Asymmetric Cryptography},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {1965--1974},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227849},
doi = {10.1109/TVLSI.2012.2227849},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PlosHFSC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13,
author = {Irith Pomeranz},
title = {Built-In Generation of Functional Broadside Tests Using a Fixed Hardware
Structure},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {124--132},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2179682},
doi = {10.1109/TVLSI.2011.2179682},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13a,
author = {Irith Pomeranz},
title = {Computing Two-Pattern Test Cubes for Transition Path Delay Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {475--485},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2188727},
doi = {10.1109/TVLSI.2012.2188727},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13b,
author = {Irith Pomeranz},
title = {Broadside and Skewed-Load Tests Under Primary Input Constraints},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {776--780},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2192300},
doi = {10.1109/TVLSI.2012.2192300},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13c,
author = {Irith Pomeranz},
title = {Reduced Power Transition Fault Test Sets for Circuits With Independent
Scan Chain Modes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1354--1359},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2207137},
doi = {10.1109/TVLSI.2012.2207137},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13d,
author = {Irith Pomeranz},
title = {Transition Fault Simulation Considering Broadside Tests as Partially-Functional
Broadside Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1359--1363},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2206835},
doi = {10.1109/TVLSI.2012.2206835},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13e,
author = {Irith Pomeranz},
title = {On Test Compaction of Broadside and Skewed-Load Test Cubes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1705--1714},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2217360},
doi = {10.1109/TVLSI.2012.2217360},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13e.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13f,
author = {Irith Pomeranz},
title = {Functional Broadside Templates for Low-Power Test Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2321--2325},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2228510},
doi = {10.1109/TVLSI.2012.2228510},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13f.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PostmanKEPC13,
author = {Jacob Postman and
Tushar Krishna and
Christopher Edmonds and
Li{-}Shiuan Peh and
Patrick Chiang},
title = {{SWIFT:} {A} Low-Power Network-On-Chip Implementing the Token Flow
Control Router Architecture With Swing-Reduced Interconnects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1432--1446},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2211904},
doi = {10.1109/TVLSI.2012.2211904},
timestamp = {Fri, 03 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PostmanKEPC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PurohitCMV13,
author = {Sohan Purohit and
Sai Rahul Chalamalasetti and
Martin Margala and
Wim Vanderbauwhede},
title = {Throughput/Resource-Efficient Reconfigurable Processor for Multimedia
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1346--1350},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2206063},
doi = {10.1109/TVLSI.2012.2206063},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PurohitCMV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PurohitCMV13a,
author = {Sohan Purohit and
Sai Rahul Chalamalasetti and
Martin Margala and
Wim Vanderbauwhede},
title = {Design and Evaluation of High-Performance Processing Elements for
Reconfigurable Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1915--1927},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2220868},
doi = {10.1109/TVLSI.2012.2220868},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PurohitCMV13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QaziTDSC13,
author = {Masood Qazi and
Mehul Tikekar and
Lara Dolecek and
Devavrat Shah and
Anantha P. Chandrakasan},
title = {Technique for Efficient Evaluation of {SRAM} Timing Failure},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1558--1562},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2212254},
doi = {10.1109/TVLSI.2012.2212254},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/QaziTDSC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ReviriegoMF13,
author = {Pedro Reviriego and
Juan Antonio Maestro and
Mark F. Flanagan},
title = {Error Detection in Majority Logic Decoding of Euclidean Geometry Low
Density Parity Check {(EG-LDPC)} Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {156--159},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2179681},
doi = {10.1109/TVLSI.2011.2179681},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ReviriegoMF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ReviriegoPM13,
author = {Pedro Reviriego and
Salvatore Pontarelli and
Juan Antonio Maestro},
title = {Concurrent Error Detection for Orthogonal Latin Squares Encoders and
Syndrome Computation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2334--2338},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2230655},
doi = {10.1109/TVLSI.2012.2230655},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ReviriegoPM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Rius13,
author = {Josep Rius},
title = {IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform
Power Consumption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {512--522},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2188918},
doi = {10.1109/TVLSI.2012.2188918},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Rius13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RossiMCSVSWEPG13,
author = {Davide Rossi and
Claudio Mucci and
Fabio Campi and
Simone Spolzino and
Luca Vanzolini and
Henning Sahlbach and
Sean Whitty and
Rolf Ernst and
Wolfram Putzke{-}R{\"{o}}ming and
Roberto Guerrieri},
title = {Application Space Exploration of a Heterogeneous Run-Time Configurable
Digital Signal Processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {193--205},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2185963},
doi = {10.1109/TVLSI.2012.2185963},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RossiMCSVSWEPG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RoyRM13,
author = {Sujoy Sinha Roy and
Chester Rebeiro and
Debdeep Mukhopadhyay},
title = {Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based
FPGAs for Area and Speed},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {901--909},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2198502},
doi = {10.1109/TVLSI.2012.2198502},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RoyRM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SaeedSA13,
author = {Samah Mohamed Saeed and
Ozgur Sinanoglu and
Sobeeh Almukhaizim},
title = {Predictive Techniques for Projecting Test Data Volume Compression},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1762--1766},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2217359},
doi = {10.1109/TVLSI.2012.2217359},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SaeedSA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SamieDTPB13,
author = {Mohammad Samie and
Gabriel Dragffy and
Andy M. Tyrrell and
Tony Pipe and
Paul Bremner},
title = {Novel Bio-Inspired Approach for Fault-Tolerant {VLSI} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1878--1891},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2220793},
doi = {10.1109/TVLSI.2012.2220793},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SamieDTPB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShabanyYG13,
author = {Mahdi Shabany and
Ameer Youssef and
P. Glenn Gulak},
title = {High-Throughput 0.13-{\(\mathrm{\mu}\)}m {CMOS} Lattice Reduction
Core Supporting 880 Mb/s Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {848--861},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2198927},
doi = {10.1109/TVLSI.2012.2198927},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShabanyYG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShiLXZ13,
author = {Liang Shi and
Jianhua Li and
Chun Jason Xue and
Xuehai Zhou},
title = {Cooperating Virtual Memory and Write Buffer Management for Flash-Based
Storage Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {706--719},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2193909},
doi = {10.1109/TVLSI.2012.2193909},
timestamp = {Mon, 07 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShiLXZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShiWY13,
author = {Feng Shi and
Xuebin Wu and
Zhiyuan Yan},
title = {New Crosstalk Avoidance Codes Based on a Novel Pattern Classification},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1892--1902},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2219565},
doi = {10.1109/TVLSI.2012.2219565},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShiWY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShiZS13,
author = {Bing Shi and
Yufu Zhang and
Ankur Srivastava},
title = {Dynamic Thermal Management Under Soft Thermal Constraints},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2045--2054},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227854},
doi = {10.1109/TVLSI.2012.2227854},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShiZS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShimH13,
author = {Kyu{-}Nam Shim and
Jiang Hu},
title = {Boostable Repeater Design for Variation Resilience in {VLSI} Interconnects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1619--1631},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2212733},
doi = {10.1109/TVLSI.2012.2212733},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShimH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShimHS13,
author = {Kyu{-}Nam Shim and
Jiang Hu and
Jos{\'{e}} Silva{-}Mart{\'{\i}}nez},
title = {Dual-Level Adaptive Supply Voltage System for Variation Resilience},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1041--1052},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2203326},
doi = {10.1109/TVLSI.2012.2203326},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShimHS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShoaibJV13,
author = {Mohammed Shoaib and
Niraj K. Jha and
Naveen Verma},
title = {Algorithm-Driven Architectural Design Space Exploration of Domain-Specific
Medical-Sensor Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1849--1862},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2220161},
doi = {10.1109/TVLSI.2012.2220161},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShoaibJV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShojaeiDB13,
author = {Hamid Shojaei and
Azadeh Davoodi and
Twan Basten},
title = {Collaborative Multiobjective Global Routing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1308--1321},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2205717},
doi = {10.1109/TVLSI.2012.2205717},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShojaeiDB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShyuLHLLC13,
author = {Ya{-}Ting Shyu and
Jai{-}Ming Lin and
Chun{-}Po Huang and
Cheng{-}Wu Lin and
Ying{-}Zu Lin and
Soon{-}Jyh Chang},
title = {Effective and Efficient Approach for Power Reduction by Using Multi-Bit
Flip-Flops},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {624--635},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190535},
doi = {10.1109/TVLSI.2012.2190535},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShyuLHLLC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SinkarPK13,
author = {Abhishek A. Sinkar and
Taejoon Park and
Nam Sung Kim},
title = {Clamping Virtual Supply Voltage of Power-Gated Circuits for Active
Leakage Reduction and Gate-Oxide Reliability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {580--584},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2189422},
doi = {10.1109/TVLSI.2012.2189422},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SinkarPK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SmolyakovGGL13,
author = {Vadim Smolyakov and
P. Glenn Gulak and
Timothy Gallagher and
Curtis Ling},
title = {Fault-Tolerant Embedded-Memory Strategy for Baseband Signal Processing
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1299--1307},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2208208},
doi = {10.1109/TVLSI.2012.2208208},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SmolyakovGGL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongAJKK13,
author = {Minyoung Song and
Sunghoon Ahn and
Inhwa Jung and
Yongtae Kim and
Chulwoo Kim},
title = {Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1234--1245},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2210290},
doi = {10.1109/TVLSI.2012.2210290},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SongAJKK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongKAPK13,
author = {Minyoung Song and
Young{-}Ho Kwak and
Sunghoon Ahn and
Hojin Park and
Chulwoo Kim},
title = {10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {11},
pages = {2080--2093},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2227068},
doi = {10.1109/TVLSI.2012.2227068},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SongKAPK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SousaAC13,
author = {Leonel Sousa and
Samuel Antao and
Ricardo Chaves},
title = {On the Design of {RNS} Reverse Converters for the Four-Moduli Set
{\textdollar}\{{\textbackslash}bf{\textbackslash}\{2\{{\textbackslash}mmb
n\}+1, 2\{{\textbackslash}mmb n\}-1, 2\{{\textbackslash}mmb n\}, 2\{\{{\textbackslash}mmb
n\}+1\}+1{\textbackslash}\}\}{\textdollar}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1945--1949},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2219564},
doi = {10.1109/TVLSI.2012.2219564},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SousaAC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SuLH13,
author = {Jun{-}Ren Su and
Te{-}Wen Liao and
Chung{-}Chih Hung},
title = {All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable
Duty Cycle},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1154--1164},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2205168},
doi = {10.1109/TVLSI.2012.2205168},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SuLH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SunC13,
author = {Yang Sun and
Joseph R. Cavallaro},
title = {{VLSI} Architecture for Layered Decoding of {QC-LDPC} Codes With High
Circulant Weight},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1960--1964},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2220388},
doi = {10.1109/TVLSI.2012.2220388},
timestamp = {Tue, 06 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SunC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TakeuchiSSKYM13,
author = {Kan Takeuchi and
Masaki Shimada and
Takao Sato and
Yusaku Katsuki and
Hiroumi Yoshikawa and
Hiroaki Matsushita},
title = {Spatial Distribution Measurement of Dynamic Voltage Drop Caused by
Pulse and Periodic Injection of Spot Noise},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {164--168},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2180742},
doi = {10.1109/TVLSI.2011.2180742},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TakeuchiSSKYM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TaoF13,
author = {Chengwu Tao and
Ayman A. Fayed},
title = {{PWM} Control Architecture With Constant Cycle Frequency Hopping and
Phase Chopping for Spur-Free Operation in Buck Regulators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1596--1607},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2217515},
doi = {10.1109/TVLSI.2012.2217515},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TaoF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TayCL13,
author = {Thian Fatt Tay and
Chip{-}Hong Chang and
Jeremy Yung Shern Low},
title = {Efficient {VLSI} Implementation of {\textdollar}2\{\{n\}\}{\textdollar}
Scaling of Signed Integer in {RNS} {\textdollar}\{{\textbackslash}\{2\{n\}-1,
2\{n\}, 2\{n\}+1{\textbackslash}\}\}{\textdollar}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1936--1940},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2221752},
doi = {10.1109/TVLSI.2012.2221752},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TayCL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThapliyalRK13,
author = {Himanshu Thapliyal and
Nagarajan Ranganathan and
Saurabh Kotiyal},
title = {Design of Testable Reversible Sequential Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1201--1209},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2209688},
doi = {10.1109/TVLSI.2012.2209688},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ThapliyalRK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TheodorouKPG13,
author = {Giorgos Theodorou and
Nektarios Kranitis and
Antonis M. Paschalis and
Dimitris Gizopoulos},
title = {Software-Based Self Test Methodology for On-Line Testing of {L1} Caches
in Multithreaded Multicore Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {786--790},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2191000},
doi = {10.1109/TVLSI.2012.2191000},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TheodorouKPG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThomasL13,
author = {David B. Thomas and
Wayne Luk},
title = {The {LUT-SR} Family of Uniform Random Number Generators for {FPGA}
Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {761--770},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2194171},
doi = {10.1109/TVLSI.2012.2194171},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ThomasL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThomasL13a,
author = {David B. Thomas and
Wayne Luk},
title = {Multiplierless Algorithm for Multivariate Gaussian Random Number Generation
in FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2193--2205},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2228017},
doi = {10.1109/TVLSI.2012.2228017},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ThomasL13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TianZSLLXLC13,
author = {Wanyong Tian and
Yingchao Zhao and
Liang Shi and
Qing'an Li and
Jianhua Li and
Chun Jason Xue and
Minming Li and
Enhong Chen},
title = {Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1271--1284},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2208129},
doi = {10.1109/TVLSI.2012.2208129},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TianZSLLXLC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TodriBDGV13,
author = {Aida Todri and
Alberto Bosio and
Luigi Dilillo and
Patrick Girard and
Arnaud Virazel},
title = {Uncorrelated Power Supply Noise and Ground Bounce Consideration for
Test Pattern Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {958--970},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2197427},
doi = {10.1109/TVLSI.2012.2197427},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TodriBDGV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TodriKGBDV13,
author = {Aida Todri and
Sandip Kundu and
Patrick Girard and
Alberto Bosio and
Luigi Dilillo and
Arnaud Virazel},
title = {A Study of Tapered 3-D TSVs for Power and Thermal Integrity},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {306--319},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2187081},
doi = {10.1109/TVLSI.2012.2187081},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TodriKGBDV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TongC13,
author = {Ting{-}Chi Tong and
Yun{-}Nan Chang},
title = {Efficient Vector Graphics Rasterization Accelerator Using Optimized
Scan-Line Buffer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1246--1259},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2207413},
doi = {10.1109/TVLSI.2012.2207413},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TongC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VaccaGZ13,
author = {Marco Vacca and
Mariagrazia Graziano and
Maurizio Zamboni},
title = {Nanomagnetic Logic Microprocessor: Hierarchical Power Model},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1410--1420},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2211903},
doi = {10.1109/TVLSI.2012.2211903},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VaccaGZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangCYC13,
author = {Jinn{-}Shyan Wang and
Keng{-}Jui Chang and
Chingwei Yeh and
Shih{-}Chieh Chang},
title = {Embedding Repeaters in Silicon IPs for Cross-IP Interconnections},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {597--601},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190434},
doi = {10.1109/TVLSI.2012.2190434},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangCYC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangMC13,
author = {Hongyi Wang and
Yanzhao Ma and
Jun Cheng},
title = {Soft-Start Method With Small Capacitor Charged by Pulse Current and
Gain-Degeneration Error Amplifier for On-Chip {DC-DC} Power Converters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1447--1453},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2211388},
doi = {10.1109/TVLSI.2012.2211388},
timestamp = {Tue, 16 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangMC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangZWYLPT13,
author = {Ying Wang and
Xuegong Zhou and
Lingli Wang and
Jian Yan and
Wayne Luk and
Chenglian Peng and
Jiarong Tong},
title = {{SPREAD:} {A} Streaming-Based Partially Reconfigurable Architecture
and Programming Model},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2179--2192},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2231101},
doi = {10.1109/TVLSI.2012.2231101},
timestamp = {Tue, 19 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangZWYLPT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WannerABGS13,
author = {Lucas Francisco Wanner and
Charwak Apte and
Rahul Balani and
Puneet Gupta and
Mani B. Srivastava},
title = {Hardware Variability-Aware Duty Cycling for Embedded Sensors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1000--1012},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2203325},
doi = {10.1109/TVLSI.2012.2203325},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WannerABGS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WhatmoughDBD13,
author = {Paul N. Whatmough and
Shidhartha Das and
David M. Bull and
Izzat Darwazeh},
title = {Circuit-Level Timing Error Tolerance for Low-Power {DSP} Filters and
Transforms},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {989--999},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2202930},
doi = {10.1109/TVLSI.2012.2202930},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WhatmoughDBD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WongC13,
author = {Justin S. J. Wong and
Peter Y. K. Cheung},
title = {Timing Measurement Platform for Arbitrary Black-Box Circuits Based
on Transition Probability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2307--2320},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2230280},
doi = {10.1109/TVLSI.2012.2230280},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WongC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WooSL13,
author = {Dong Hyuk Woo and
Nak Hee Seong and
Hsien{-}Hsin S. Lee},
title = {Pragmatic Integration of an {SRAM} Row Cache in Heterogeneous 3-D
{DRAM} Architecture Using {TSV}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {1--13},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2176761},
doi = {10.1109/TVLSI.2011.2176761},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WooSL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuM13,
author = {Kai{-}Chiang Wu and
Diana Marculescu},
title = {A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic
Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {367--379},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2184145},
doi = {10.1109/TVLSI.2012.2184145},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WunderlichAH13,
author = {Richard B. Wunderlich and
Farhan Adil and
Paul E. Hasler},
title = {Floating Gate-Based Field Programmable Mixed-Signal Array},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {8},
pages = {1496--1505},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2211049},
doi = {10.1109/TVLSI.2012.2211049},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WunderlichAH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XieHM13,
author = {Jiafeng Xie and
Jianjun He and
Pramod Kumar Meher},
title = {Low Latency Systolic Montgomery Multiplier for Finite Field {\textdollar}GF(2\{m\}){\textdollar}
Based on Pentanomials},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {385--389},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2185257},
doi = {10.1109/TVLSI.2012.2185257},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XieHM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XieMH13,
author = {Jiafeng Xie and
Pramod Kumar Meher and
Jianjun He},
title = {Low-Complexity Multiplier for GF(2\({}^{\mbox{m}}\)) Based on All-One
Polynomials},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {168--173},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2181434},
doi = {10.1109/TVLSI.2011.2181434},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XieMH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XieNXWZYWWL13,
author = {Yiyuan Xie and
Mahdi Nikdast and
Jiang Xu and
Xiaowen Wu and
Wei Zhang and
Yaoyao Ye and
Xuan Wang and
Zhehui Wang and
Weichen Liu},
title = {Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical
Networks-on-Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1823--1836},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2220573},
doi = {10.1109/TVLSI.2012.2220573},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XieNXWZYWWL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuPTBM13,
author = {Hu Xu and
Vasilis F. Pavlidis and
Xifan Tang and
Wayne P. Burleson and
Giovanni De Micheli},
title = {Timing Uncertainty in 3-D Clock Trees Due to Process Variations and
Power Supply Noise},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2226--2239},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2230035},
doi = {10.1109/TVLSI.2012.2230035},
timestamp = {Thu, 11 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuPTBM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangJC13,
author = {Isaak Yang and
Sung Hoon Jung and
Kwang{-}Hyun Cho},
title = {Self-Repairing Digital System With Unified Recovery Process Inspired
by Endocrine Cellular Communication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1027--1040},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2203618},
doi = {10.1109/TVLSI.2012.2203618},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangJC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangT13,
author = {Joon{-}Sung Yang and
Nur A. Touba},
title = {Improved Trace Buffer Observation via Selective Data Capture Using
2-D Compaction for Post-Silicon Debug},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {320--328},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2183399},
doi = {10.1109/TVLSI.2012.2183399},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangTC13,
author = {Kai{-}Jiun Yang and
Shang{-}Ho Tsai and
Gene C. H. Chuang},
title = {{MDC} {FFT/IFFT} Processor With Variable Length for {MIMO-OFDM} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {720--731},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2194315},
doi = {10.1109/TVLSI.2012.2194315},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangTC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YeXWZWNWL13,
author = {Yaoyao Ye and
Jiang Xu and
Xiaowen Wu and
Wei Zhang and
Xuan Wang and
Mahdi Nikdast and
Zhehui Wang and
Weichen Liu},
title = {System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {292--305},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2185524},
doi = {10.1109/TVLSI.2012.2185524},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YeXWZWNWL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YilmazM13,
author = {Yalcin Yilmaz and
Pinaki Mazumder},
title = {Nonvolatile Nanopipelining Logic Using Multiferroic Single-Domain
Nanomagnets},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1181--1188},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2205594},
doi = {10.1109/TVLSI.2012.2205594},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YilmazM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YilmazOB13,
author = {Ender Yilmaz and
Sule Ozev and
Kenneth M. Butler},
title = {Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based
Process Monitoring},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {6},
pages = {1116--1128},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2205027},
doi = {10.1109/TVLSI.2012.2205027},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YilmazOB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YoonKKLKCPK13,
author = {Jae{-}Sung Yoon and
Jeong{-}Hyun Kim and
Hyo{-}Eun Kim and
Won{-}Young Lee and
Seok{-}Hoon Kim and
Kyusik Chung and
Jun{-}Seok Park and
Lee{-}Sup Kim},
title = {A Unified Graphics and Vision Processor With a 0.89 {\(\mathrm{\mu}\)}W/fps
Pose Estimation Engine for Augmented Reality},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {2},
pages = {206--216},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2186157},
doi = {10.1109/TVLSI.2012.2186157},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YoonKKLKCPK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YouHLTKCW13,
author = {Jhih{-}Wei You and
Shi{-}Yu Huang and
Yu{-}Hsiang Lin and
Meng{-}Hsiu Tsai and
Ding{-}Ming Kwai and
Yung{-}Fa Chou and
Cheng{-}Wen Wu},
title = {In-Situ Method for {TSV} Delay Testing and Characterization Using
Input Sensitivity Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {443--453},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2187543},
doi = {10.1109/TVLSI.2012.2187543},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YouHLTKCW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangC13,
author = {Yanheng Zhang and
Chris Chu},
title = {RegularRoute: An Efficient Detailed Router Applying Regular Routing
Patterns},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1655--1668},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2214491},
doi = {10.1109/TVLSI.2012.2214491},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangC13a,
author = {Yanheng Zhang and
Chris Chu},
title = {Fast and Effective Placement Refinement for Routability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1751--1756},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2214408},
doi = {10.1109/TVLSI.2012.2214408},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangC13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangL13,
author = {Xiwen Zhang and
Hoi Lee},
title = {Gain-Enhanced Monolithic Charge Pump With Simultaneous Dynamic Gate
and Substrate Control},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {593--596},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2190149},
doi = {10.1109/TVLSI.2012.2190149},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangLL13,
author = {Ying Zhang and
Huawei Li and
Xiaowei Li},
title = {Automatic Test Program Generation Using Executing-Trace-Based Constraint
Extraction for Embedded Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1220--1233},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2208130},
doi = {10.1109/TVLSI.2012.2208130},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangLL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangWP13,
author = {Wei Zhang and
Hao Wang and
Boyang Pan},
title = {Reduced-Complexity {LCC} Reed-Solomon Decoder Based on Unified Syndrome
Computation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {5},
pages = {974--978},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2197030},
doi = {10.1109/TVLSI.2012.2197030},
timestamp = {Wed, 09 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangWP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhaoEA13,
author = {Xin Zhao and
Ahmet T. Erdogan and
Tughrul Arslan},
title = {High-Efficiency Customized Coarse-Grained Dynamically Reconfigurable
Architecture for {JPEG2000}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2343--2348},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2230034},
doi = {10.1109/TVLSI.2012.2230034},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhaoEA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhenZLHZ13,
author = {Shaowei Zhen and
Xiaohui Zhu and
Ping Luo and
Yajuan He and
Bo Zhang},
title = {Digital Error Corrector for Phase Lead-Compensated Buck Converter
in {DVS} Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1747--1751},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2217513},
doi = {10.1109/TVLSI.2012.2217513},
timestamp = {Tue, 20 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhenZLHZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhengLPML13,
author = {Yuxiang Zheng and
Jin Liu and
Robert Payne and
Mark Morgan and
Hoi Lee},
title = {A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel
Data Communications in 0.13-{\(\mathrm{\mu}\)}m {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2274--2285},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2232319},
doi = {10.1109/TVLSI.2012.2232319},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhengLPML13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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