BibTeX record conf/isscc/FujiwaraLPLHLLC19

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@inproceedings{DBLP:conf/isscc/FujiwaraLPLHLLC19,
  author    = {Hidehiro Fujiwara and
               Chih{-}Yu Lin and
               Hsien{-}Yu Pan and
               Cheng{-}Han Lin and
               Po{-}Yi Huang and
               Kao{-}Cheng Lin and
               Jhon{-}Jhy Liaw and
               Yen{-}Huei Chen and
               Hung{-}Jen Liao and
               Jonathan Chang},
  title     = {A 7nm 2.1GHz Dual-Port {SRAM} with {WL-RC} Optimization and Dummy-Read-Recovery
               Circuitry to Mitigate Read- Disturb-Write Issue},
  booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
               San Francisco, CA, USA, February 17-21, 2019},
  pages     = {390--392},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {https://doi.org/10.1109/ISSCC.2019.8662415},
  doi       = {10.1109/ISSCC.2019.8662415},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/FujiwaraLPLHLLC19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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