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Tadayuki Taura
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2020 – today
- 2020
- [c5]Yuri Kato, Yoshihisa Matoba, Katsumi Honda, Koji Ogawa, Kan Shimizu, Masataka Maehara, Atsushi Fujiwara, Aoi Odawara, Chigusa Yamane, Naohiko Kimizuka, Jun Ogi, Tadayuki Taura, Ikuro Suzuki, Yusuke Oike:
High-Density and Large-Scale MEA System Featuring 236, 880 Electrodes at 11.72μm Pitch for Neuronal Network Analysis. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c4]Tsukasa Miura, Masaki Sakakibara, Hirotsugu Takahashi, Tadayuki Taura, Keiji Tatani, Yusuke Oike, Takayuki Ezaki:
A 6.9 μm Pixel-Pitch 3D Stacked Global Shutter CMOS Image Sensor with 3M Cu-Cu connections. 3DIC 2019: 1-2 - 2018
- [j5]Masaki Sakakibara, Koji Ogawa, Shin Sakai, Yasuhisa Tochigi, Katsumi Honda, Hidekazu Kikuchi, Takuya Wada, Yasunobu Kamikubo, Tsukasa Miura, Masahiko Nakamizo, Naoki Jyo, Ryo Hayashibara, Shinya Miyata, Satoshi Yamamoto, Yoshiyuki Ota, Hirotsugu Takahashi, Tadayuki Taura, Yusuke Oike, Keiji Tatani, Takayuki Ezaki, Teruo Hirayama:
A 6.9-µm Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC. IEEE J. Solid State Circuits 53(11): 3017-3025 (2018) - [c3]Masaki Sakakibara, Koji Ogawa, Shin Sakai, Yasuhisa Tochigi, Katsumi Honda, Hidekazu Kikuchi, Takuya Wada, Yasunobu Kamikubo, Tsukasa Miura, Masahiko Nakamizo, Naoki Jyo, Ryo Hayashibara, Yohei Furukawa, Shinya Miyata, Satoshi Yamamoto, Yoshiyuki Ota, Hirotsugu Takahashi, Tadayuki Taura, Yusuke Oike, Keiji Tatani, Takashi Nagano, Takayuki Ezaki, Teruo Hirayama:
A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC. ISSCC 2018: 80-82 - 2012
- [c2]Masaki Sakakibara, Yusuke Oike, Takafumi Takatsuka, Akihiko Kato, Katsumi Honda, Tadayuki Taura, Takashi Machida, Jun Okuno, Atsuhiro Ando, Taketo Fukuro, Tomohiko Asatsuma, Suzunori Endo, Junpei Yamamoto, Yasuhiro Nakano, Takumi Kaneshige, Ikuhiro Yamamura, Takayuki Ezaki, Teruo Hirayama:
An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage. ISSCC 2012: 380-382
2000 – 2009
- 2006
- [c1]Yoshikazu Nitta, Yoshinori Muramatsu, Kiyotaka Amano, Takayuki Toyama, Jun Yamamoto, Koji Mishina, Atsushi Suzuki, Tadayuki Taura, Akihiko Kato, Masaru Kikuchi, Yukihiro Yasui, Hideo Nomura, Noriyuki Fukushima:
High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor. ISSCC 2006: 2024-2031 - 2002
- [j4]Toru Tanzawa, Akira Umezawa, Tadayuki Taura, Hitoshi Shiga, Tokumasa Hara, Yoshinori Takano, Takeshi Miyaba, Naoya Tokiwa, Kentaro Watanabe, Hiroshi Watanabe, Kazunori Masuda, Kiyomi Naruke, Hideo Kato, Shigeru Atsumi:
A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller. IEEE J. Solid State Circuits 37(11): 1485-1492 (2002) - 2001
- [j3]Toru Tanzawa, Akira Umezawa, Masao Kuriyama, Tadayuki Taura, Hironori Banba, Takeshi Miyaba, Hitoshi Shiga, Yoshinori Takano, Shigeru Atsumi:
Wordline voltage generating system for low-power low-voltage flash memories. IEEE J. Solid State Circuits 36(1): 55-63 (2001) - 2000
- [j2]Toru Tanzawa, Yoshinori Takano, Tadayuki Taura, Shigeru Atsumi:
Design of a sense circuit for low-voltage flash memories. IEEE J. Solid State Circuits 35(10): 1415-1421 (2000) - [j1]Shigeru Atsumi, Akira Umezawa, Tooru Tanzawa, Tadayuki Taura, Hitoshi Shiga, Yoshinori Takano, Takeshi Miyaba, Michiharu Matsui, Hiroshi Watanabe, Kazuaki Isobe, Shota Kitamura, Seiji Yamada, Masanobu Saito, Seiichi Mori, Toshiharu Watanabe:
A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. IEEE J. Solid State Circuits 35(11): 1648-1654 (2000)
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