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ORCIDDominique Borrione
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2010 – 2019
- 2019
[j13]Guillaume Plassan
, Katell Morin-Allory, Dominique Borrione:
Mining Missing Assumptions from Counter-Examples. ACM Trans. Embed. Comput. Syst. 18(1): 3:1-3:25 (2019)- 2017
- [j12]Fatemeh Negin Javaheri, Katell Morin-Allory, Dominique Borrione:
Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 869-882 (2017) - [c57]Guillaume Plassan, Katell Morin-Allory, Dominique Borrione:
Extraction of missing formal assumptions in under-constrained designs. MEMOCODE 2017: 94-103 - 2016
- [c56]Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Fahim Rahim, Shaker Sarwary, Dominique Borrione:
Conclusively verifying clock-domain crossings in very large hardware designs. VLSI-SoC 2016: 1-6 - [c55]Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Shaker Sarwary, Dominique Borrione:
Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings. VLSI-SoC (Selected Papers) 2016: 108-129 - 2015
- [j11]Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione:
Efficient and Correct by Construction Assertion-Based Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2890-2901 (2015) - [c54]Mejid Kebaili, Katell Morin-Allory, Jean-Christophe Brignone, Dominique Borrione:
Enabler-based synchronizer model for clock domain crossing static verification. FDL 2015: 11-17 - 2014
- [c53]Zeineb Bel Hadj Amor, Laurence Pierre, Dominique Borrione:
A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow. VLSI-SoC 2014: 1-6 - 2013
- [c52]Dominique Borrione, Ashraf M. Salem:
Application of formal methods for design space exploration and refinement. FDL 2013: 1 - [c51]Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione:
Fast prototyping from assertions: A pragmatic approach. MEMOCODE 2013: 23-32 - [c50]Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione:
SyntHorus-2: Automatic prototyping from PSL. VLSI-SoC 2013: 72-77 - 2010
- [j10]Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic:
Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1436-1448 (2010)
2000 – 2009
- 2009
- [j9]Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz:
A Formal Approach to the Verification of Networks on Chip. EURASIP J. Embed. Syst. 2009 (2009) - [c49]Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre:
High-level symbolic simulation for automatic model extraction. DDECS 2009: 218-221 - [c48]Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic:
MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI 2009: 75-80 - [c47]Yann Oddos, Katell Morin-Allory, Dominique Borrione:
From Assertion-Based Verification to Assertion-Based Synthesis. VLSI-SoC 2009: 94-117 - 2008
- [j8]Julien Schmaltz, Dominique Borrione:
A functional formalization of on chip communications. Formal Aspects Comput. 20(3): 241-258 (2008) - [c46]Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic:
Proving and disproving assertion rewrite rules with automated theorem provers. HLDVT 2008: 56-63 - [c45]Yann Oddos, Katell Morin-Allory, Dominique Borrione:
Assertion-Based Design with Horus. MEMOCODE 2008: 75-76 - [c44]Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz:
Executable formal specification and validation of NoC communication infrastructures. SBCCI 2008: 176-181 - 2007
- [j7]Katell Morin-Allory, Eric Gascard, Dominique Borrione:
Synthesis of Property Monitors for Online Fault Detection. J. Circuits Syst. Comput. 16(6): 943-960 (2007) - [c43]Yann Oddos, Katell Morin-Allory, Dominique Borrione:
Prototyping Generators for On-line Test Vector Generation Based on PSL Properties. DDECS 2007: 383-388 - [c42]Katell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione:
Asynchronous online-monitoring of logical and temporal assertions. FDL 2007: 286-290 - [c41]Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz:
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. NOCS 2007: 127-136 - 2006
- [c40]Julien Schmaltz, Dominique Borrione:
Towards a formal theory of on chip communications in the ACL2 logic. ACL2 2006: 47-56 - [c39]Julien Schmaltz, Dominique Borrione:
Formalizing On Chip Communications in a Functional Style. Trustworthy Software 2006 - [c38]Katell Morin-Allory, Dominique Borrione:
Proven correct monitors from PSL specifications. DATE 2006: 1246-1251 - [c37]Katell Morin-Allory, Dominique Borrione:
On-line Monitoring of Properties Built on Regular Expressions. FDL 2006: 249-255 - [c36]Katell Morin-Allory, Laurent Fesquet, Dominique Borrione:
Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping 2006: 98-102 - [c35]Yann Oddos, Katell Morin-Allory, Dominique Borrione:
On-Line Test Vector Generation from Temporal Constraints Written in PSL. VLSI-SoC 2006: 397-402 - 2005
- [c34]Ghiath Al Sammane, Dominique Borrione, Remy Chevallier:
Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning. ACM Great Lakes Symposium on VLSI 2005: 260-263 - [c33]Katell Morin-Allory, Dominique Borrione:
A proof of correctness for the construction of property monitors. HLDVT 2005: 237-244 - [c32]Julien Schmaltz, Dominique Borrione:
A Generic Network on Chip Model. TPHOLs 2005: 310-325 - [c31]Diana Toma, Dominique Borrione:
Formal Verification of a SHA-1 Circuit Core Using ACL2. TPHOLs 2005: 326-341 - [e1]Dominique Borrione, Wolfgang J. Paul:
Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings. Lecture Notes in Computer Science 3725, Springer 2005, ISBN 3-540-29105-9 [contents] - 2004
- [c30]Diana Toma, Dominique Borrione, Ghiath Al Sammane:
Combining Several Paradigms for Circuit Validation and Verification. CASSIS 2004: 229-249 - [c29]Julien Schmaltz, Dominique Borrione:
A Functional Approach to the Formal Specification of Networks on Chip. FMCAD 2004: 52-66 - [c28]Ghiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione:
TheoSim: combining symbolic simulation and theorem proving for hardware verification. SBCCI 2004: 60-65 - 2003
- [c27]Ghiath Al Sammane, Diana Toma, Julien Schmaltz, Pierre Ostier, Dominique Borrione:
Constrained Symbolic Simulation with Mathematica and ACL2. CHARME 2003: 150-157 - [c26]Dominique Borrione, Menouer Boubekeur:
Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications. FDL 2003: 481-492 - [c25]Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Siriani:
An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. HICSS 2003: 279 - [c24]Emil Dumitrescu, Dominique Borrione:
Symbolic Simulation as a Simplifying Strategy for SoC Verification. IWSOC 2003: 378-383 - [c23]Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani:
Validation of Asynchronous Circuit Specifications Using IF/CADP. VLSI-SoC (Selected Papers) 2003: 85-100 - [c22]Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani:
Validation of asynchronous circuit specifications using IF/CADP. VLSI-SOC 2003: 86-91 - 2002
- [c21]Joel Blasquez, Marten van Hulst, Andrea Fedeli, Jean-Luc Lambert, Dominique Borrione, Coby Hanoch, Pierre Bricaud:
Formal Verification Techniques: Industrial Status and Perspectives. DATE 2002: 1050 - [c20]Jorgiano Vidal, David Déharbe, Dominique Borrione:
Improving Static Ordering of BDDs for Reachability Analysis. IWLS 2002: 73-77 - 2001
- [c19]Sherief Reda, Ayman Wahba, Ashraf Salem, Dominique Borrione, M. Ghonaimy:
On the use of don't cares during symbolic reachability analysis. ISCAS (5) 2001: 121-124 - 2000
- [j6]Vanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin:
Using the ACL2 Theorem Prover to Reason about VHDL Components. RITA 7(1): 129-148 (2000) - [j5]Dominique Borrione, Julia Dushina, Laurence V. Pierre:
A compositional model for the functional verification of high-level synthesis results. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 526-530 (2000) - [c18]Vanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin:
An ACL2 Model of VHDL for Symbolic Simulation and Formal Verification. SBCCI 2000: 269-274
1990 – 1999
- 1999
- [c17]Raimund Ubar, Dominique Borrione:
Design Error Diagnosis in Digital Circuits without Error Model. VLSI 1999: 281-292 - 1998
- [c16]Raimund Ubar, Dominique Borrione:
Generation of Tests for the Localization of Single Gate Design Errors in Combinational Circuits using the Stuck-at Fault Model. SBCCI 1998: 51-54 - [c15]Dominique Borrione, Julia Dushina, Laurence Pierre:
Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis. SBCCI 1998: 99-102 - 1997
- [c14]Dominique Borrione, F. Vestman, H. Bouamama:
An approach to Verilog-VHDL interoperability for synchronous designs. CHARME 1997: 65-87 - [c13]Ayman M. Wahba, Dominique Borrione:
Connection error location and correction in combinational circuits. ED&TC 1997: 235-241 - 1996
- [j4]Ayman M. Wahba, Dominique Borrione:
A method for automatic design error location and correction in combinational logic circuits. J. Electron. Test. 8(2): 113-127 (1996) - [c12]Ayman M. Wahba, Dominique Borrione:
Automatic diagnosis may replace simulation for correcting simple design errors. EURO-DAC 1996: 476-481 - [c11]Dominique Borrione, H. Bouamama, David Déharbe, C. Le Faou, Ayman M. Wahba:
HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment. FMCAD 1996: 450-467 - 1995
- [j3]Dominique Borrione, Ashraf M. Salem:
Denotational Semantics of a Synchronous VHDL Subset. Formal Methods Syst. Des. 7(1/2): 53-71 (1995) - [c10]Ayman M. Wahba, Dominique Borrione:
Design error diagnosis in sequential circuits. CHARME 1995: 171-188 - [c9]David Déharbe, Dominique Borrione:
Semantics of a verification-oriented subset of VHDL. CHARME 1995: 293-310 - 1994
- [c8]Catherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto:
A process algebra interpretation of a verification oriented overlanguage of VHDL. EURO-DAC 1994: 506-511 - 1992
- [j2]Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem:
Formal Verification of VHDL Descriptions in the Prevail Environment. IEEE Des. Test Comput. 9(2): 42-56 (1992) - [j1]Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby:
Three Decades of HDLs: Part II, Conlan Through Verilog. IEEE Des. Test Comput. 9(3): 54-63 (1992)
1980 – 1989
- 1989
- [c7]Dominique Borrione, Paolo Prinetto:
Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis. IFIP Congress 1989: 233-240 - 1988
- [c6]Dominique Borrione, Paolo Camurati, J. L. Paillet, Paolo Prinetto:
A functional approach to formal hardware verification: the MTI experience. ICCD 1988: 592-595 - 1983
- [b3]Robert Piloty, Dominique Borrione, Mario Barbacci, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly:
CONLAN Report. Lecture Notes in Computer Science 151, Springer 1983, ISBN 3-540-12275-3 - 1982
- [c5]Robert Piloty, Dominique Borrione:
The conlan project: Status and future plans. DAC 1982: 202-212 - 1981
- [b2]Dominique Borrione:
Langages de description de systèmes logiques : propositions pour une méthode formelle de définition. Grenoble Institute of Technology, France, 1981 - 1980
- [c4]Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly:
CONLAN: a formal construction method for hardware description languages: basic principles. AFIPS National Computer Conference 1980: 209-217 - [c3]Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly:
CONLAN: a formal construction method for hardware description languages: language derivation. AFIPS National Computer Conference 1980: 219-227 - [c2]Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly:
CONLAN: a formal construction method for hardware description languages: language application. AFIPS National Computer Conference 1980: 229-236 - [c1]Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly:
An Overview of CONLAN: A Formal Construction Method for Hardware Description Language. IFIP Congress 1980: 199-204
1970 – 1979
- 1976
- [b1]Dominique Borrione:
LASCAR : un langage pour la simulation et l'évaluation des architectures d'ordinateurs. Joseph Fourier University, Grenoble, France, 1976
Coauthor Index
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