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ORCIDPeter Zipf
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- affiliation: University of Kassel, Germany
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2020 – today
- 2023
[j16]Nicolai Fiege
, Peter Zipf:
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining. ACM Trans. Reconfigurable Technol. Syst. 16(3): 49:1-49:32 (2023)- [c83]Martin Hardieck, Tobias Habermann, Fabian Wagner, Michael Mecik, Martin Kumm, Peter Zipf:
More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers. ISCAS 2023: 1-5 - 2022
- [j15]Patrick Sittel, Nicolai Fiege, John Wickerson, Peter Zipf:
Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 614-627 (2022) - [c82]Nicolai Fiege, Patrick Sittel, Peter Zipf:
Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling. FCCM 2022: 1-2 - [c81]Nicolai Fiege, Patrick Sittel, Peter Zipf:
Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis. FPL 2022: 262-269 - [c80]Nicolai Fiege, Patrick Sittel, Peter Zipf:
Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals. FPL 2022: 322-326 - 2021
- [c79]Diego Botache, Florian Bethke, Martin Hardieck, Maarten Bieshaar, Ludwig Brabetz, Mohamed Ayeb, Peter Zipf, Bernhard Sick:
Towards Highly Automated Machine-Learning-Empowered Monitoring of Motor Test Stands. ACSOS 2021: 120-130 - 2020
- [j14]Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong:
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 115-128 (2020) - [c78]Patrick Sittel, John Wickerson, Martin Kumm, Peter Zipf:
Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design. ASP-DAC 2020: 568-573
2010 – 2019
- 2019
- [j13]Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong:
Unrolling Ternary Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 12(4): 22:1-22:23 (2019) - [c77]Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers:
Efficient Error-Tolerant Quantized Neural Network Accelerators. DFT 2019: 1-6 - [c76]Martin Hardieck, Martin Kumm, Konrad Möller, Peter Zipf:
Reconfigurable Convolutional Kernels for Neural Networks on FPGAs. FPGA 2019: 43-52 - [c75]Patrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf:
Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. ReConFig 2019: 1-8 - [i5]Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong:
Unrolling Ternary Neural Networks. CoRR abs/1909.04509 (2019) - [i4]Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong:
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. CoRR abs/1911.08097 (2019) - [i3]Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers:
Efficient Error-Tolerant Quantized Neural Network Accelerators. CoRR abs/1912.07394 (2019) - 2018
- [j12]Konrad Möller, Martin Kumm, Mario Garrido, Peter Zipf:
Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 710-714 (2018) - [j11]Martin Kumm, Oscar Gustafsson, Mario Garrido, Peter Zipf:
Optimal Single Constant Multiplication Using Ternary Adders. IEEE Trans. Circuits Syst. II Express Briefs 65-II(7): 928-932 (2018) - [c74]Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, Peter Zipf:
Karatsuba with Rectangular Multipliers for FPGAs. ARITH 2018: 13-20 - [c73]Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch:
ILP-Based Modulo Scheduling and Binding for Register Minimization. FPL 2018: 265-271 - [c72]Martin Hardieck, Martin Kumm, Patrick Sittel, Peter Zipf:
Constant Matrix Multiplication with Ternary Adders. ICECS 2018: 85-88 - [c71]Patrick Sittel, Thomas Schönwälder, Martin Kumm, Peter Zipf:
ScaLP: A Light-Weighted (MI)LP-Library. MBMV 2018 - 2017
- [j10]Martin Kumm, Martin Hardieck, Peter Zipf:
Optimization of Constant Matrix Multiplication with Low Power and High Throughput. IEEE Trans. Computers 66(12): 2072-2080 (2017) - [j9]Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf:
Reconfigurable Constant Multiplication for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 927-937 (2017) - [c70]Martin Kumm, Johannes Kappauf, Matei Istoan, Peter Zipf:
Resource Optimal Design of Large Multipliers for FPGAs. ARITH 2017: 131-138 - [c69]Patrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca, Mark Jervis:
Model-based hardware design based on compatible sets of isomorphic subgraphs. FPT 2017: 199-202 - [c68]Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf:
High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. MBMV 2017: 103-114 - 2016
- [j8]Martin Kumm, Peter Zipf:
Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs". Int. J. Reconfigurable Comput. 2016: 3015403:1-3015403:3 (2016) - [c67]Martin Kumm, Marco Kleinlein, Peter Zipf:
Efficient sum of absolute difference computation on FPGAs. FPL 2016: 1-4 - 2015
- [c66]Martin Kumm, Shahid Abbas, Peter Zipf:
An Efficient Softcore Multiplier Architecture for Xilinx FPGAs. ARITH 2015: 18-25 - [c65]Mathias Faust, Martin Kumm, Chip-Hong Chang, Peter Zipf:
Efficient structural adder pipelining in transposed form FIR filters. DSP 2015: 311-314 - [i2]Konrad Möller, Martin Kumm, Charles-Frederic Müller, Peter Zipf:
Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits. CoRR abs/1508.06811 (2015) - 2014
- [c64]Martin Kumm, Peter Zipf:
Pipelined compressor tree optimization using integer linear programming. FPL 2014: 1-8 - [c63]Michael Kunz, Alexander Ostrowski, Peter Zipf:
An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications. FPL 2014: 1-4 - [c62]Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf:
Pipelined reconfigurable multiplication with constants on FPGAs. FPL 2014: 1-6 - [c61]Konrad Möller, Martin Kumm, Björn Barschtipan, Peter Zipf:
Dynamically Reconfigurable Constant Multiplication on FPGAs. MBMV 2014: 159-169 - [c60]Martin Kumm, Peter Zipf:
Efficient High Speed Compression Trees on Xilinx FPGAs. MBMV 2014: 171-182 - 2013
- [j7]Martin Kumm, Diana Fanghänel, Konrad Möller, Peter Zipf, Uwe Meyer-Baese:
FIR filter optimization for video processing on FPGAs. EURASIP J. Adv. Signal Process. 2013: 111 (2013) - [c59]Martin Kumm, Martin Hardieck, Jens Willkomm, Peter Zipf, Uwe Meyer-Baese:
Multiple constant multiplication with ternary adders. FPL 2013: 1-8 - [c58]Martin Kumm, Konrad Möller, Peter Zipf:
Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs. ISCAS 2013: 2054-2057 - [c57]Martin Kumm, Konrad Möller, Peter Zipf:
Reconfigurable FIR filter using distributed arithmetic on FPGAs. ISCAS 2013: 2058-2061 - [c56]Martin Kumm, Konrad Möller, Peter Zipf:
Dynamically reconfigurable FIR filter architectures with fast reconfiguration. ReCoSoC 2013: 1-8 - 2012
- [c55]Martin Kumm, Katharina Liebisch, Peter Zipf:
Reduced complexity single and multiple constant multiplication in floating point precision. FPL 2012: 255-261 - [c54]Michael Kunz, Martin Kumm, Martin Heide, Peter Zipf:
Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system. FPL 2012: 591-594 - [c53]Martin Kumm, Peter Zipf:
Hybrid multiple constant multiplication for FPGAs. ICECS 2012: 556-559 - [c52]Martin Kumm, Peter Zipf, Mathias Faust, Chip-Hong Chang:
Pipelined adder graph optimization for high speed multiple constant multiplication. ISCAS 2012: 49-52 - 2011
- [c51]Martin Kumm, Peter Zipf:
High speed low complexity FPGA-based FIR filters using pipelined adder graphs. FPT 2011: 1-4 - 2010
- [j6]Martin Kumm, Harald Klingbeil, Peter Zipf:
An FPGA-Based Linear All-Digital Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(9): 2487-2497 (2010) - [p1]Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
Dynamically Reconfigurable Systems for Wireless Sensor Networks. Dynamically Reconfigurable Systems 2010: 315-334
2000 – 2009
- 2009
- [j5]Peter Zipf, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, Manfred Glesner:
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips. Int. J. Reconfigurable Comput. 2009: 453970:1-453970:14 (2009) - [j4]Michael Hübner, Juan Manuel Moreno, Gilles Sassatelli, Peter Zipf:
Selected Papers from ReCoSoC 2008. Int. J. Reconfigurable Comput. 2009: 894059:1-894059:2 (2009) - [j3]Heiko Hinkelmann, Peter Zipf, Jia Li, Guifang Liu, Manfred Glesner:
On the design of reconfigurable multipliers for integer and Galois field multiplication. Microprocess. Microsystems 33(1): 2-12 (2009) - [c50]Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. FPL 2009: 92-98 - [c49]Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes. FPL 2009: 359-366 - [c48]Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf:
Towards a unique FPGA-based identification circuit using process variations. FPL 2009: 397-402 - [c47]Thomas C. P. Chau, S. Man Ho Ho, Philip Heng Wai Leong, Peter Zipf, Manfred Glesner:
Generation of Synthetic Floating-Point benchmark circuits. IPDPS 2009: 1-9 - 2008
- [j2]Peter Zipf:
Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays. IEEE Trans. Very Large Scale Integr. Syst. 16(2): 134-143 (2008) - [c46]Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
Coarse-grained reconfiguration. FPL 2008: 349 - [c45]Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll:
Application-specific reconfigurable processors. FPL 2008: 350 - [c44]Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
A scalable reconfiguration mechanism for fast dynamic reconfiguration. FPT 2008: 145-152 - [c43]Peter Zipf, Heiko Hinkelmann, Hui Shao, Radu Dogaru, Manfred Glesner:
An area-efficient FPGA realisation of a codebook-based image compression method. FPT 2008: 349-352 - [c42]Christopher Spies, Peter Zipf, Manfred Glesner, Harald Klingbeil:
Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II. IEEE International Workshop on Rapid System Prototyping 2008: 196-202 - 2007
- [j1]Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck:
Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). it Inf. Technol. 49(3): 174- (2007) - [c41]Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll:
A Power Estimation Model for an FPGA-based Softcore Processor. FPL 2007: 171-176 - [c40]Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks. FPT 2007: 313-316 - [c39]Peter Zipf, Yang Qiao, Manfred Glesner:
Ein Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer Hardwarestrukturen. MBMV 2007: 253-262 - [c38]Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner:
A Customizable LEON2-Based VLIW Processor. ReCoSoC 2007: 55-60 - [c37]Heiko Hinkelmann, Tudor Murgan, Guifang Liu, Peter Zipf, Manfred Glesner:
On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. ReCoSoC 2007: 185-191 - 2006
- [c36]Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
Design Concepts for a Dynamically ReconfigurableWireless Sensor Node. AHS 2006: 436-441 - [c35]Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner:
Implementation of Realtime and Highspeed Phase Detector on FPGA. ARC 2006: 1-11 - [c34]Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
A metric for the energy-efficiency of dynamically reconfigurable systems. ARCS Workshops 2006: 152-161 - [c33]Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred Glesner:
A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits. DATE 2006: 632-637 - [c32]Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner:
Multitasking Support for Dynamically Reconfig Urable Systems. FPL 2006: 1-6 - [c31]Peter Zipf, Volker Hampel, Manfred Glesner, Thilo Pionteck:
Eine Scheduling Heuristik zur Minimierung der Verlustleistung. MBMV 2006: 51-60 - [c30]Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
A Concept for a Profile-based Dynamic Reconfiguration Mechanism. ReCoSoC 2006: 105-110 - [i1]Peter Zipf, Manfred Glesner:
Towards an Automated Design of Application-specific Reconfigurable Logic. Dynamically Reconfigurable Architectures 2006 - 2005
- [c29]Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, Antonio Rubio:
CONAN - A Design Exploration Framework for Reliable Nano-Electronics. ASAP 2005: 260-267 - [c28]Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner:
Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata. FPL 2005: 329-334 - [c27]Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner:
A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata. FPL 2005: 335-340 - [c26]Peter Zipf, Oliver Soffke, Michael Velten, Manfred Glesner:
Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC. GI Jahrestagung (1) 2005: 329-333 - [c25]Clemens Schlachta, Oliver Soffke, Peter Zipf, Manfred Glesner:
Eine weiterentwickelte quasi-statische adiabatische Logikfamilie. GI Jahrestagung (1) 2005: 448 - [c24]A. Petrov, Tudor Murgan, Peter Zipf, Manfred Glesner:
Functional modeling techniques for a wireless LAN OFDM transceiver. ISCAS (4) 2005: 3970-3973 - [c23]Peter Zipf, Claude Stötzler, Manfred Glesner:
Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model. ReCoSoC 2005: 53-58 - [c22]Tudor Murgan, Abdulfattah Mohammad Obeid, Andre Guntoro, Peter Zipf, Manfred Glesner, Ulrich Heinkel:
Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks. ReCoSoC 2005: 151-156 - [c21]Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf:
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. SAMOS 2005: 12-21 - 2004
- [c20]Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan:
Reconfigurable platforms for ubiquitous computing. Conf. Computing Frontiers 2004: 377-389 - [c19]Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner:
Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. Conf. Computing Frontiers 2004: 404-418 - [c18]Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong-Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong:
IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. FPL 2004: 526-535 - [c17]Mihail Petrov, Tudor Murgan, Frank May, Martin Vorbach, Peter Zipf, Manfred Glesner:
The XPP Architecture and Its Co-simulation Within the Simulink Environment. FPL 2004: 761-770 - [c16]Mihail Petrov, Tudor Murgan, Abdulfattah Mohammad Obeid, Cristian Chitu, Peter Zipf, Jörg Brakensiek, Manfred Glesner:
Dynamic power optimization of the trace-back process for the Viterbi algorithm. ISCAS (2) 2004: 721-724 - [c15]Peter Zipf, Claude Stötzler, Manfred Glesner:
A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. ISVLSI 2004: 266-267 - [c14]Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel:
Flexible Overhead Processing Architectures for G.709 Optical Transport Networks. MBMV 2004: 156-164 - [c13]Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Thomas Hollstein, Manfred Glesner:
An Asynchronous Switch Implmentation for Systems-on-a-Chip. MBMV 2004: 224-231 - [c12]Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner:
A switch architecture and signal synchronization for GALS system-on-chips. SBCCI 2004: 210-215 - 2003
- [c11]Stephan Bingemer, Peter Zipf, Manfred Glesner:
A granularity-based classification model for systems-on-a-chip. FPGA 2003: 239 - [c10]Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek:
Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. FPL 2003: 1111-1114 - [c9]Chun Hok Ho, Kuen Hung Tsoi, Jackson H. C. Yeung, Yuet Ming Lam, Kin-Hong Lee, Philip Heng Wai Leong, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner:
Arbitrary function approximation in HDLs with application to the N-body problem. FPT 2003: 84-91 - [c8]Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner:
A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. VLSI-SOC 2003: 44-49 - [c7]Mihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner:
An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. VLSI-SOC 2003: 167- - [c6]Stephan Bingemer, Peter Zipf, Manfred Glesner:
An Integrated Model Bridging the Gap between Technology and Economy. VLSI-SOC 2003: 442- - [e2]Manfred Glesner, Ricardo Augusto da Luz Reis, Hans Eveking, Vincent John Mooney III, Leandro Soares Indrusiak, Peter Zipf:
IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003. Technische Universität Darmstadt, Insitute of Microelectronic Systems 2003, ISBN 3-901882-17-0 [contents] - 2002
- [c5]Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner:
Fly - A Modifiable Hardware Compiler. FPL 2002: 381-390 - [c4]Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner:
A Framework for Teaching (Re)Configurable Architectures in Student Projects. FPL 2002: 444-451 - [c3]Peter Zipf, Manfred Glesner, Christine Bauer, Hans Wojtkowiak:
Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension. FPL 2002: 586-595 - [e1]Manfred Glesner, Peter Zipf, Michel Renovell:
Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings. Lecture Notes in Computer Science 2438, Springer 2002, ISBN 3-540-44108-5 [contents] - 2000
- [c2]Christine Bauer, Peter Zipf, Hans Wojtkowiak:
System Design with Genetic Algorithms. FPL 2000: 250-259 - [c1]Christine Bauer, Peter Zipf, Hans Wojtkowiak:
Integration und Fehlertoleranz im Codesign. MBMV 2000: 250-258
Coauthor Index
[p1] [j5] [j3] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [j1] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [i1] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [e2] [c5] [c4] [c3] [e1]