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2020 – today
- 2024
[j67]Janusz Rajski
, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer:
The Future of Design for Test and Silicon Lifecycle Management. IEEE Des. Test 41(4): 35-49 (2024)- [j66]Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
H2B: Crypto Hash Functions Based on Hybrid Ring Generators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 442-455 (2024) - 2023
- [j65]Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
A Lightweight True Random Number Generator for Root of Trust Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2815-2825 (2023) - [j64]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak:
X-Masking for Deterministic In-System Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4260-4269 (2023) - [j63]Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer:
A New Static Compaction of Deterministic Test Sets. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 411-420 (2023) - [c87]Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
Hybrid Ring Generators for In-System Test Applications. ETS 2023: 1-6 - 2022
- [j62]Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer:
LBIST for Automotive ICs With Enhanced Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2290-2300 (2022) - [c86]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak:
X-Masking for In-System Deterministic Test. ETS 2022: 1-6 - [c85]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak:
DIST: Deterministic In-System Test with X-masking. ITC 2022: 20-27 - [c84]Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
Hardware Root of Trust for SSN-basedDFT Ecosystems. ITC 2022: 479-483 - 2021
- [j61]Wu-Tung Cheng, Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer:
Autonomous Scan Patterns for Laser Voltage Imaging. IEEE Trans. Emerg. Top. Comput. 9(2): 680-691 (2021) - [j60]Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Time and Area Optimized Testing of Automotive ICs. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 76-88 (2021) - [j59]Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak:
X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan. IEEE Trans. Very Large Scale Integr. Syst. 29(8): 1553-1566 (2021) - [c83]Bartosz Grzelak, Martin Keim, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Convolutional Compaction-Based MRAM Fault Diagnosis. ETS 2021: 1-6 - [c82]Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer:
On Reduction of Deterministic Test Pattern Sets. ITC 2021: 260-267 - 2020
- [j58]Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer:
Scan Integrity Tests for EDT Compression. IEEE Des. Test 37(4): 21-26 (2020) - [j57]Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer:
Deterministic Stellar BIST for Automotive ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1699-1710 (2020) - [j56]Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang:
Low Cost Hypercompression of Test Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2964-2975 (2020) - [c81]Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer:
Test Sequence-Optimized BIST for Automotive Applications. ETS 2020: 1-6 - [c80]Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wldarczak:
X-Tolerant Tunable Compactor for In-System Test. ITC 2020: 1-10
2010 – 2019
- 2019
- [j55]Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada:
Logic BIST With Capture-Per-Clock Hybrid Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1028-1041 (2019) - [c79]Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki:
Test Time and Area Optimized BrST Scheme for Automotive ICs. ITC 2019: 1-10 - [c78]Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer:
On Cyclic Scan Integrity Tests for EDT-based Compression. VTS 2019: 1-6 - 2018
- [j54]Michael Chen, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
Hardware Protection via Logic Locking Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3020-3030 (2018) - [c77]Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang:
Hypercompression of Test Patterns. ITC 2018: 1-9 - [c76]Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer:
Deterministic Stellar BIST for In-System Automotive Test. ITC 2018: 1-9 - [c75]Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
On New Class of Test Points and Their Applications. ITC 2018: 1-9 - [c74]Yingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jedrzej Solecki, Jerzy Tyszer:
Staggered ATPG with capture-per-cycle observation test points. VTS 2018: 1-6 - 2017
- [j53]Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer:
Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(4): 683-693 (2017) - [j52]Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang:
Trimodal Scan-Based Test Paradigm. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1112-1125 (2017) - [j51]Cesar Acero, Derek Feltham, Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Justyna Zawada:
Embedded Deterministic Test Points. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2949-2961 (2017) - [c73]Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
ROM fault diagnosis for O(n2) test algorithms. ETS 2017: 1-6 - [c72]Sylwester Milewski, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada:
Full-scan LBIST with capture-per-cycle hybrid test points. ITC 2017: 1-9 - 2016
- [j50]Cesar Acero, Derek Feltham, Marek Patyra, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
On New Test Points for Compact Cell-Aware Tests. IEEE Des. Test 33(6): 7-14 (2016) - [c71]Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
On Test Points Enhancing Hardware Security. ATS 2016: 61-66 - [c70]Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer:
Minimal area test points for deterministic patterns. ITC 2016: 1-7 - [c69]Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
Test point insertion in hybrid test compression/LBIST architectures. ITC 2016: 1-10 - 2015
- [j49]Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1847-1859 (2015) - [j48]Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1050-1062 (2015) - [j47]Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Low-Power Programmable PRPG With Test Compression Capabilities. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1063-1076 (2015) - [c68]Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang:
TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm. ATS 2015: 19-24 - [c67]Haluk Konuk, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Deepak Solanki, Jerzy Tyszer, Justyna Zawada:
Design for low test pattern counts. DAC 2015: 136:1-136:6 - [c66]Cesar Acero, Derek Feltham, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Marek Patyra, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
Embedded deterministic test points for compact cell-aware tests. ITC 2015: 1-8 - [c65]Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer:
A deterministic BIST scheme based on EDT-compressed test patterns. ITC 2015: 1-8 - 2014
- [j46]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 167 (2014) - [c64]Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer:
High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. ATS 2014: 74-80 - [c63]Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Test Compression with Programmable Broadcast-Based Control. ATS 2014: 174-179 - [c62]Marcin Gebala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
On Using Implied Values in EDT-based Test Compression. DAC 2014: 11:1-11:6 - [c61]Albert Au, Artur Pogiel, Janusz Rajski, Piotr Sydow, Jerzy Tyszer, Justyna Zawada:
Quality assurance in memory built-in self-test tools. DDECS 2014: 39-44 - [c60]Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric test compression with low toggling activity. ITC 2014: 1-7 - 2013
- [j45]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
On Deploying Scan Chains for Data Storage in Test Compression Environment. IEEE Des. Test 30(1): 68-76 (2013) - [j44]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1776-1786 (2013) - [c59]Jerzy Tyszer, Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski:
New test compression scheme based on low power BIST. ETS 2013: 1-6 - [c58]Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles:
EDT bandwidth management - Practical scenarios for large SoC designs. ITC 2013: 1-10 - [c57]Janusz Rajski, Jerzy Tyszer:
Fault diagnosis of TSV-based interconnects in 3-D stacked designs. ITC 2013: 1-9 - 2012
- [j43]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
EDT Bandwidth Management in SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1894-1907 (2012) - [c56]Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski:
Bandwidth-aware test compression logic for SoC designs. ETS 2012: 1-6 - [c55]Dariusz Czysz, Janusz Rajski, Jerzy Tyszer:
Low power test application with selective compaction in VLSI designs. ITC 2012: 1-10 - [c54]Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski:
Low power programmable PRPG with enhanced fault coverage gradient. ITC 2012: 1-9 - [c53]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie:
Test generator with preselected toggling for low power built-in self-test. VTS 2012: 1-6 - 2011
- [j42]Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer:
Ring Generator: An Ultimate Linear Feedback Shift Register. Computer 44(6): 64-71 (2011) - [j41]Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs. J. Electron. Test. 27(5): 599-609 (2011) - [j40]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
BIST-Based Fault Diagnosis for Read-Only Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(7): 1072-1085 (2011) - [j39]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer:
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1225-1238 (2011) - [c52]Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer:
Low Power Decompressor and PRPG with Constant Value Broadcast. Asian Test Symposium 2011: 84-89 - [c51]Grzegorz Mrugalski, Artur Pogiel, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Pawel Urbanek:
Fault Diagnosis in Memory BIST Environment with Non-march Tests. Asian Test Symposium 2011: 419-424 - [c50]Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer:
Power Aware Embedded Test. Asian Test Symposium 2011: 511-516 - [c49]Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. ETS 2011: 1-6 - [c48]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Reduced ATE Interface for High Test Data Compression. ETS 2011: 99-104 - [c47]Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski:
EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC 2011: 1-9 - 2010
- [j38]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
On Compaction Utilizing Inter and Intra-Correlation of Unknown States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 117-126 (2010) - [j37]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
High Volume Diagnosis in Memory BIST Based on Compressed Failure Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 441-453 (2010) - [c46]Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Diagnosis of failing scan cells through orthogonal response compaction. ETS 2010: 221-226 - [c45]Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer:
Dynamic channel allocation for higher EDT compression in SoC designs. ITC 2010: 265-274 - [c44]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer:
Low power compression of incompatible test cubes. ITC 2010: 704-713
2000 – 2009
- 2009
- [j36]Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low-Power Scan Operation in Test Compression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1742-1755 (2009) - [c43]Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer:
Compression based on deterministic vector clustering of incompatible test cubes. ITC 2009: 1-10 - [c42]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Fault diagnosis for embedded read-only memories. ITC 2009: 1-10 - [c41]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Defect Aware to Power Conscious Tests - The New DFT Landscape. VLSI Design 2009: 23-25 - [c40]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
High-Speed On-Chip Event Counters for Embedded Systems. VLSI Design 2009: 275-280 - [c39]Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer:
Highly X-Tolerant Selective Compaction of Test Responses. VTS 2009: 245-250 - 2008
- [j35]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab:
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 147-159 (2008) - [j34]Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1278-1290 (2008) - [c38]Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Scan Shift and Capture in the EDT Environment. ITC 2008: 1-10 - [c37]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. ITC 2008: 1-10 - 2007
- [j33]Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai:
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Des. Test Comput. 24(5): 476-485 (2007) - [j32]Grzegorz Mrugalski, Janusz Rajski, Chen Wang, Artur Pogiel, Jerzy Tyszer:
Isolation of Failing Scan Cells through Convolutional Test Response Compaction. J. Electron. Test. 23(1): 35-45 (2007) - [j31]Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Fault Diagnosis With Convolutional Compactors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1478-1494 (2007) - [c36]Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer:
New Test Data Decompressor for Low Power Applications. DAC 2007: 539-544 - [c35]Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Embedded Deterministic Test. VTS 2007: 75-83 - 2006
- [j30]Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
High Performance Dense Ring Generators. IEEE Trans. Computers 55(1): 83-87 (2006) - [c34]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Test response compactor with programmable selector. DAC 2006: 1089-1094 - [c33]Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Convolutional Compactors with Variable Polynomials. ETS 2006: 117-122 - [c32]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab:
X-Press Compactor for 1000x Reduction of Test Data. ITC 2006: 1-10 - 2005
- [j29]Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy:
Finite memory test response compactors for embedded test applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 622-634 (2005) - [c31]Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer, Chen Wang:
Convolutional compaction-driven diagnosis of scan failures. ETS 2005: 176-181 - [c30]Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Diagnosis with convolutional compactors in presence of unknown states. ITC 2005: 10 - [c29]Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz:
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. VLSI Design 2005: 59-64 - [c28]Janusz Rajski, Jerzy Tyszer:
Synthesis of X-Tolerant Convolutional Compactors. VTS 2005: 114-119 - 2004
- [j28]Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee:
Embedded deterministic test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 776-792 (2004) - [j27]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Ring generators - new devices for embedded test applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9): 1306-1320 (2004) - [c27]Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski:
Fault Diagnosis in Designs with Convolutional Compactors. ITC 2004: 498-507 - [c26]Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht:
Embedded Test for Low Cost Manufacturing. VLSI Design 2004: 21-23 - [c25]Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Planar High Performance Ring Generators. VTS 2004: 193-198 - 2003
- [j26]Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski:
2D Test Sequence Generators. IEEE Des. Test Comput. 20(1): 51-59 (2003) - [j25]Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Des. Test Comput. 20(5): 58-66 (2003) - [j24]Janusz Rajski, Jerzy Tyszer:
Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients. J. Electron. Test. 19(6): 645-657 (2003) - [c24]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer:
On Compacting Test Response Data Containing Unknown Values. ICCAD 2003: 855-862 - [c23]Janusz Rajski, Jerzy Tyszer:
Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. ICCD 2003: 331- - [c22]Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy:
Convolutional Compaction of Test Responses. ITC 2003: 745-754 - [c21]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
High Speed Ring Generators and Compactors of Test Data. VTS 2003: 57-62 - 2002
- [c20]Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC 2002: 301-310 - 2001
- [j23]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Testing Schemes for FIR Filter Structures. IEEE Trans. Computers 50(7): 674-688 (2001) - 2000
- [j22]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Cellular automata-based test pattern generators with phase shifters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 878-893 (2000) - [j21]Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer:
Automated synthesis of phase shifters for built-in self-testapplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10): 1175-1188 (2000) - [c19]Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski:
Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. VTS 2000: 377-388
1990 – 1999
- 1999
- [j20]Janusz Rajski, Jerzy Tyszer:
Testing of telecommunications hardware [Guest Editorial]. IEEE Commun. Mag. 37(6): 60-62 (1999) - [j19]Janusz Rajski, Jerzy Tyszer:
Diagnosis of Scan Cells in BIST Environment. IEEE Trans. Computers 48(7): 724-731 (1999) - [c18]Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski:
Synthesis of pattern generators based on cellular automata with phase shifters. ITC 1999: 368-377 - [c17]Janusz Rajski, Jerzy Tyszer, Sanjay Patel:
Built-In Self-Test for Systems on Silicon. VLSI Design 1999: 609-610 - [c16]Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer:
Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. VTS 1999: 236-245 - 1998
- [j18]Janusz Rajski, Jerzy Tyszer, Nadime Zacharia:
Test Data Decompression for Multiple Scan Designs with Boundary Scan. IEEE Trans. Computers 47(11): 1188-1200 (1998) - [c15]Janusz Rajski, Jerzy Tyszer:
Modular logic built-in self-test for IP cores. ITC 1998: 313-321 - [c14]Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer:
Automated synthesis of large phase shifters for built-in self-test. ITC 1998: 1047-1056 - [c13]Janusz Rajski, Jerzy Tyszer:
Design of Phase Shifters for BIST Applications. VTS 1998: 218-224 - 1997
- [j17]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Design of Testable Multipliers for Fixed-Width Data Paths. IEEE Trans. Computers 46(7): 795-810 (1997) - [j16]Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer:
Arithmetic built-in self-test for DSP cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1358-1369 (1997) - [c12]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Parameterizable Testing Scheme for FIR Filters. ITC 1997: 694-703 - [c11]Janusz Rajski, Jerzy Tyszer:
Fault Diagnosis in Scan-Based BIST. ITC 1997: 894-902 - 1996
- [j15]Andrzej Jajszczyk, Jerzy Tyszer:
Broadband Time-Division Circuit Switching. IEEE J. Sel. Areas Commun. 14(2): 337-345 (1996) - [j14]Sanjay Gupta, Janusz Rajski, Jerzy Tyszer:
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns. IEEE Trans. Computers 45(8): 939-949 (1996) - [j13]Janusz Rajski, Jerzy Tyszer:
On Linear Dependencies in Subspaces of LFSR-Generated Sequences. IEEE Trans. Computers 45(10): 1212-1216 (1996) - [c10]Janusz Rajski, Jerzy Tyszer:
Multiplicative Window Generators of Pseudo-random Test Vectors. ED&TC 1996: 42-49 - [c9]Nadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski:
Two-Dimensional Test Data Decompressor for Multiple Scan Designs. ITC 1996: 186-194 - 1995
- [c8]Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC 1995: 333-338 - [c7]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
On testable multipliers for fixed-width data path architectures. ICCAD 1995: 541-547 - [c6]Mark Kassab, Janusz Rajski, Jerzy Tyszer:
Hierarchical Functional-Fault Simulation for High-Level Synthesis. ITC 1995: 596-605 - [c5]Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer:
Arithmetic built-in self test for high-level synthesis. VTS 1995: 132-139 - [c4]Nadime Zacharia, Janusz Rajski, Jerzy Tyszer:
Decompression of test data using variable-length seed LFSRs. VTS 1995: 426-433 - 1994
- [c3]Sanjay Gupta, Janusz Rajski, Jerzy Tyszer:
Test pattern generation based on arithmetic operations. ICCAD 1994: 117-124 - 1993
- [j12]Janusz Rajski, Jerzy Tyszer:
Accumulator-Based Compaction of Test Responses. IEEE Trans. Computers 42(6): 643-650 (1993) - [j11]Janusz Rajski, Jerzy Tyszer:
Recursive Pseudoexhaustive Test Pattern Generation. IEEE Trans. Computers 42(12): 1517-1521 (1993) - [j10]Janusz Rajski, Jerzy Tyszer:
Test responses compaction in accumulators with rotate carry adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4): 531-539 (1993) - 1992
- [j9]Jerzy Tyszer:
Testing of three-stage switching networks for coupling faults. IEEE Trans. Commun. 40(2): 413-422 (1992) - 1991
- [j8]Janusz Rajski, Jerzy Tyszer:
On the diagnostic properties of linear feedback shift registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(10): 1316-1322 (1991) - [j7]Jerzy Tyszer:
Test generation for pattern-sensitive faults in integrated switches. IEEE Trans. Commun. 39(11): 1546-1548 (1991) - 1990
- [j6]Jerzy Tyszer:
Interference faults testing for time switches. IEEE Trans. Commun. 38(7): 954-958 (1990) - [c2]Janusz Rajski, Jerzy Tyszer, Babak Salimi:
On the Diagnostic Resolution of Signature Analysis. ICCAD 1990: 364-367
1980 – 1989
- 1989
- [j5]Andrzej Jajszczyk, Jerzy Tyszer:
Fault diagnosis of digital switching networks. IEEE Trans. Commun. 37(7): 732-739 (1989) - 1988
- [j4]Jerzy Tyszer:
Multiple fault diagnosis for interconnection networks for distributed systems. Microprocess. Microprogramming 24(1-5): 731-734 (1988) - [j3]Jerzy Tyszer:
A Multiple Fault-Tolerant Processor Network Architecture for Pipeline Computing. IEEE Trans. Computers 37(11): 1414-1418 (1988) - 1986
- [j2]Janusz Rajski, Jerzy Tyszer:
The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's. IEEE Trans. Computers 35(1): 81-85 (1986) - 1985
- [j1]Janusz Rajski, Jerzy Tyszer:
Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays. IEEE Trans. Computers 34(6): 549-553 (1985) - 1984
- [c1]Janusz Rajski, Jerzy Tyszer:
The detection of small size multiple faults by single fault test sets n programmable logic arrays. Fehlertolerierende Rechensysteme 1984: 417-425
Coauthor Index
[j64] [j62] [c86] [c85] [j61] [j59] [j58] [c81] [c80] [c78] [j53] [j52] [j48] [j47] [c68] [c65] [j46] [c64] [c63] [c62] [j45] [j44] [c59] [j43] [c56] [c54] [c53] [j42] [j41] [j39] [c52] [c51] [c49] [c48] [c47] [j38] [c46] [c45] [c44] [j36] [c43] [c39] [j35] [j34] [c38] [j33] [j32] [j31] [c36] [c35] [j30] [c34] [c32] [c31] [c30] [j27] [c27] [c25] [j26] [c21] [c20] [j22] [c19] [c18] [c16]
[j67] [j62] [j60] [j59] [j57] [c81] [c80] [j55] [c79] [j54] [c76] [j51] [c72] [j50] [c71] [c70] [c69] [j49] [j48] [j47] [c67] [c66] [j46] [c64] [c62] [c60] [j45] [j44] [c59] [c58] [j43] [c54] [j42] [j40] [j39] [c51] [c50] [c48] [c47] [j38] [j37] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [j35] [c37] [j33] [j30] [c32] [j28] [c26] [c25] [j25] [c20] [j23] [j17] [c12] [c8] [c7] [c5]
[j67] [j66] [j65] [j64] [j63] [c87] [j62] [c86] [c85] [c84] [j61] [j60] [j59] [c83] [c82] [j58] [j57] [j56] [c81] [c80] [j55] [c79] [c78] [j54] [c77] [c76] [c75] [c74] [j53] [j52] [j51] [c73] [c72] [j50] [c71] [c70] [c69] [j49] [j48] [j47] [c68] [c67] [c66] [c65] [j46] [c64] [c63] [c62] [c61] [c60] [j45] [j44] [c59] [c58] [c57] [j43] [c56] [c55] [c54] [c53] [j42] [j41] [j40] [j39] [c52] [c51] [c50] [c49] [c48] [c47] [j38] [j37] [c46] [c45] [c44] [j36] [c43] [c42] [c41] [c40] [c39] [j35] [j34] [c38] [c37] [j33] [j32] [j31] [c36] [c35] [j30] [c34] [c33] [c32] [j29] [c31] [c30] [c29] [c28] [j28] [j27] [c27] [c26] [c25] [j26] [j25] [j24] [c24] [c23] [c22] [c21] [c20] [j23] [j22] [j21] [c19] [j20] [j19] [c18] [c17] [c16] [j18] [c15] [c14] [c13] [j17] [j16] [c12] [c11] [j14] [j13] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [j12] [j11] [j10] [j8] [c2] [j2] [j1] [c1]
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