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"Area-efficient design of three- and four-stage voltage multipliers for ..."

Giuseppe Di Cataldo, Gaetano Palumbo (1996)

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DOI: 10.1002/(SICI)1097-007X(199609/10)24:5<541::AID-CTA935>3.0.CO;2-L

access: closed

type: Journal Article

metadata version: 2020-05-11

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  - journals/ijcta/CataldoP96
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  - https://dblp.org/rec/journals/ijcta/CataldoP96
Giuseppe Di Cataldo, Gaetano Palumbo:
Area-efficient design of three- and four-stage voltage multipliers for power integrated circuits. Int. J. Circuit Theory Appl. 24(5): 541-550 (1996)

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