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"A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, ..."

Marco Zanuso et al. (2010)

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DOI: 10.1109/ISSCC.2010.5433842

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-27

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Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation. ISSCC 2010: 476-477

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