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2020 – today
- 2024
[j5]Guodong Yin
, Yiming Chen, Mufeng Zhou, Wenjun Tang, Mingyen Lee, Zekun Yang, Tianyu Liao, Xirui Du, Vijaykrishnan Narayanan, Huazhong Yang, Hongyang Jia, Yongpan Liu, Xueqing Li:
Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm2 Density in 65-nm CMOS. IEEE J. Solid State Circuits 59(6): 1912-1925 (2024)- [j4]Yiming Chen, Mingyen Lee, Guohao Dai, Mufeng Zhou, Nagadastagiri Challapalle, Tianyi Wang, Yao Yu, Yongpan Liu, Yu Wang, Huazhong Yang, Vijaykrishnan Narayanan, Xueqing Li:
GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility. IEEE Trans. Emerg. Top. Comput. 12(1): 84-96 (2024) - [c6]Yiming Chen, Guodong Yin, Hongtao Zhong, Mingyen Lee, Huazhong Yang, Sumitha George, Vijaykrishnan Narayanan, Xueqing Li:
ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns. ASPDAC 2024: 153-158 - [c5]Guodong Yin, Yiming Chen, Mingyen Lee, Xirui Du, Yue Ke, Wenjun Tang, Zhonghao Chen, Mufeng Zhou, Jinshan Yue, Huazhong Yang, Hongyang Jia, Yongpan Liu, Xueqing Li:
A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM. CICC 2024: 1-2 - 2023
- [j3]Wenjun Tang, Mingyen Lee, Juejian Wu, Yixin Xu, Yao Yu, Yongpan Liu, Kai Ni, Yu Wang, Huazhong Yang, Vijaykrishnan Narayanan, Xueqing Li:
FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2398-2411 (2023) - [j2]Yiming Chen, Guodong Yin, Mufeng Zhou, Wenjun Tang, Zekun Yang, Mingyen Lee, Xirui Du, Jinshan Yue, Jiaxin Liu, Huazhong Yang, Yongpan Liu, Xueqing Li:
SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2762-2773 (2023) - [j1]Yiming Chen, Yushen Fu, Mingyen Lee, Sumitha George, Yongpan Liu, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li:
FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1605-1609 (2023) - [c4]Mingyen Lee, Wenjun Tang, Yiming Chen, Juejian Wu, Hongtao Zhong, Yixin Xu, Yongpan Liu, Huazhong Yang, Vijaykrishnan Narayanan, Xueqing Li:
Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM. DAC 2023: 1-6 - 2022
- [c3]Yiming Chen, Guodong Yin, Zhanhong Tan, Mingyen Lee, Zekun Yang, Yongpan Liu, Huazhong Yang, Kaisheng Ma, Xueqing Li:
YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip. DAC 2022: 1093-1098 - [c2]Yiming Chen, Guodong Yin, Mingyen Lee, Wenjun Tang, Zekun Yang, Yongpan Liu, Huazhong Yang, Xueqing Li:
Hidden-ROM: A Compute-in-ROM Architecture to Deploy Large-Scale Neural Networks on Chip with Flexible and Scalable Post-Fabrication Task Transfer Capability. ICCAD 2022: 45:1-45:9 - [i4]Yiming Chen, Yushen Fu, Mingyen Lee, Sumitha George, Yongpan Liu, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li:
FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications. CoRR abs/2205.11088 (2022) - [i3]Yiming Chen, Guodong Yin, Zhanhong Tan, Mingyen Lee, Zekun Yang, Yongpan Liu, Huazhong Yang, Kaisheng Ma, Xueqing Li:
YOLoC: DeploY Large-Scale Neural Network by ROM-based Computing-in-Memory using ResiduaL Branch on a Chip. CoRR abs/2206.00379 (2022) - [i2]Yiming Chen, Guohao Dai, Mufeng Zhou, Mingyen Lee, Nagadastagiri Challapalle, Guodong Yin, Zekun Yang, Yongpan Liu, Huazhong Yang, Vijaykrishnan Narayanan, Xueqing Li:
GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph. CoRR abs/2208.08600 (2022) - [i1]Guodong Yin, Mufeng Zhou, Yiming Chen, Wenjun Tang, Zekun Yang, Mingyen Lee, Xirui Du, Jinshan Yue, Jiaxin Liu, Huazhong Yang, Yongpan Liu, Xueqing Li:
A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface. CoRR abs/2212.04320 (2022) - 2020
- [c1]Mingyen Lee, Wenjun Tang, Bowen Xue, Juejian Wu, Mingyuan Ma, Yu Wang, Yongpan Liu, Deliang Fan, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li:
FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface. ISLPED 2020: 127-132
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