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ORCIDJaume Segura 0001
Jaume A. Segura 0001
Person information
- affiliation: University de les Illes Baleares, Electronic Systems Group, Palma de Mallorca, Spain
- affiliation (PhD 1992): Polytechnic University of Catalonia, Barcelona, Spain
Other persons with the same name
- Jaume Segura-Garcia
![[0000-0002-9138-5465]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-9138-5465")
(aka: Jaume Segura 0002) — University of Valencia, Department of Computer Science, Spain
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Journal Articles
- 2024
[j34]Rafel Perelló-Roig, Salvador Barceló, Jaume Verd, Sebastià A. Bota, Jaume Segura:
A 164-dBΩ Transimpedance Amplifier for Monolithic CMOS-MEMS Oscillators in Biosensing Applications. IEEE Access 12: 75061-75071 (2024)- [j33]Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas, Jaume Segura:
Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations. J. Electron. Test. 40(1): 75-86 (2024) - 2020
- [j32]Rafel Perelló-Roig, Jaume Verd, Sebastià A. Bota, Jaume Segura:
Impact of Fluid Flow on CMOS-MEMS Resonators Oriented to Gas Sensing. Sensors 20(17): 4663 (2020) - 2019
- [j31]Gabriel Torrens, Bartomeu Alorda, Cristian Carmona, Daniel Malagón-Periánez, Jaume Segura, Sebastià A. Bota:
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors. IEEE Trans. Emerg. Top. Comput. 7(3): 447-455 (2019) - 2018
- [j30]Rafel Perelló-Roig, Jaume Verd, Sebastià A. Bota, Jaume Segura:
Thermomechanical Noise Characterization in Fully Monolithic CMOS-MEMS Resonators. Sensors 18(9): 3124 (2018) - 2017
- [j29]Daniel Malagón, Sebastià A. Bota, Gabriel Torrens, Xavier Gili, Javier Praena, B. Fernández, Miguel Macías, José Manuel Quesada, Carlos Guerrero Sanchez, María del Carmen Jiménez-Ramos, Javier García López, José Luis Merino, Jaume Segura:
Soft error rate comparison of 6T and 8T SRAM ICs using mono-energetic proton and neutron irradiation sources. Microelectron. Reliab. 78: 38-45 (2017) - 2016
- [j28]Joan Barceló, José Luis Rosselló, Sebastià A. Bota, Jaume Segura, Jaume Verd:
Electrostatically actuated microbeam resonators as chaotic signal generators: A practical perspective. Commun. Nonlinear Sci. Numer. Simul. 30(Issues): 316-327 (2016) - [j27]Hector Villacorta, Jaume Segura, Víctor H. Champac:
Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability. J. Electron. Test. 32(3): 307-314 (2016) - 2015
- [j26]Hector Villacorta, Jose Luis Garcia-Gervacio, Jaume Segura, Víctor H. Champac:
Low VDD and body bias conditions for testing bridge defects in the presence of process variations. Microelectron. J. 46(5): 398-403 (2015) - 2014
- [j25]Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura:
Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells. Microelectron. Reliab. 54(11): 2613-2620 (2014) - [j24]Salvador Barceló, Xavier Gili, Sebastià A. Bota, Jaume Segura:
Sensitization Input Vector Impact on Propagation Delay for Nanometer CMOS ICs: Analysis and Solutions. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1557-1569 (2014) - 2013
- [j23]Hector Villacorta, Charles F. Hawkins, Víctor H. Champac, Jaume Segura, Roberto Gómez:
Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths. IEEE Des. Test 30(6): 70-79 (2013) - [j22]José Luis Merino, Sebastià Antoni Bota, Rodrigo Picos, Jaume Segura:
Alternate characterization technique for static random-access memory static noise margin determination. Int. J. Circuit Theory Appl. 41(10): 1085-1096 (2013) - 2012
- [j21]Víctor H. Champac, Julio Vazquez Hernandez, Salvador Barceló, Roberto Gómez, Chuck Hawkins, Jaume Segura:
Testing of Stuck-Open Faults in Nanometer Technologies. IEEE Des. Test Comput. 29(4): 80-91 (2012) - [j20]Hector Villacorta, Víctor H. Champac, Sebastià A. Bota, Jaume Segura:
Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test. Microelectron. Reliab. 52(11): 2799-2804 (2012) - 2011
- [j19]Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura:
8T vs. 6T SRAM cell radiation robustness: A comparative analysis. Microelectron. Reliab. 51(2): 350-359 (2011) - 2010
- [j18]Gabriel Torrens, Bartomeu Alorda, Salvador Barceló, José Luis Rosselló, Sebastià A. Bota, Jaume Segura:
Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination. IEEE Trans. Circuits Syst. II Express Briefs 57-II(4): 280-284 (2010) - 2007
- [j17]Bartomeu Alorda, Ivan de Paúl, Jaume Segura:
Charge-based testing BIST for embedded memories. IET Comput. Digit. Tech. 1(5): 481-490 (2007) - 2006
- [j16]Sebastià A. Bota, José Luis Rosselló, Carol de Benito, Ali Keshavarzi, Jaume Segura:
Impact of Thermal Gradients on Clock Skew and Testing. IEEE Des. Test Comput. 23(5): 414-424 (2006) - 2005
- [j15]José Luis Rosselló, Carol de Benito, Jaume Segura:
A compact gate-level energy and delay model of dynamic CMOS gates. IEEE Trans. Circuits Syst. II Express Briefs 52-II(10): 685-689 (2005) - 2004
- [j14]Bartomeu Alorda, Vincent Canals, Jaume Segura:
A Two-Level Power-Grid Model for Transient Current Testing Evaluation. J. Electron. Test. 20(5): 543-552 (2004) - [j13]José Luis Rosselló, Jaume A. Segura:
An analytical charge-based compact delay model for submicrometer CMOS inverters. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(7): 1301-1311 (2004) - 2003
- [j12]Josep Altet, Antonio J. Rubio, José Luis Rosselló, Jaume Segura:
Structural RFIC device testing through built-in thermal monitoring. IEEE Commun. Mag. 41(9): 98-104 (2003) - [j11]Joan Font, J. Ginard, Rodrigo Picos, Eugeni Isern, Jaume Segura, Miquel Roca, Eugenio García:
A BICS for CMOS OpAmps by Monitoring the Supply Current Peak. J. Electron. Test. 19(5): 597-603 (2003) - 2002
- [j10]Jaume Segura, Peter C. Maxwell:
Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era. IEEE Des. Test Comput. 19(5): 5-7 (2002) - [j9]José Luis Rosselló, Jaume Segura:
Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 433-448 (2002) - 2000
- [j8]Rodrigo Picos, Miquel Roca, Eugeni Isern, Jaume Segura, Eugenio García-Moreno:
Experimental Results on BIC Sensors for Transient Current Testing. J. Electron. Test. 16(3): 235-241 (2000) - 1999
- [j7]Charles F. Hawkins, Jaume Segura:
Test and Reliability: Partners in IC Manufacturing, Part 1. IEEE Des. Test Comput. 16(3): 64-71 (1999) - [j6]Charles F. Hawkins, Jaume Segura, Jerry M. Soden, Ted Dellin:
Test and Reliability: Partners in IC Manufacturing, Part 2. IEEE Des. Test Comput. 16(4): 66-73 (1999) - 1998
- [j5]Eugenio García-Moreno, Benjamín Iñíguez, Miquel Roca, Jaume Segura, Eugeni Isern:
Clocked Dosimeter Compatible with Digital CMOS Technology. J. Electron. Test. 12(1-2): 101-110 (1998) - [j4]Jaume Segura, José Luis Rosselló, J. Morra, H. Sigg:
A variable threshold voltage inverter for CMOS programmable logic circuits. IEEE J. Solid State Circuits 33(8): 1262-1265 (1998) - 1997
- [j3]Jaume Segura, Antonio Rubio:
A detailed analysis of CMOS SRAM's with gate oxide short defects. IEEE J. Solid State Circuits 32(10): 1543-1550 (1997) - 1996
- [j2]Jaume Segura, Carol de Benito, Antonio Rubio, Charles F. Hawkins:
A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors. J. Electron. Test. 8(3): 229-239 (1996) - 1992
- [j1]Jaume A. Segura, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio:
Quiescent current analysis and experimentation of defective CMOS circuits. J. Electron. Test. 3(4): 337-348 (1992)
Conference and Workshop Papers
- 2023
- [c58]Sebastià A. Bota, Salvador Barceló, Gabriel Torrens, Rafel Perelló, Jaume Verd, Ivan de Paúl, Jaume Segura:
A Compact Double-Exponential Circuit for Single Event Transient Emulation. DCIS 2023: 1-6 - 2022
- [c57]Rafel Perelló-Roig, Francisca Orvay, Ivan de Paúl, Jaume Verd, Sebastià A. Bota, Jaume Segura:
Fully Integrated Front-End CMOS-MEMS Transducer for Low-Cost Real-Time Breath Monitoring. IEEE SENSORS 2022: 1-4 - [c56]Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas, Jaume Segura:
Failure Probability due to Radiation-induced Effects in FinFET SRAM Cells under Process Variations. LATS 2022: 1-6 - 2018
- [c55]Joan Barceló, Ivan de Paúl, Sebastià A. Bota, Jaume Segura, Jaume Verd:
Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator. ISCAS 2018: 1-5 - [c54]Rafel Perelló-Roig, Jaume Verd, Sebastià A. Bota, Jaume Segura:
Frequency Fluctuations in CMOS-MEMS Oscillators: Towards the Thermomechanical Limit. ISCAS 2018: 1-5 - 2017
- [c53]Sebastià A. Bota, Jaume Verd, Joan Barceló, Xavier Gili, Bartomeu Alorda, Gabriel Torrens, Carol de Benito, Jaume Segura:
Cantilever NEMS relay-based SRAM devices for enhanced reliability. DTIS 2017: 1-6 - [c52]Jaume Segura:
Integrated microelectromechanical systems in the More than Moore era. DTIS 2017: 1 - [c51]Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Gabriel Torrens, Sebastià A. Bota, Jaume Segura, Francesc Moll, Antonio Rubio:
Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells. SMACD 2017: 1-4 - 2015
- [c50]Hector Villacorta, Roberto Gómez, Sebastià A. Bota, Jaume Segura, Víctor H. Champac:
Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell. LATS 2015: 1-6 - 2014
- [c49]Hector Villacorta, Jaume Segura, Sebastià A. Bota, Víctor H. Champac:
Analysis of fin height on FinFET SRAM cell hardening. MWSCAS 2014: 671-674 - 2013
- [c48]Hector Villacorta, Jose Luis Garcia-Gervacio, Víctor H. Champac, Sebastià A. Bota, Jaime Martínez-Castillo, Jaume Segura:
Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias. LATW 2013: 1-6 - 2011
- [c47]Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura:
Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation. DATE 2011: 986-991 - [c46]Salvador Barceló, Xavier Gili, Sebastià A. Bota, Jaume Segura:
An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation. DATE 2011: 1602-1607 - 2010
- [c45]Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura:
Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs. DATE 2010: 429-434 - [c44]Sebastià A. Bota, Gabriel Torrens, Bartomeu Alorda, Jaume Verd, Jaume Segura:
Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories. IOLTS 2010: 141-146 - [c43]Hector Villacorta, Víctor H. Champac, Chuck Hawkins, Jaume Segura:
Reliability analysis of small delay defects in vias located in signal paths. LATW 2010: 1-6 - 2009
- [c42]Roberto Gómez, Víctor H. Champac, Chuck Hawkins, Jaume Segura:
A modern look at the CMOS stuck-open fault. LATW 2009: 1-6 - [c41]Julio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura:
Stuck-Open Fault Leakage and Testing in Nanometer Technologies. VTS 2009: 315-320 - 2008
- [c40]José Luis Rosselló, Vincent Canals, Ivan de Paúl, Jaume Segura:
Using stochastic logic for efficient pattern recognition analysis. IJCNN 2008: 1057-1061 - 2007
- [c39]José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura:
Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. DATE 2007: 1271-1276 - [c38]X. Cano, Sebastià A. Bota, Ricardo Graciani Diaz, David Gascon, A. Herms, Albert Comerma, Jaume Segura, Lluís Garrido:
Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment. IOLTS 2007: 183-184 - 2006
- [c37]José Luis Rosselló, Jaume Segura:
A compact model to identify delay faults due to crosstalk. DATE 2006: 902-906 - [c36]Jaume Segura:
CMOS Testing at the End of the Roadmap: Challenges and Opportunities. DDECS 2006: 2 - [c35]José Luis Rosselló, Sebastià A. Bota, Vicent Canals, Ivan de Paúl, Jaume Segura:
A Fully CMOS Low-Cost Chaotic Neural Network. IJCNN 2006: 659-663 - [c34]José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura:
Leakage Power Characterization Considering Process Variations. PATMOS 2006: 66-74 - [c33]Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura:
Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. VTS 2006: 358-363 - 2005
- [c32]José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura:
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. DATE 2005: 206-211 - [c31]Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura:
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. DATE 2005: 464-465 - [c30]Chuck Hawkins, Jaume Segura:
The anatomy of nanometer timing failures. ETS 2005: 210-215 - [c29]Bartomeu Alorda, Sebastià A. Bota, Jaume Segura:
A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. IOLTS 2005: 177-182 - [c28]José Luis Rosselló, Sebastià A. Bota, Jaume Segura:
Compact Static Power Model of Complex CMOS Gates. PATMOS 2005: 348-354 - 2004
- [c27]José Luis Rosselló, Jaume Segura:
A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. DATE 2004: 954-961 - [c26]Bartomeu Alorda, Vicent Canals, Ivan de Paúl, Jaume Segura:
A BIST-based Charge Analysis for Embedded Memories. IOLTS 2004: 199-206 - [c25]Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi:
Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. ITC 2004: 1276-1284 - 2003
- [c24]Charles F. Hawkins, Ali Keshavarzi, Jaume Segura:
CMOS IC nanometer technology failure mechanisms. CICC 2003: 605-611 - [c23]Charles F. Hawkins, Ali Keshavarzi, Jaume Segura:
A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect. DFT 2003: 267- - [c22]Bartomeu Alorda, Jaume Segura:
An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing. IOLTS 2003: 178-182 - [c21]Bartomeu Alorda, Brad Bloechel, Ali Keshavarzi, Jaume Segura:
CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing. ITC 2003: 719-726 - [c20]José Luis Rosselló, Jaume Segura:
A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. PATMOS 2003: 51-59 - 2002
- [c19]Swarup Bhunia, Kaushik Roy, Jaume Segura:
A novel wavelet transform based transient current analysis for fault detection and localization. DAC 2002: 361-366 - [c18]Joan Font, J. Ginard, Eugeni Isern, Miquel Roca, Jaume Segura, Eugenio García:
A BICS for CMOS Opamps by Monitoring the Supply Current Peak. IOLTW 2002: 94-98 - [c17]Bartomeu Alorda, André Ivanov, Jaume Segura:
An Off-Chip Sensor Circuit for On-Line Transient Current Testing. IOLTW 2002: 192 - [c16]Jaume Segura, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins:
Parametric Failures in CMOS ICs - A Defect-Based Analysis. ITC 2002: 90-99 - [c15]Bartomeu Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura:
Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs. ITC 2002: 947-953 - [c14]Chuck Hawkins, Jaume Segura:
GHz Testing and Its Fuzzy Targets. ITC 2002: 1228 - [c13]José Luis Rosselló, Jaume Segura:
A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. PATMOS 2002: 219-228 - [c12]Jaume Segura, Vivek De, Ali Keshavarzi:
Challenges in Nanometric Technology Scaling: Trends and Projections. VTS 2002: 447-448 - 2001
- [c11]José Luis Rosselló, Jaume Segura:
Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. ICCAD 2001: 494- - [c10]Ivan de Paúl, M. Rosales, Bartomeu Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden:
Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. VTS 2001: 286-291 - 2000
- [c9]Bartomeu Alorda, Ivan de Paúl, Jaume Segura, T. Miller:
On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. IOLTW 2000: 87-91 - [c8]Rodrigo Picos, J. Colom, Miquel Roca, Eugeni Isern, Jaume Segura, Oscar Calvo, Eugenio García-Moreno:
Transient Current Monitoring Using a Current-to-Frequency Converter. LATW 2000: 54-58 - 1999
- [c7]Rodrigo Picos, Miquel Roca, Eugeni Isern, Jaume Segura, Eugenio García-Moreno:
Experimental results on BIC sensors for transient current testing. ETW 1999: 46-50 - [c6]Eugeni Isern, Miquel Roca, Jaume Segura:
Analyzing the Need for ATPG Targeting GOS Defects. VTS 1999: 420-425 - 1998
- [c5]Oscar Calvo, M. González, C. Romero, Eugenio García-Moreno, Eugeni Isern, Miquel Roca, Jaume Segura:
Integrated Cmos Linear Dosimeter. SBCCI 1998: 78-81 - 1995
- [c4]Antonio Rubio, Edmond Janssens, H. Casier, Joan Figueras, Diego Mateo, P. De Pauw, Jaume Segura:
A built-in quiescent current monitor for CMOS VLSI circuits. ED&TC 1995: 581-587 - [c3]Jaume Segura, Carol de Benito, Antonio Rubio, Charles F. Hawkins:
A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level. ITC 1995: 544-551 - [c2]Jaume A. Segura, Miquel Roca, Diego Mateo, Antonio Rubio:
An approach to dynamic power consumption current testing of CMOS ICs. VTS 1995: 95-100 - 1991
- [c1]Rosa Rodríguez-Montañés, Jaume A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio:
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. ITC 1991: 510-519
Informal and Other Publications
- 2024
- [i3]Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, Sebastià A. Bota, Jaume Segura:
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results. CoRR abs/2402.10917 (2024) - 2007
- [i2]Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura:
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. CoRR abs/0710.4733 (2007) - [i1]José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura:
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. CoRR abs/0710.4759 (2007)
Coauthor Index
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