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ORCIDDFT 2003: Boston, MA, USA
- 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings. IEEE Computer Society 2003, ISBN 0-7695-2042-1
Yield and Defects
- Xiaopeng Wang, Marco Ottavi
, Fabrizio Lombardi:
Yield Analysis of Compiler-Based Arrays of Embedded SRAMs. 3-10 - Tianxu Zhao, Xuchao Duan, Yue Hao, Peijun Ma:
Reliability Estimation Model of ICs Interconnect Based on Uniform Distribution of Defects on a Chip. 11-17 - Meng Lu, Yvon Savaria, Bing Qiu, Jacques Taillefer:
IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration. 18-25 - Dirk K. de Vries, Paul L. C. Simon:
Calibration of Open Interconnect Yield Models. 26-33 - Tao Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri:
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults. 34-
Optoelectronics
- Vijay K. Jain, Glenn H. Chapman:
Level-Hybrid Optoelectronic TESH Interconnection Network. 45-52 - Sunjaya Djaja, Glenn H. Chapman, Desmond Y. H. Cheung, Yves Audet:
Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS). 53-
Fault Analysis, Injection & Simulation
- Cecilia Metra, T. M. Mak, Daniele Rossi:
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. 63-70 - Monica Alderighi, Fabio Casini, Sergio D'Angelo, Marcello Mancini, A. Marmo, Sandro Pastore, Giacomo R. Sechi:
A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs. 71-78 - Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi:
CodSim -- A Combined Delay Fault Simulator. 79-
Test & Diagnosis
- Hiroshi Takahashi, Yasunori Tsugaoka, Hidekazu Ayano, Yuzo Takamatsu:
BIST Based Fault Diagnosis Using Ambiguous Test Set. 89-96 - Luca Schiano, Fabrizio Lombardi:
On the Test and Diagnosis of the Perfect Shuffle. 97-104 - Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri:
Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard. 105-
Current Test & Diagnosis
- Yassine Hariri, Claude Thibeault:
3DSDM: A 3 Data-Source Diagnostic Method. 117-123 - Marco S. Dragic, Martin Margala:
Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits. 124-131 - Sagar S. Sabade, D. M. H. Walker:
CROWNE: Current Ratio Outliers with Neighbor Estimator. 132-139 - Abhijit Prasad, D. M. H. Walker:
Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors. 140-
Test Generation & Application
- Hamidreza Hashempour, Fabrizio Lombardi:
ATE-Amenable Test Data Compression with No Cyclic Scan. 151-158 - Fengming Zhang, Young-Jun Lee, Thomas Kane, Luca Schiano, Mariam Momenzadeh, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi, Solomon Max, Phil Perkinson:
A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment. 159-166 - James Wingfield, Jennifer Dworak, M. Ray Mercer:
Function-Based Dynamic Compaction and its Impact on Test Set Sizes. 167-174 - Xiao Liu, Michael S. Hsiao:
Constrained ATPG for Broadside Transition Testing. 175-
Scan Design & Test
- Sandeep Bhatia:
Test Compaction by Using Linear-Matrix Driven Scan Chains. 185-190 - Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy:
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. 191-198 - Ching-Hwa Cheng:
Design Scan Test Strategy for Single Phase Dynamic Circuits. 199-
BIST
- Kedarnath J. Balakrishnan, Nur A. Touba:
Scan-Based BIST Diagnosis Using an Embedded Processor. 209-216 - C. V. Krishna, Nur A. Touba:
Hybrid BIST Using an Incrementally Guided LFSR. 217-224 - Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin:
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. 225-
Error Correcting Codes
- Parag K. Lala:
A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems. 235-241 - Haruhiko Kaneko, Eiji Fujiwara:
Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols. 242-249 - Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.:
Quadruple Time Redundancy Adders. 250-256 - Daniele Rossi, S. Cavallotti, Cecilia Metra:
Error Correcting Codes for Crosstalk Effect Minimization. 257-
Invited Talk
- Charles F. Hawkins, Ali Keshavarzi, Jaume Segura:
A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect. 267-
Analogue & Mixed Signal Test
- Yukiya Miura, Daisuke Kato:
Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation. 279-286 - Kranthi K. Pinjala, Bruce C. Kim:
An Approach for Selection of Test Points for Analog Fault Diagnosis. 287-294 - Jerzy J. Dabrowski:
BiST Model for IC RF-Transceiver Front-End. 295-302 - John Marty Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani:
A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits. 303-
Defect Tolerance and Testing
- Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi:
Thermal Management of High Performance Microprocessors. 313-319 - Ying Zhang, Krishnendu Chakrabarty:
Fault Recovery Based on Checkpointing for Hard Real-Time Embedded Systems. 320-327 - Eiko Sugawara, Masaru Fukushi, Susumu Horiguchi:
Fault Tolerant Multi-Layer Neural Networks with GA Training. 328-335 - Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante:
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. 336-343 - Konstantinos Rokas, Yiorgos Makris, Dimitris Gizopoulos:
Low Cost Convolutional Code Based Concurrent Error Detection in FSMs. 344-351 - Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi:
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. 352-360 - John Marty Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani:
An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals. 361-368 - Rafic A. Ayoubi, Haissam Ziade, Magdy A. Bayoumi:
Fault Tolerant Hopfield Associative Memory on Torus. 369-376 - Bogdan Nicolescu, Paul Peronnard, Raoul Velazco, Yvon Savaria:
Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study. 377-384 - Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng:
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip. 385-392 - Noh-Jin Park, Byoungjae Jin, K. M. George, Nohpill Park, Minsu Choi:
Regressive Testing for System-on-Chip with Unknown-Good-Yield. 393-400 - Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker. 401-408 - Mehdi Baradaran Tahoori:
Application-Dependent Testing of FPGA Interconnects. 409-416 - Cecilia Metra, Stefano Di Francescantonio, Martin Omaña:
Automatic Modification of Sequential Circuits for Self-Checking Implementation. 417-424 - Dan Zhao, Shambhu J. Upadhyaya, Martin Margala:
Control Constrained Resource Partitioning for Complex SoCs. 425-432 - Kartik Mohanram, Nur A. Touba:
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. 433-
FPGA & Memory Test
- Cristiana Bolchini, Fabio Salice, Donatella Sciuto, R. Zavaglia:
An Integrated Design Approach for Self-Checking FPGAs. 443-450 - Bai Hong Fang, Nicola Nicolici:
Power-Constrained Embedded Memory BIST Architecture. 451-458 - Michael Nicolaidis, Nadir Achouri, Lorena Anghel:
A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities. 459-466 - Rob Aitken, Neeraj Dogra, Dhrumil Gandhi, Scott Becker:
Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator. 467-474 - Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott:
An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture. 475-
Design Verification & Synthesis
- Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali:
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. 485-492 - Lorena Anghel, Raoul Velazco, S. Saleh, S. Deswaertes, A. El Moucary:
Preliminary Validation of an Approach Dealing with Processor Obsolescence. 493-
SoC & Core Test
- Gang Zeng, Hideo Ito:
Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core. 503-510 - Vikram Iyengar, Anshuman Chandra:
A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design. 511-518 - Adam B. Kinsman, Jonathan I. Hewitt, Nicola Nicolici:
Embedded Compact Deterministic Test for IP-Protected Cores. 519-
System Reliability
- Fulvio Corno, Simonluca Tosato, Paolo Gabrielli:
System-Level Analysis of Fault Effects in an Automotive Environment. 529-536 - Julio Pérez, Matteo Sonza Reorda, Massimo Violante:
Dependability Analysis of CAN Networks: An Emulation-Based Approach. 537-
Fault Tolerance
- Toshinori Sato:
Exploiting Instruction Redundancy for Transient Fault Tolerance. 547-554 - Yung-Yuan Chen, Shi-Jinn Horng, Hung-Chuan Lai:
An Integrated Fault-Tolerant Design Framework for VLIW Processors. 555-562 - Sobeeh Almukhaizim, Yiorgos Makris:
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code. 563-570 - Vinu Vijay Kumar, John C. Lach:
Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area Overhead. 571-
Soft Errors
- Olga Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Soft-Error Detection Using Control Flow Assertions. 581-588 - Bogdan Nicolescu, Yvon Savaria, Raoul Velazco:
SIED: Software Implemented Error Detection. 589-596 - Atul Maheshwari, Israel Koren, Wayne P. Burleson:
Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits. 597-
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