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ORCID11th SBCCI 1998: Rio de Janiero, Brazil
- Proceedings of the 11th Annual Symposium on Integrated Circuits Design, SBCCI 1998, Rio de Janiero, Brazil, September 30 - October 2, 1998. IEEE Computer Society 1998, ISBN 978-0-8186-8704-4
- Claudionor José Nunes Coelho Jr., Diógenes Cecilio da Silva Jr., Antônio Otávio Fernandes:
Hardware-Software Codesign of Embedded Systems. 2-9 - R. Velazco:
The ALFA-HUERTA Project. 10 - Simon D. Haynes, Antonio B. Ferrari, Peter Y. K. Cheung:
Algorithms and Structures for Reconfigurable Multiplication Units. 13 - Panel Statement. 15-18
- F. França L. Malta, C. Amorim:
Reconfigurable Hardware for Tomographic Processing. 19-24 - Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner:
Internet-based Training of Reconfigurable Technologies. 25-30 - Ricardo Reis, Leandro Soares Indrusiak
:
Microelectronics Education using WWW and CAD Tools. 31-37 - Claudionor Coelho, A. Araújo R. Tavare, Antônio Otávio Fernandes:
Implementation of an Edge Detection Algorithm in a Reconfigurable Computing System. 38-41 - Ernesto Damiani, Andrea G. B. Tettamanzi, Valentino Liberali:
Automatic Synthesis of Hashing Function Circuits using Evolutionary Techniques. 42-45 - Valery Sklyarov, Nuno Lau, Arnaldo S. R. Oliveira, Andreia Melo, Konstantin Kondratjuk, António de Brito Ferrari, Ricardo Sal Monteiro, Iouliia Skliarova:
Synthesis Tools and Design Environment for Dynamically Reconfigurable FPGAs. 46-50 - Raimund Ubar, Dominique Borrione:
Generation of Tests for the Localization of Single Gate Design Errors in Combinational Circuits using the Stuck-at Fault Model. 51-54 - Fabian Vargas, Eduardo Bezerra, A. Terroso, Daniel Barros Jr.:
Reliability Verification of Fault-Tolerant Systems Design based on Mutation Analysis. 55-59 - Manfred Glesner, Andreas Kirschbaum:
State-of-the-Art in Rapid Prototyping. 60-66 - Michel Renovell:
SRAM-based FPGAs: A Structural Test Approach. 67-73 - José Luis Cura, Dinis M. Santos:
A Novel 12-Bit, 3(s, Integrating-Type CMOS Analog-to-Digital Converter. 74-77 - Oscar Calvo, M. González, C. Romero, Eugenio García-Moreno, Eugeni Isern, Miquel Roca, Jaume Segura:
Integrated Cmos Linear Dosimeter. 78-81 - Rui L. Aguiar:
A Physical Layer Controller for Wireless Infrared Networks. 82-85 - Denis Archambaud, P. Gaglione:
A Versatile, Low-Power Platform for PHS Silicon Integration. 86-90 - Vanderlei Moraes Rodrigues, Flávio Rech Wagner:
A Temporal Logic for Data-Flow VHDL. 91-94 - David Déharbe, Subash Shankar, Edmund M. Clarke:
Formal Verification of VHDL ¾ The Model Checker CV. 95-98 - Dominique Borrione, Julia Dushina, Laurence Pierre:
Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis. 99-102 - Edelweis Helena Ache Garcez, Wolfgang Rosenstiel:
CVF ¾ Coverification Framework. 103-107 - Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije:
VHDL Models for High Level Synthesis of Fuzzy Logic Controllers. 108-111 - Francisco Assis M. do Nascimento, Wolfgang Rosenstiel:
A Co-Synthesis Approach based on Symbolic Reachability Analysis. 112-115 - Leandro Soares Indrusiak, Ricardo Reis:
A Case Study for a WWW based CAD Framework. 116-120 - R. Brannen, Hassan O. Elwan, Mohammed Ismail:
Linear MOSFET-C Integrators using a Single Triode Region MOS Resistance. 121-124 - Ricardo Salem Zebulum, Marco Aurélio Pacheco, Marley M. B. R. Vellasco:
Synthesis of CMOS Operational Amplifiers through Genetic Algorithms. 125-128 - Fernando A. P. Barúqui, Sanjit K. Mitra:
Efficient IC Design of SC Decimation Filters. 129-133 - Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh:
MorphoSys: A Reconfigurable Architecture for Multimedia Applications. 134-140 - Franco Maloberti, Valentino Liberali, Piero Malcovati:
Signal Processing for Smart Sensors. 141-149 - J. Alcântara, V. C. Alves, E. Filho:
Designing the Dispatch Stage of a Superscalar Microprocessor. 150-153 - Júlio Salek Aude, M. T. Young, Gerson Bronstein:
A High-Performance Switching Element for a Multistage Interconnection Network. 154-157 - S. Salomão, V. Alves, E. Filho:
A Two-level Pipelined Implementation of the IDEA Cryptographic Algorithm. 158-161 - Raoul Velazco, Ph. Cheynet, R. Ecoffet:
Operation in Space of Artificial Neural Networks Implemented by Means of a Dedicated Architecture based on a Transputer. 162-166 - Gabriel Parmegianni Jahn, Luigi Carro:
A Non-Linear Adaptive Filter for Sensor and Amplifier Linearization. 167-170 - Oscar Calvo, Miquel Roca:
Low-Power Fully-Testable Flow Meter in CMOS ASIC. 171-174 - Marcelo Lubaszewski, Michel Renovell, Salvador Mir, Florence Azaïs, Yves Bertrand:
A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing. 175-178 - Arturo Sarmiento-Reyes, Miguel Ángel Gutiérrez de Anda, Víctor H. Champac:
A Graph-Oriented CAD Tool for Establishing the Topological Diagnostic Conditions of Analogue Circuits. 179-183 - M. Marzouki:
France-Brazil Cooperative Actions. 184-186 - Fabio A. Salazar, Júlio C. G. Pimentel, Marco Aurélio Pacheco, Marley M. B. R. Vellasco:
Micro Power CMOS Analog Cells. 187-190 - Tuna B. Tarim, Mohammed Ismail, H. Hakan Kuntman:
Statistical Design of a Multiplier using a Low Power Square-Law CMOS Analog Cell. 191-194 - Chi-Hung Lin, Tales C. Pimenta, Mohammed Ismail:
A Low-Voltage CMOS Exponential Function Circuit for AGC Applications. 195-199 - E. Charry, J. López R. Rein, Roberto Sarmiento:
Circuits for Low Power Consumption in GaAs Technology. 200-203 - J. Güntzel F. de Lim, Luigi Carro:
Improving Logic Density of QCL Masterslices by using Universal Logic Gates. 204-207 - José Luís Güntzel, Ana Cristina Medina Pinto, Fernando Moraes, Ricardo Reis:
An Improved Path Enumeration Method Considering Different Fall and Rise Gate Delays. 208-212 - A. Reis, R. Reis, M. Robert:
Topological Parameters for Library Free Technology Mapping. 213-216 - Ricardo P. Jacobi:
LogosPGA: Synthesis System for LUT Devices. 217-220 - Valery Sklyarov:
Logic Synthesis of Reconfigurable Control Circuits based on Mutually Exclusive Reprogrammable Elements. 221-225 - Sudhakar Muddu, Egino Sarto, M. Hofmann, A. Bashteen:
Repeater and Interconnect Strategies for High-Performance Physical Designs. 226-231 - M. Vaz, R. Natalizi:
A Tool to Design Circuits with Statistics. 232-325 - A. Carvalho, Fadi J. Kurdahi, Sani R. Nassif:
IR and Thermal Estimation Tools, with Applications to the GUTS 1GHz Processor. 236-239 - Enrico Malavasi, Edoardo Charbon, Bogdan G. Arsintescu, William H. Kao:
A Constraint Management System for IC Physical Design. 240-243 - José Roberto de A. Amazonas, Marius Strum, Wang Jiang Chau:
Exploring Concurrency in Data Path Functional Units BIST Plan Optimization: A Study-Case. 244-248
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