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"A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors."

Gabriel Torrens et al. (2019)

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DOI: 10.1109/TETC.2017.2721932

access: closed

type: Journal Article

metadata version: 2022-10-02

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Gabriel Torrens, Bartomeu Alorda, Cristian Carmona, Daniel Malagón-Periánez, Jaume Segura, Sebastià A. Bota:
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors. IEEE Trans. Emerg. Top. Comput. 7(3): 447-455 (2019)

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